aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu/soc15.h
Commit message (Collapse)AuthorAgeFilesLines
* drm/amdgpu: use common function to map ip for aqua_vanjaramLikun Gao2025-06-241-1/+0
| | | | | | | | | | Transfer to use function amdgpu_ip_map_init to map ip instance for aqua_vanjaram instead of operation on different ASIC. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add macro to calculate offset with instanceSunil Khatri2024-07-271-0/+4
| | | | | | | | | | | | | | | Add macro definition which calculate offset of the register with index override. This is useful in case when there is an array of registers which is common for all instances. To read registers in that case it is easy to define registers once and the index value is manually passed to calculate proper offset of register for each instance. Signed-off-by: Sunil Khatri <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add support of gfx10 register dumpSunil Khatri2024-04-261-0/+2
| | | | | | | | | | Adding gfx10 gc registers to be used for register dump via devcoredump during a gpu reset. Signed-off-by: Sunil Khatri <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Read aquavanjaram PCIE register stateLijo Lazar2023-11-291-0/+4
| | | | | | | | Add support to read aqua vanjaram PCIE register state Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Add soc config init for GC9.4.3 ASICsLijo Lazar2023-06-091-0/+1
| | | | | | | | | | | | | Add function to initialize soc configuration information for GC 9.4.3 ASICs. Use it to map IPs and other SOC related information once IP configuration information is available through discovery. For GC9.4.3 compute partition related callbacks are initialized as part of configuration init. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add helpers to access registers on different AIDsLe Ma2023-06-091-0/+1
| | | | | | | | | | | | SMN address which is larger than 32bit has different indications through bit[34:32] on different AIDs. v2: put smn addressing of different AIDs into asic specific place v3: change to ext_id/ext_offset naming Signed-off-by: Le Ma <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: switch to aqua_vanjaram_doorbell_index_initLe Ma2023-06-091-0/+1
| | | | | | | | New doorbell index assignment is used by aqua_vanjaram. Signed-off-by: Le Ma <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Add IP instance map for aqua vanjaramLijo Lazar2023-06-091-0/+1
| | | | | | | | | | | | | | Add XCC logical to physical instance map for aqua vanjaram v2: Keep look up table only for required IPs, for others return default mapping (Felix). Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add xcc index argument to soc15_grbm_selectLe Ma2023-04-181-1/+1
| | | | | | | | | | To support grbm select for multiple XCD case. v2: unify naming style Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: drop soc15_set_ip_blocks()Alex Deucher2021-10-201-1/+0
| | | | | | | | No longer used since IP enumeration is now driven by amdgpu IP discovery code. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/soc15: export common IP functionsAlex Deucher2021-10-041-0/+2
| | | | | | | So they can be driven by IP discovery table. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: make soc15_common_ip_funcs staticAlex Deucher2021-09-231-2/+0
| | | | | | | It's not used outside of soc15.c Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: refine ras codes for GC utc of aldebaranDennis Li2021-03-241-1/+1
| | | | | | | | | The bank number of both VML2 and ATCL2 are changed to 8, so refine related codes to avoid defining long name arrays. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add ras support for gfx of aldebaranDennis Li2021-03-241-0/+11
| | | | | | | | | | | | | add edc counter/status reset and query functions for gfx block of aldebaran. v2: change to clear edc counter explicitly aldebaran hardware will not clear edc counter after driver reading them, so driver should clear them explicitly. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add register base init for aldebaran (v2)Le Ma2021-03-101-0/+1
| | | | | | | | | | | | | v1: add aldebaran_reg_base_init function to initialize register base for aldebaran (Le) v2: update VCN HWIP and initialize base offset (James) Signed-off-by: Le Ma <[email protected]> Signed-off-by: James Zhu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: request init data in virt detectionWenhui Sheng2020-07-021-0/+1
| | | | | | | | | | Move request init data to virt detection func, so we can insert request full access between request init data and set ip blocks. Signed-off-by: Wenhui Sheng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: revise RLCG access pathMonk Liu2020-03-161-0/+7
| | | | | | | | | | | | | | | | what changed: 1)provide new implementation interface for the rlcg access path 2)put SQ_CMD/SQ_IND_INDEX to GFX9 RLCG path to let debugfs's reg_op function can access reg that need RLCG path help now even debugfs's reg_op can used to dump wave. tested-by: Monk Liu <[email protected]> tested-by: Zhou pengju <[email protected]> Signed-off-by: Zhou pengju <[email protected]> Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10changzhu2019-11-221-2/+2
| | | | | | | | | | | | | | | | It may lose gpuvm invalidate acknowldege state across power-gating off cycle. To avoid this issue in gmc9/gmc10 invalidation, add semaphore acquire before invalidation and semaphore release after invalidation. After adding semaphore acquire before invalidation, the semaphore register become read-only if another process try to acquire semaphore. Then it will not be able to release this semaphore. Then it may cause deadlock problem. If this deadlock problem happens, it needs a semaphore firmware fix. Signed-off-by: changzhu <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: define soc15_ras_field_entry for reuseDennis Li2019-11-221-0/+12
| | | | | | | | | | | | | The struct soc15_ras_field_entry will be reused by other IPs, such as mmhub and gc v2: rename ras_subblock_regs to gc_ras_fields_vg20, because the future asic maybe have a different table. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: change to query the actual EDC counterDennis Li2019-10-151-0/+2
| | | | | | | | | | For the potential request in the future, change to query the actual EDC counter. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: dynamically initialize IP offset for ArcturusLe Ma2019-07-181-0/+1
| | | | | | | | Add support for the IP offsets on Arcturus. Signed-off-by: Le Ma <[email protected]> Acked-by: Snow Zhang < [email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: avoid to use SOC15_REG_OFFSET in static array for navi10Hawking Zhang2019-06-211-0/+8
| | | | | | | | Move to the header file. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Fixed missing to clear some EDC countJames Zhu2019-06-111-0/+2
| | | | | | | | | | EDC counts are related to instance and se. They are not the same for different type of EDC. EDC clearing are changed to base on individual EDC's instance and SE number. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add gfx9 gpr EDC workaround when RAS is enabledJames Zhu2019-05-241-0/+10
| | | | | | | | | | When RAS is enabled, initializes the VGPRs/LDS/SGPRs and resets EDC error counts. This is done in late_init, before RAS TA GFX enable. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Doorbell layout for vega20 and future asicOak Zeng2018-11-281-0/+1
| | | | | | | | | | | | This introduces new doorbell layout for vega20 and future asics v2: Use enum definition instead of hardcoded value Signed-off-by: Oak Zeng <[email protected]> Suggested-by: Felix Kuehling <[email protected]> Suggested-by: Alex Deucher <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Vega10 doorbell index initializationOak Zeng2018-11-281-0/+1
| | | | | | | | | | | v2: Use enum definition instead of hardcoded value v3: Remove unused enum definition Signed-off-by: Oak Zeng <[email protected]> Suggested-by: Felix Kuehling <[email protected]> Suggested-by: Alex Deucher <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Add nbio 7.4 support for vega20 (v3)Feifei Xu2018-08-271-0/+1
| | | | | | | | | | | | | Some register offset in nbio v7.4 are different with v7.0. We need a seperate nbio_v7_4.c for vega20. v2: fix doorbell range for sdma (Alex) v3: squash in static fix (kbuild test robot) Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/soc15: dynamic initialize ip offset for vega20Feifei Xu2018-05-171-0/+1
| | | | | | | | | | | Vega20 need a seperate vega20_reg_init.c due to ip base offset difference. Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: move waiting for VM flush into gmc_v9_0_emit_flush_gpu_tlbChristian König2018-02-191-1/+2
| | | | | | | | | Keep that at a common place instead of spread over all engines. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add PASID mapping for GMC v9Christian König2018-02-191-1/+1
| | | | | | | | This way we can see the PASID in VM faults. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: implement gmc_v9_0_emit_flush_gpu_tlbChristian König2018-02-191-0/+2
| | | | | | | | Unify tlb flushing for gmc v9. Signed-off-by: Christian König <[email protected]> Acked-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const arrayShaoyun Liu2017-12-081-0/+18
| | | | | | | | Handle dynamic offsets correctly in static arrays. Acked-by: Christian Konig <[email protected]> Signed-off-by: Shaoyun Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Dynamic initialize IP base offsetShaoyun Liu2017-12-081-0/+2
| | | | | | | | | | The base offsets of the IP blocks may change across asics even though the relative register offsets are the same for an IP. Handle this dynamically. Acked-by: Christian Konig <[email protected]> Signed-off-by: Shaoyun Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: apply nbio7 for Raven (v3)Chunming Zhou2017-05-241-0/+1
| | | | | | | | | | | | | nbio handles misc bus io operations. Handle differences between different nbio bus versions. v2: switch checks from RAVEN to APU (Alex) squash in raven rev id fetch squash in fix uninitalized hdp flush reg index for raven v3: add some missed RAVEN to APU checks (Alex) Signed-off-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add common soc15 headersKen Wang2017-03-301-0/+35
These are used by various IP modules. Acked-by: Christian König <[email protected]> Signed-off-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
generated by cgit (git 2.51.2) at 2025-11-30 17:48:47 +0000