diff options
| author | James Zhu <[email protected]> | 2019-04-05 19:31:47 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2019-05-24 17:20:50 +0000 |
| commit | 5326ad54c5ef01a828cf5a942f6fdbf204ef7d3f (patch) | |
| tree | 95b5e837d320db447710126e301c96638a813c52 /drivers/gpu/drm/amd/amdgpu/soc15.h | |
| parent | drm/amdgpu: add EDC counter register (diff) | |
| download | kernel-5326ad54c5ef01a828cf5a942f6fdbf204ef7d3f.tar.gz kernel-5326ad54c5ef01a828cf5a942f6fdbf204ef7d3f.zip | |
drm/amdgpu: add gfx9 gpr EDC workaround when RAS is enabled
When RAS is enabled, initializes the VGPRs/LDS/SGPRs and
resets EDC error counts. This is done in late_init, before
RAS TA GFX enable.
Signed-off-by: James Zhu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h index a66c8bfbbaa6..06f39f5bbf76 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h @@ -42,8 +42,18 @@ struct soc15_reg_golden { u32 or_mask; }; +struct soc15_reg_entry { + uint32_t hwip; + uint32_t inst; + uint32_t seg; + uint32_t reg_offset; + uint32_t reg_value; +}; + #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg +#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset) + #define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \ { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask } |