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authorMonk Liu <[email protected]>2020-03-10 12:28:45 +0000
committerAlex Deucher <[email protected]>2020-03-16 20:17:55 +0000
commit2e0cc4d48b91a856a34027b093306c01c45d3a38 (patch)
treeb9e9cd5e6583891e88620fec6f9d40794544fe07 /drivers/gpu/drm/amd/amdgpu/soc15.h
parentdrm/scheduler: fix inconsistent locking of job_list_lock (diff)
downloadkernel-2e0cc4d48b91a856a34027b093306c01c45d3a38.tar.gz
kernel-2e0cc4d48b91a856a34027b093306c01c45d3a38.zip
drm/amdgpu: revise RLCG access path
what changed: 1)provide new implementation interface for the rlcg access path 2)put SQ_CMD/SQ_IND_INDEX to GFX9 RLCG path to let debugfs's reg_op function can access reg that need RLCG path help now even debugfs's reg_op can used to dump wave. tested-by: Monk Liu <[email protected]> tested-by: Zhou pengju <[email protected]> Signed-off-by: Zhou pengju <[email protected]> Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/soc15.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
index d0fb7a67c1a3..b03f950c486c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -42,6 +42,13 @@ struct soc15_reg_golden {
u32 or_mask;
};
+struct soc15_reg_rlcg {
+ u32 hwip;
+ u32 instance;
+ u32 segment;
+ u32 reg;
+};
+
struct soc15_reg_entry {
uint32_t hwip;
uint32_t inst;