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* drm/amd/display: Clear the CUR_ENABLE register on DCN314 w/out DPP PGIvan Lipski2025-08-291-0/+3
| | | | | | | | | | | | | | | | | | [Why&How] ON DCN314, clearing DPP SW structure without power gating it can cause a double cursor in full screen with non-native scaling. A W/A that clears CURSOR0_CONTROL cursor_enable flag if dcn10_plane_atomic_power_down is called and DPP power gating is disabled. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4168 Reviewed-by: Sun peng (Leo) Li <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> (cherry picked from commit 645f74f1dc119dad5a2c7bbc05cc315e76883011) Cc: [email protected]
* drm/amd/display: Fix BT2020 YCbCr limited/full range inputIlya Bakoulin2025-02-191-1/+5
| | | | | | | | | | | | | | | | | [Why] BT2020 YCbCr input is not handled properly when full range quantization is used and limited range is not supported at all. [How] - Add enums for BT2020 YCbCr limited/full range - Add limited range CSC matrix Reviewed-by: Krunoslav Kovac <[email protected]> Signed-off-by: Ilya Bakoulin <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Robert Mader <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add simple struct doc to remove doc build warningRodrigo Siqueira2024-07-161-5/+17
| | | | | | | | | | | | | | | | | | | This commit is a part of a series that addresses the following build warning for opp: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.h:1: warning: no structured comments found ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h:1: warning: no structured comments found This commit fixes this issue by adding a simple kernel-doc to a struct in the opp.h and the dpp.h files. Cc: Alex Deucher <[email protected]> Acked-by: Alex Deucher <[email protected]> Reported-by: Stephen Rothwell <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add misc DC changes for DCN401Aurabindo Pillai2024-04-261-0/+4
| | | | | | | | Add miscellaneous changes to enable DCN401 init Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Remove plane and stream pointers from dc scratchAlvin Lee2024-03-271-1/+1
| | | | | | | | | | | | [Why&How] Remove several plane and stream pointers from dc for code refactoring. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Documentation/gpu: Add kernel doc entry for DPPRodrigo Siqueira2024-01-291-0/+25
| | | | | | | | | | | | | | | | | This commit introduces basic DPP information and the struct scan for code documentation. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Hamza Mahfooz <[email protected]> Cc: Christian König <[email protected]> Cc: Aurabindo Pillai <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: fill up DCN3 DPP color stateMelissa Wen2024-01-221-0/+8
| | | | | | | | | | | | | DCN3 DPP color state was uncollected and some state elements from DCN1 doesn't fit DCN3. Create new elements according to DCN3 color caps and fill them up for DTN log output. rfc-v2: - fix reading of gamcor and blnd gamma states - remove gamut remap register in favor of gamut remap matrix reading Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: read gamut remap matrix in fixed-point 31.32 formatMelissa Wen2024-01-221-0/+3
| | | | | | | | | | Instead of read gamut remap data from hw values, convert HW register values (S2D13) into a fixed-point 31.32 matrix for color state log. Change DCN10 log to print data in the format of the gamut remap matrix. Signed-off-by: Melissa Wen <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add dpp_get_gamut_remap functionsHarry Wentland2024-01-221-0/+3
| | | | | | | | | | | We want to be able to read the DPP's gamut remap matrix. v2: - code-style and doc comments clean-up (Melissa) Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Format input and output CSC matrixHarry Wentland2023-02-281-22/+32
| | | | | | | | | | | | | | | | | Format the input and output CSC matrix so they look like 3x4 matrixes. This will make parsing them much easier and allows us to quickly spot potential mistakes. Signed-off-by: Harry Wentland <[email protected]> Cc: Pekka Paalanen <[email protected]> Cc: Sebastian Wick <[email protected]> Cc: [email protected] Cc: Joshua Ashton <[email protected]> Cc: [email protected] Cc: [email protected] Reviewed-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add YCBCR2020 coefficients to CSC matrixRodrigo Siqueira2022-11-231-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When some of the IGT tests are executed in DCN31, it is possible to see multiple occurrences of this warning: WARNING: CPU: 9 PID: 3482 at drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dcn30/dcn30_dpp.c:154 dpp3_program_post_csc+0x196/0x220 [amdgpu] [..] PU: 9 PID: 3482 Comm: amd_hdr Tainted: G W 5.18.0+ #3 IP: 0010:dpp3_program_post_csc+0x196/0x220 [amdgpu] [..] all Trace: <TASK> dpp3_cnv_setup+0x5d9/0x5f0 [amdgpu] ? dcn20_blank_pixel_data+0x30a/0x330 [amdgpu] dcn20_program_pipe+0x259/0xb40 [amdgpu] ? offset_to_id+0x1b0/0x1c0 [amdgpu] dcn20_program_front_end_for_ctx+0x36a/0x450 [amdgpu] commit_planes_for_stream+0x8eb/0x13e0 [amdgpu] This commit fix the above issue by adding YCBCR2020 coefficients to the DPP Color Space Converter (CSC) matrix. Reviewed-by: Nawwar Ali <[email protected]> Acked-by: Brian Chang <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Use the same cursor info across featuresMax Tseng2022-10-101-0/+4
| | | | | | | | | | | | | | | Since different features would need to update cursor registers, However, they would use different approaches. To unify varied methods, this refactor is implemented the same update cursor info method for current varied features. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Max Tseng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Defer GAMCOR and DSCL power down sequence to vupdateMichael Strauss2021-10-281-0/+2
| | | | | | | | | | | | | | | | | | | | [WHY] Every other CM LUT power down sequence is deferred to next vupdate as memory powerdown updates immediately while selecting LUTs is double buffered. Previous update to defer LUT power down missed GAMCOR and DSCL, causing some visible flicker when entering/exiting fullscreen video playback. [HOW] Update dpp deferred update loop to check for valid DPPs in res_pool instead of referencing dcn_ip which turns out to not be populated during runtime. Move GAMCOR and DSCL powerdown to dpp deferred updates. Reviewed-by: Haonan Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Defer LUT memory powerdown until LUT bypass latchesMichael Strauss2021-09-291-0/+12
| | | | | | | | | | | | | | | | | | | | | [WHY] Blnd, 3dlut, and shaper LUT select registers are double buffered, however their accompanying LUT memory shutdown registers are not. As a result, shutting down LUT memory immediately after setting a block to bypass causes corruption as bypass only happens at next Vupdate. [HOW] Re-enable mem low power for CM block Force optimization on next flip and disable LUT memory during optimization sequence if LUT select field is then set to bypass v2: squash in CONFIG_DRM_AMD_DC_DCN fix (Alex) Reviewed-by: Eric Yang <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Document set RECOUT operationRodrigo Siqueira2021-05-201-0/+6
| | | | | | | | | | | | | | During the investigation on how to add visual confirmation on top of the planes used by DCN, it becomes evident that the lack of information in the code makes this work unnecessarily complicated. This commit introduces a set of documentation related to the RECOUT operation in order to make it easy for developers to navigate this set of functions. Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display/dc/inc/hw/dpp: Mark 'dpp_input_csc_matrix' as __maybe_unusedLee Jones2020-12-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | 'dpp_input_csc_matrix' is used by some, but not all source files which include dpp.h. Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/inc/hw/dpp.h:50:42: warning: ‘dpp_input_csc_matrix’ defined but not used [-Wunused-const-variable=] NB: Snipped lots of these for brevity Cc: Harry Wentland <[email protected]> Cc: Leo Li <[email protected]> Cc: Alex Deucher <[email protected]> Cc: "Christian König" <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Lee Jones <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)Alex Deucher2020-11-041-2/+0
| | | | | | | | | | Avoids confusion in configurations. v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code Reviewed-by: Luben Tuikov <[email protected]> (v1) Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add DCN3 DPPBhawanpreet Lakha2020-07-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to program the DCN3 DPP (Multiple pipe and plane combine) HW Blocks: +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix double buffering in dcn2 ICSCNoah Abradjian2020-01-161-0/+20
| | | | | | | | | | | | | | | | | | [Why] When rapidly adjusting video brightness, screen tearing was observed. This was due to overwritten values in ICSC registers. In dcn10, this issue had been fixed by implementing double buffering via alternating ICSC modes. However, the second register set used in dcn1 doesn't exist in dcn2. [How] Create new program_input_csc for dcn20. Use ICSC_B registers instead of COMA registers as second set. Signed-off-by: Noah Abradjian <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTEDBhawanpreet Lakha2019-11-131-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] DCN2 and DSC are stable enough to be build by default. So drop the flags. [How] Remove them using the unifdef tool. The following commands were executed in sequence: $ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' $ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' In addition: * Remove from kconfig, and replace any dependencies with DCN1_0. * Remove from any makefiles. * Fix and cleanup NV defninitions in dal_asic_id.h * Expand DCN1 ifdef to include DCN2 code in the following files: * clk_mgr/clk_mgr.c: dc_clk_mgr_create() * core/dc_resources.c: dc_create_resource_pool() * dce/dce_dmcu.c: dcn20_*lock_phy() * dce/dce_dmcu.c: dcn20_funcs * dce/dce_dmcu.c: dcn20_dmcu_create() * gpio/hw_factory.c: dal_hw_factory_init() * gpio/hw_translate.c: dal_hw_translate_init() Signed-off-by: Leo Li <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add Cursor Degamma logic for DCN2Bayan Zabihiyan2019-08-231-1/+1
| | | | | | | | | | | | | | [Why] We need to have the ability to to tell us set degamma on the cursor. [How] Pass a flag down to register programming that tells us if the current surface format needs cursor degamma. Signed-off-by: Bayan Zabihiyan <[email protected]> Reviewed-by: Krunoslav Kovac <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add CM_BYPASS via debug optionQingqing Zhuo2019-07-181-0/+1
| | | | | | | | | | | | | | [Why] bypass CM block and MPC ogam for debug or triage use. [How] create a new flag cm_bypass_mode, which will set both CM_CONTROL and MPCC_OGAM_MODE to bypass when set to 1. Signed-off-by: Qingqing Zhuo <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add DCN2 DPPHarry Wentland2019-06-211-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to program the DCN2 DPP (Multiple pipe and plane combine) HW Blocks: +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Implement CM dealpha and bias interfacesGary Kattan2019-05-311-0/+17
| | | | | | | | | | | Add vtable entries for de-alpha and bias color management interfaces. Move piece-wise transfer function registers to a helper list for future reuse. Signed-off-by: Gary Kattan <[email protected]> Reviewed-by: Nevenko Stupar <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix runtime errors for diagnostic testsEric Bernstein2019-01-141-0/+5
| | | | | | | | | | | | | | | 1) Rename and make public definition of input CSC matrix struct. 2) Make wm_read_state() function an interface of hubbub, and check if watermark registers exist before read/write to them. 3) Check if OTG_INTERLACE_CONTROL register exists before updating 4) Add dummy functions for set_input/output_transfer function to avoid errors due to differences in CM registers. 5) Added missing register field definition in header file Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: fix PIP bugs on Dal3Gloria Li2018-08-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | [Why] There are outstanding bugs for PIP in Dal3: -Crash when toggling PIP visibility -Global Alpha is not working, Adjusting global alpha doesn’t have an effect -Cursor is not working with pip plane and pipe splits -One flash occurs when cursor enters PIP plane from top/bottom -Crash when moving PIP plane off the screen [How] Resolve divide by 0 error Implement global alpha Program cursor on all pipes Add dst rects' x and y offests into cursor position Disable cursor when it is beyond bottom/top edge Signed-off-by: Gloria Li <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Print DPP DTN log info only for enabled pipesNikola Cornij2018-08-271-0/+1
| | | | | | | | | | | | | | | | | | | [why] There is currently a dependency on the order in which tests are executed. This is because the non-relevant state info is being printed, which results in the output based on the state from the previous test. [how] Print DPP DTN log only if the pipe is enabled. In addition to the affected per-submission DTN golden logs, included in this change is also DTN golden log update for pre-submission tests. The other DTN golden logs affected by this change will be updated upon nightly test run (which will generate the updated DTN logs). Signed-off-by: Nikola Cornij <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Refactor SDR cursor boosting in HDR modeKrunoslav Kovac2018-07-161-0/+3
| | | | | | | | | | | | | | | | | | [Why] Cursor boosting is done via CNVC_CUR register which is DPP, not HUBP Previous commit was implementing it in HUBP functions, and also breaking diags tests. [How] 1. Undo original commit as well as Eric's diags test fix, almost completely 2. Move programming to DPP and call via new dc_stream function 3. Also removing cur_rom_en from dpp_cursor_attributes and programming as part of normal cursor attributes as it depends on cursor color format Signed-off-by: Krunoslav Kovac <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add some DTN logs for input and output tfAnthony Koo2018-05-151-0/+16
| | | | | | | Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: csc_transform to dc_csc_transformAnthony Koo2018-05-151-1/+1
| | | | | | | | Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: use HW hdr mult for brightness boostKrunoslav Kovac2018-03-141-0/+3
| | | | | | | | | | | | | | | In MPO scenario when playing SDR clip in HDR desktop mode, Win is boosting desktop and requests driver to boost MPO. But driver boosting is currently done in regamma which is stream property and thus shared between grph and video. Redesigning the boosting in RV: use CM_HDR_MULT register which was added for this scenario. It also has the benefit that it can be done in HIRQL. Signed-off-by: Krunoslav Kovac <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Handle HDR use cases.Vitaly Prosyak2018-03-051-0/+2
| | | | | | | | | | | | | Implementation of de-gamma, blnd-gamma, shaper and 3d lut's. Removed memory allocations in transfer functions. Refactor color module. Signed-off-by: Vitaly Prosyak <[email protected]> Reviewed-by: Krunoslav Kovac <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Move dpp reg access from hwss to dpp module.Yongqiang Sun2018-02-191-0/+5
| | | | | | | Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Declare and share color space types for dcn'sVitaly Prosyak2017-12-201-1/+1
| | | | | | | Signed-off-by: Vitaly Prosyak <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: CNVC pseudocode review follow upYue Hin Lau2017-12-141-1/+1
| | | | | | | Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: renaming dpp function to follow naming conventionYue Hin Lau2017-12-061-14/+14
| | | | | | | Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Yuehin Lau <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: call set csc_default if enable adjustment is falseYue Hin Lau2017-12-061-1/+1
| | | | | | | Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: cache pwl params and scl_data to avoid extra programmingDmytro Laktyushkin2017-12-061-5/+3
| | | | | | | | | | This saves us about 5000 reg writes per full update. This translates to about 40000 writes over the course of single eDP bootup. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Apply VQ adjustments in MPO caseSivapiriyanKumarasamy2017-12-041-2/+8
| | | | | | | Signed-off-by: SivapiriyanKumarasamy <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: rename transform to dpp for dcnYue Hin Lau2017-10-211-0/+134
Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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