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* drm/amd/display: Correct sequences and delays for DCN35 PG & RCGOvidiu Bunea2025-09-091-0/+1
| | | | | | | | | | | | | | | | | | | | [why] The current PG & RCG programming in driver has some gaps and incorrect sequences. [how] Added delays after ungating clocks to allow ramp up, increased polling to allow more time for power up, and removed the incorrect sequences. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Signed-off-by: Ovidiu Bunea <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> (cherry picked from commit 1bde5584e297921f45911ae874b0175dce5ed4b5) Cc: [email protected]
* drm/amd/display: Clear the CUR_ENABLE register on DCN314 w/out DPP PGIvan Lipski2025-08-291-0/+3
| | | | | | | | | | | | | | | | | | [Why&How] ON DCN314, clearing DPP SW structure without power gating it can cause a double cursor in full screen with non-native scaling. A W/A that clears CURSOR0_CONTROL cursor_enable flag if dcn10_plane_atomic_power_down is called and DPP power gating is disabled. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4168 Reviewed-by: Sun peng (Leo) Li <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]> (cherry picked from commit 645f74f1dc119dad5a2c7bbc05cc315e76883011) Cc: [email protected]
* drm/amd/display: Initial support for SmartMuxAurabindo Pillai2025-07-151-0/+2
| | | | | | | | | | | | | | | | | | | SmartMux is a mechanism to switch the GPU being used for scanout in a hybrid configuration. This is used for devices with an eDP and two GPUs. This is only valid when the system has a physical switch (Multiplexer) in the board to switch between the two GPUs. When a graphically intensive workload like a game is being run, the system can be switch the active display to the dGPU, so that we can avoid copying the buffer from dGPU to APU for scanout. This helps with latency and FPS. When power consumption is preferred, the system can be switched to the APU. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add static pg implementations for future useLeo Chen2025-07-151-0/+2
| | | | | | | | | | | [Why & How] Add static pg implementations and debug flags for future use. Reviewed-by: Duncan Ma <[email protected]> Signed-off-by: Leo Chen <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Refactor DSC cap calculationsDillon Varone2025-07-151-0/+12
| | | | | | | | | | | | | | | | | | | | | | [WHY] DSC block level should only be responsible for reporting single DSC instance capabilities. Factoring in ODM combine requirements should be handled in dc_dsc.c. Both components should acquire clocks from clk_mgr to determine throughput capabilities instead of relying on hard coded values as these can differ by SoC and SKU. [HOW] 1) Add dsc_get_single_enc_caps to acquire single DSC instance capabilities (replacing dsc_get_enc_caps), factoring in DSCCLK 2) add build_dsc_enc_caps to combine single DSC instance capabilities 3) account for max pixel rate per pipe (DISPCLK) when calculating minimum slice count Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: MPC basic allocation logic and TMZYihan Zhu2025-07-151-1/+1
| | | | | | | | | | | [WHY & HOW] Adding basic logic to allocate unused RMCM block and TMZ support. Reviewed-by: Krunoslav Kovac <[email protected]> Signed-off-by: Yihan Zhu <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add num_slices_h to set_dto_dscclk signatureIlya Bakoulin2025-06-241-1/+1
| | | | | | | | | | | Add the number of horizontal slices argument to allow configuring clock based on slice number. Reviewed-by: Nevenko Stupar <[email protected]> Signed-off-by: Ilya Bakoulin <[email protected]> Signed-off-by: Fangzhi Zuo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add APG struct to stream_enc for future useCharlene Liu2025-06-181-0/+1
| | | | | | | | | some new asics will have an APG instance taking over certain functions. Reviewed-by: Dmytro Laktyushkin <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix kernel docs for new struct membersAlex Hung2025-06-181-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | [WHAT & HOW] Add kernel-doc for new struct members for lut3d_caps and mpc_funcs. This fixes the follow warnings from "make htmldocs". ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:1106: warning: Function parameter or struct member 'mcm' not described in 'mpc_funcs' ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:1106: warning: Function parameter or struct member 'rmcm' not described in 'mpc_funcs' ./drivers/gpu/drm/amd/display/dc/dc.h:249: warning: Function parameter or struct member 'mcm_3d_lut_caps' not described in 'mpc_color_caps' ./drivers/gpu/drm/amd/display/dc/dc.h:249: warning: Function parameter or struct member 'rmcm_3d_lut_caps' not described in 'mpc_color_caps' ./drivers/gpu/drm/amd/display/dc/dc.h:249: warning: Function parameter or struct member 'preblend' not described in 'mpc_color_caps' Reviewed-by: Aurabindo Pillai <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add RMCM debug loggingYihan Zhu2025-06-181-0/+37
| | | | | | | | | | | | [WHY & HOW] Add new FL feature debug logging into the existing DTN logging. Reviewed-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Signed-off-by: Yihan Zhu <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Refactor DML2 DC power instanceDillon Varone2025-06-181-0/+2
| | | | | | | | | | | [WHY & HOW] Use a dedicated DC power option and instance pair. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: DCN42 RMCM and MCM 3DLUT supportYihan Zhu2025-04-211-0/+29
| | | | | | | | | | | [WHY & HOW] Providing hardware programming for the RMCM and MCM IPs for 3DLUT in DCN42. Reviewed-by: Charlene Liu <[email protected]> Signed-off-by: Yihan Zhu <[email protected]> Signed-off-by: Zaeem Mohamed <[email protected]> Tested-by: Mark Broadworth <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: wait for updates to latch before lockingAusef Yousof2025-04-071-0/+1
| | | | | | | | | | | | | | | | | | | | | [why&how] It is possible for an update to acquire otg lock and begin programming while the previous update has not completed and its values have not latched. The correct way to go about this is to wait until the vupdate pulses so we can be sure that previous updates have latched and we can continue with the current update pipe programming, otherwise during consecutive full updates we will have corruption flash on the screen. The corruption flash occurs specifically on configs that require odm combine, and its local to a specific pipe (will not flash across whole screen). This ticket is across the otg slave, but it may also appear across master. Reviewed-by: Leo Chen <[email protected]> Signed-off-by: Ausef Yousof <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Correct SSC enable detection for DCN351Kevin Gao2025-04-071-1/+2
| | | | | | | | | | | | | | | | | | | | | [Why] Due to very small clock register delta between DCN35 and DCN351, clock spread is being checked on the wrong register for DCN351, causing the display driver to believe that DPREFCLK downspread to be disabled when in some stacks it is enabled. This causes the clock values for audio to be incorrect. [How] Both DCN351 and DCN35 use the same clk_mgr, so we modify the DCN35 function that checks for SSC enable to read CLK6 instead of CLK5 when using DCN351. This allows us to read for DPREFCLK downspread correctly so the clock can properly compensate when setting values. Reviewed-by: Charlene Liu <[email protected]> Signed-off-by: Kevin Gao <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: removed unused functionJames Flowers2025-04-071-17/+0
| | | | | | | Removed unused function mpc401_get_3dlut_fast_load_status. Signed-off-by: James Flowers <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix BT2020 YCbCr limited/full range inputIlya Bakoulin2025-02-191-1/+5
| | | | | | | | | | | | | | | | | [Why] BT2020 YCbCr input is not handled properly when full range quantization is used and limited range is not supported at all. [How] - Add enums for BT2020 YCbCr limited/full range - Add limited range CSC matrix Reviewed-by: Krunoslav Kovac <[email protected]> Signed-off-by: Ilya Bakoulin <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Robert Mader <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Move SPL to a new pathSamson Tam2025-02-131-1/+1
| | | | | | | | | | | | | [WHY & HOW] - Move SPL from dc/spl to dc/sspl - Update build files and header paths - Remove dc/spl files Reviewed-by: George Zhang <[email protected]> Signed-off-by: Samson Tam <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Populate register address for dentist for dcn401Dillon Varone2025-02-131-0/+1
| | | | | | | | | | | | [WHY&HOW] Address was not previously populated which can result in incorrect clock frequencies being read on boot. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: log destination of vertical interruptJosip Pavic2025-02-132-29/+31
| | | | | | | | | | | | | | | | | | | [Why] Knowing the destination of OTG's vertical interrupt 2 is useful for debugging, but it is not currently included in the OTG state readback logic [How] Read the OTG interrupt destination register to get the vertical interrupt 2 destination on ASICs that have this register when reading back the OTG state from hardware Reviewed-by: Sung Lee <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Signed-off-by: Josip Pavic <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add hubp cache reset when powergatingAric Cyr2025-01-241-0/+2
| | | | | | | | | | | | | | | | | | | | | [Why] When HUBP is power gated, the SW state can get out of sync with the hardware state causing cursor to not be programmed correctly. [How] Similar to DPP, add a HUBP reset function which is called wherever HUBP is initialized or powergated. This function will clear the cursor position and attribute cache allowing for proper programming when the HUBP is brought back up. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Sung Lee <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add support to configure CRC window on specific CRC instanceWayne Lin2025-01-101-0/+3
| | | | | | | | | | | | | | | | | | [Why] Have the need to specify the CRC window on specific CRC engine. dc_stream_configure_crc() today calculates CRC on crc engine 0 only and always resets CRC engine at first. [How] Add index parameter to dc_stream_configure_crc() for selecting the desired crc engine. Additionally, add another parameter to specify whether to skip the default reset of crc engine. Reviewed-by: HaoPing Liu <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Signed-off-by: Tom Chung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: DML2.1 Post-Si CleanupRafal Ostrowski2025-01-101-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] There are a few cleanup and refactoring tasks that need to be done with the DML2.1 wrapper and DC interface to remove dependencies on legacy structures and N-1 prototypes. [How] Implemented pipe_ctx->global_sync. Implemented new functions to use pipe_ctx->hubp_regs and pipe_ctx->global_sync: - hubp_setup2 - hubp_setup_interdependent2 - Several other new functions for DCN 4.01 to support newer structures Removed dml21_update_pipe_ctx_dchub_regs Removed dml21_extract_legacy_watermark_set Removed dml21_populate_pipe_ctx_dlg_param Removed outdated dcn references in DML2.1 wrapper. Reviewed-by: Austin Zheng <[email protected]> Reviewed-by: Dillon Varone <[email protected]> Signed-off-by: Rafal Ostrowski <[email protected]> Signed-off-by: Tom Chung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Log Hard Min Clocks and Phantom Pipe StatusSung Lee2025-01-101-0/+3
| | | | | | | | | | | | | | | | [WHY] On entering/exiting idle power, certain parameters would be very useful to know for power profiling purposes. [HOW] This commit adds certain hard min clocks and pipe types to log output on idle optimization enter/exit. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Sung Lee <[email protected]> Signed-off-by: Tom Chung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Update dc_tiling_info union to structureKarthi Kandasamy2025-01-062-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] The `dc_tiling_info` union previously did not have a field to specify the active GFX format, assuming only one format would be used per DCN version. from DCN4+, support for switching between different GFX formats is introduced, requiring a way to track which format is currently in use. [HOW] Updated the `dc_tiling_info` union to include a new field that explicitly indicates the currently used GFX format. This allows the system to determine the active GFX format and take the correct programming path accordingly. [Description] The union `dc_tiling_info` has been updated to support multiple GFX formats by adding a new field for identifying the active format. This update ensures that the correct programming path is followed based on the selected format. All references to `dc_tiling_info` in the codebase have been updated to reflect the new structure. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Karthi Kandasamy <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: have pretrain for dpiaPeichen Huang2025-01-061-0/+8
| | | | | | | | | | | | | | | | | | | | | [WHY] We like to have pretrain for dpia link so that dp and dp tunneling have aligned behavior. The Main difficult for dpia pretrain is that encoder can not get corresponded dpia port when link detection in current implementation. [HOW] 1. create enable/disable dpia output functions for dcn35 encoder and have dpia_id and other necessary info as inputs. 2. dcn35 dpia use the new functions to enable/disable output. 3. have a option to enable/disable the change. Reviewed-by: Wenjing Liu <[email protected]> Reviewed-by: Meenakshikumar Somasundaram <[email protected]> Signed-off-by: Peichen Huang <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Extend dc_stream_get_crc to support 2nd crc engineWayne Lin2025-01-062-2/+2
| | | | | | | | | | | | | [Why & How] Since now we can set multiple crc windows for secure display, add a new input parameter for dc_stream_get_crc to indicate to fetch crc from which crc engine. Reviewed-by: HaoPing Liu <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add clear_tiling mi callbacksAlex Deucher2024-12-181-0/+2
| | | | | | | | | | | | | This adds clear_tiling callbacks to the mi structure that will be used for drm panic support to clear the tiling on a display. Mem input (mi) is used on DCE based display IPs. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: Lu Yao <[email protected]> Cc: Jocelyn Falempe <[email protected]> Cc: Harry Wentland <[email protected]>
* drm/amd/display: add clear_tiling hubp callbacksAlex Deucher2024-12-181-0/+1
| | | | | | | | | | | | | This adds clear_tiling callbacks to the hubp structure that will be used for drm panic support to clear the tiling on a display. hubp3 support from Jocelyn's original patch and the rest from me. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: Lu Yao <[email protected]> Cc: Jocelyn Falempe <[email protected]> Cc: Harry Wentland <[email protected]>
* drm/amd/display: update dcn351 used clock offsetCharlene Liu2024-12-101-0/+59
| | | | | | | | | | | [why] hw register offset delta Reviewed-by: Martin Leung <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Enable Request rate limiter during C-State on dcn401Dillon Varone2024-11-201-1/+1
| | | | | | | | | | | | | | | | [WHY] When C-State entry is requested, the rate limiter will be disabled which can result in high contention in the DCHUB return path. [HOW] Enable the rate limiter during C-state requests to prevent contention. Cc: [email protected] # 6.11+ Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add P-State Stall Timeout Recovery Support for dcn401Dillon Varone2024-10-281-0/+1
| | | | | | | | | | | [WHY&HOW] Adds support for P-State stall timeout detection in DCHUBBUB. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Tom Chung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add 3DLUT FL HW bug workaroundIlya Bakoulin2024-10-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | [Why] There is a known HW bug that causes the internal 3DLUT fetch signal to be lost at VREADY, regardless of whether the OTG lock is being held or not. A workaround is necessary to make sure that this internal signal stays up after OTG unlock. [How] Set the 3DLUT_ENABLE bit immediately before and after the unlock. Also use VUPDATE_KEEPOUT to prevent lock transition in the region between VSTARTUP and VREADY, which could cause issues with this WA sequence. Also including misc. 3DLUT DMA-related sequence fixes to address a few regressions causing corruption. Reviewed-by: Dillon Varone <[email protected]> Signed-off-by: Ilya Bakoulin <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Wait for all pending cleared before full updateAlvin Lee2024-10-011-1/+3
| | | | | | | | | | | | | | | | | [Description] Before every full update we must wait for all pending updates to be cleared - this is particularly important for minimal transitions because if we don't wait for pending cleared, it will be as if there was no minimal transition at all. In OTG we must read 3 different status registers for pending cleared, one specifically for OTG updates, one specifically for OPTC updates, and the last for surface related updates. Reviewed-by: Dillon Varone <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: fix dccg root clock optimization related hangQili Lu2024-09-061-0/+1
| | | | | | | | | | | | | | | [Why] enable dpp rcg before we disable dppclk in hw_init cause system hang/reboot [How] we remove dccg rcg related code from init into a separate function and call it after we init pipe Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Qili Lu <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Revert "drm/amd/display: Wait for all pending cleared before full update"Dillon Varone2024-09-021-3/+1
| | | | | | | | | | | This reverts commit f0b7dcf25834afd17df316367dfe5d4c890c713c. It is causing graphics hangs. Reviewed-by: Martin Leung <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Wait for all pending cleared before full updateAlvin Lee2024-08-271-1/+3
| | | | | | | | | | | | | | | | | [Description] Before every full update we must wait for all pending updates to be cleared - this is particularly important for minimal transitions because if we don't wait for pending cleared, it will be as if there was no minimal transition at all. In OTG we must read 3 different status registers for pending cleared, one specifically for OTG updates, one specifically for OPTC updates, and the last for surface related updates Reviewed-by: Dillon Varone <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Zaeem Mohamed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Unlock Pipes Based On DET AllocationAustin Zheng2024-08-131-0/+1
| | | | | | | | | | | | | | | | | | [Why] DML21 does not allocate DET evenly between pipes. May result in underflow when unlocking the pipes as DET could be overallocated. [How] 1. Unlock pipes that have a decreased amount of DET allocation 2. Wait for the double buffer to be updated. 3. Unlock the remaining pipes. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Austin Zheng <[email protected]> Signed-off-by: Tom Chung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Remove unused codeRodrigo Siqueira2024-08-061-10/+0
| | | | | | | | | Remove function pointers that were never used. Reviewed-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Remove duplicated codeRodrigo Siqueira2024-08-061-3/+0
| | | | | | | | | | DCN_MINIMUM_DISPCLK_Khz and DCN_MINIMUM_DPPCLK_Khz is declared twice. This commit removes that duplication. Reviewed-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add seamless boot support for more DIG operation modesNicholas Kazlauskas2024-07-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | [Why] When pre-OS firmware enables display support for displays that operate the DIG in 2 pixels per cycle processing modes the inferred pixel rate from get_pixel_clk_frequency_100hz does not account for the true pixel rate since we're outputting 2 per cycle past the stream encoder. This causes seamless boot validation to abort early. [How] Add a new stream encoder function for getting pixels per cycle from the stream encoder. If the pixels per cycle is greater than 1 and the driver policy is to enable 2 pixels per cycle for post-OS then allow seamless boot to continue. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Duncan Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: rename dcn3/dcn4 to more sound termsAurabindo Pillai2024-07-231-1/+1
| | | | | | | | | | Use more accurate names to refer to the asic architecture. dcn3 in DML actually refers to DCN32 and DCN321, so rename it to dcn32x dcn4 refers to any DCN4x soc., and hence rename dcn4 to dcn4x Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add P-State Keepout to dcn401 Global SyncDillon Varone2024-07-232-2/+7
| | | | | | | | | | | | | [WHY&HOW] OTG has new functionality to allow P-State relative to VStartup. Keepout region for this should be configured based on DML outputs same as other global sync params. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: avoid disable otg when dig was disabledJingwen Zhu2024-07-231-0/+1
| | | | | | | | | | | | | | | | [Why] This is a workaround for an dcn3.1 hang that happens if otg dispclk is ramped while otg is on and stream enc is off. But this w/a should not trigger when we have a dig active. [How] Avoid disable otg when dig FE/BE FIFO was not switched. Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Jingwen Zhu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Implement bias and scale pre sclRelja Vojvodic2024-07-231-6/+7
| | | | | | | | | | | | | | | | | why: New scaler needs the input to be full range color space. This will also fix issues that come up due to not having a predefined limited color space matrix for certain color spaces how: Use bias and scale HW to expand the range of limited color spaces to full before the scaler Reviewed-by: Krunoslav Kovac <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Relja Vojvodic <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: fix dscclk programming sequence on DCN401Wenjing Liu2024-07-231-4/+1
| | | | | | | | | | | | | | | | | | | | | [why] The mux to switch between refclk and dto_dsc_clk is non double buffered. However dto dsc clk's phase and modulo divider registers are currently configured as double buffered update. This causes a problem when we switch to use dto dsc clk and program phase and modulo in the same sequence. In this sequence dsc clk is switched to dto but the clock divider programming doesn't take effect until next frame. When we try to program DSCC registers, SMN bus will hang because dto dsc clk divider phase is set to 0. [how] Configure phase and modulo to take effect immediately. Always switch to dto dsc clk before DSC clock is unagted. Switch back to refclk after DSC clock is gated. Acked-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Jerry Zuo <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Added logging for automated DPM testingRyan Seto2024-07-232-1/+4
| | | | | | | | | | | | | | | [Why] Added clock logs to automate DPM testing [How] Added logs and helper functions to output clocks Co-authored-by: Ryan Seto <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Ryan Seto <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Disable HBR audio for DP2 for certain ASICsAlvin Lee2024-07-231-0/+2
| | | | | | | | | | | | [Description] Due to a HW bug, HBR audio is not supported for DP2 encoders for certain ASICs. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add simple struct doc to remove doc build warningRodrigo Siqueira2024-07-162-5/+32
| | | | | | | | | | | | | | | | | | | This commit is a part of a series that addresses the following build warning for opp: ./drivers/gpu/drm/amd/display/dc/inc/hw/opp.h:1: warning: no structured comments found ./drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h:1: warning: no structured comments found This commit fixes this issue by adding a simple kernel-doc to a struct in the opp.h and the dpp.h files. Cc: Alex Deucher <[email protected]> Acked-by: Alex Deucher <[email protected]> Reported-by: Stephen Rothwell <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add doc entry for program_3dlut_sizeAlex Hung2024-07-161-0/+14
| | | | | | | | | | | | | Fixes the warning: Function parameter or struct member 'program_3dlut_size' not described in 'mpc_funcs' Reported-by: Stephen Rothwell <[email protected]> Closes: https://lore.kernel.org/dri-devel/[email protected]/ Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Enable DCC on DCN401Aurabindo Pillai2024-06-272-0/+5
| | | | | | | | | | | [WHAT] Add registers and entry points to enable DCC on DCN4x Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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