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* Merge branch 'pci/controller/qcom'Bjorn Helgaas2025-07-311-18/+20
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Export DWC MSI controller related APIs for use by upcoming DWC-based ECAM implementation (Mayank Rana) - Rename gen_pci_init() to pci_host_common_ecam_create() and export for use by controller drivers (Mayank Rana) - Add DT binding and driver support for SA8255p, which supports ECAM for Configuration Space access (Mayank Rana) - Update DT binding and driver to describe PHYs and per-Root Port resets in a Root Port stanza and deprecate describing them in the host bridge; this makes it possible to support multiple Root Ports in the future (Krishna Chaitanya Chundru) * pci/controller/qcom: PCI: qcom: Add support for parsing the new Root Port binding dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port node PCI: qcom: Add support for Qualcomm SA8255p based PCIe Root Complex dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex PCI: host-generic: Rename and export gen_pci_init() for PCIe controller drivers PCI: dwc: Export DWC MSI controller related APIs
| * PCI: dwc: Export DWC MSI controller related APIsMayank Rana2025-07-011-18/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | Export dw_pcie_msi_host_init(), dw_pcie_msi_init(), and dw_pcie_free_msi() APIs to allow them to be reused by the upcoming DWC based ECAM driver implementation. Also, move MSI IRQ related initialization code to dw_pcie_msi_init(), as this code must be executed before dw_pcie_msi_init() API can be used with ECAM driver. Signed-off-by: Mayank Rana <[email protected]> [mani: commit message rewording] Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://patch.msgid.link/[email protected]
* | PCI: dwc: Switch to msi_create_parent_irq_domain()Nam Cao2025-07-241-43/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao <[email protected]> [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <[email protected]> [bhelgaas: rebase on dev_fwnode() conversion] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Thomas Gleixner <[email protected]> Link: https://patch.msgid.link/04d4a96046490e50139826c16423954e033cdf89.1750858083.git.namcao@linutronix.de
* | PCI: controller: Use dev_fwnode() instead of of_fwnode_handle()Jiri Slaby (SUSE)2025-07-241-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | All irq_domain functions now accept fwnode instead of of_node. But many PCI controllers still extract dev to of_node and then of_node to fwnode. Instead, clean this up and simply use the dev_fwnode() helper to extract fwnode directly from dev. Internally, it still does dev => of_node => fwnode steps, but it's now hidden from the users. In the case of altera, this also removes an unused 'node' variable that is only used when CONFIG_OF is enabled: drivers/pci/controller/pcie-altera.c: In function 'altera_pcie_init_irq_domain': drivers/pci/controller/pcie-altera.c:855:29: error: unused variable 'node' [-Werror=unused-variable] 855 | struct device_node *node = dev->of_node; Signed-off-by: Jiri Slaby (SUSE) <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]> # altera [bhelgaas: squash together, rebase to precede msi-parent] Signed-off-by: Bjorn Helgaas <[email protected]> Link: https://patch.msgid.link/[email protected] Link: https://patch.msgid.link/[email protected] Link: https://patch.msgid.link/[email protected]
* Merge branch 'pci/ptm-debugfs'Bjorn Helgaas2025-06-041-1/+1
|\ | | | | | | | | | | | | | | | | | | | | - Add debugfs support for exposing DWC device-specific PTM context (Manivannan Sadhasivam) * pci/ptm-debugfs: PCI: qcom-ep: Mask PTM_UPDATING interrupt PCI: dwc: Add debugfs support for PTM context PCI: dwc: Pass DWC PCIe mode to dwc_pcie_debugfs_init() PCI: Add debugfs support for exposing PTM context
| * PCI: dwc: Pass DWC PCIe mode to dwc_pcie_debugfs_init()Manivannan Sadhasivam2025-05-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | Upcoming PTM debugfs interface relies on the DWC PCIe mode to expose the relevant debugfs attributes to userspace. So pass the mode to dwc_pcie_debugfs_init() API from host and ep drivers and save it in 'struct dw_pcie::mode'. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Link: https://patch.msgid.link/[email protected]
* | Merge branch 'pci/controller/qcom'Bjorn Helgaas2025-06-041-0/+79
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add OF support for parsing DT 'eq-presets-<N>gts' property for lane equalization presets (Krishna Chaitanya Chundru) - Read Maximum Link Width from the Link Capabilities register if DT lacks 'num-lanes' property (Krishna Chaitanya Chundru) - Add Physical Layer 64 GT/s Capability ID and register offsets for 8, 32, and 64 GT/s lane equalization registers (Krishna Chaitanya Chundru) - Add generic dwc support for configuring lane equalization presets (Krishna Chaitanya Chundru) - Add DT and driver support for PCIe on IPQ5018 SoC (Nitheesh Sekar) * pci/controller/qcom: PCI: qcom: Add support for IPQ5018 dt-bindings: PCI: qcom: Add IPQ5018 SoC PCI: dwc: Add support for configuring lane equalization presets PCI: Add lane equalization register offsets PCI: dwc: Update pci->num_lanes to maximum supported link width PCI: of: Add of_pci_get_equalization_presets() API
| * | PCI: dwc: Add support for configuring lane equalization presetsKrishna Chaitanya Chundru2025-04-231-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCIe equalization presets are predefined settings used to optimize signal integrity by compensating for signal loss and distortion in high-speed data transmission. Based upon the number of lanes and the data rate supported, write the preset data read from the device tree in to the lane equalization control registers. These preset values will be used by the controller during the LTSSM lane equalization procedure. Signed-off-by: Krishna Chaitanya Chundru <[email protected]> [mani: reworded the commit message and comments in the driver] Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://patch.msgid.link/[email protected]
| * | PCI: dwc: Update pci->num_lanes to maximum supported link widthKrishna Chaitanya Chundru2025-04-191-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | If the num-lanes property is not present in the devicetree, update pci->num_lanes with the hardware supported maximum link width using the newly introduced dw_pcie_link_get_max_link_width() API. The API is used to get the Maximum Link Width (MLW) of the controller. Signed-off-by: Krishna Chaitanya Chundru <[email protected]> [mani: reworded commit message a bit] Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://patch.msgid.link/[email protected]
* / irqdomain: pci: Switch to of_fwnode_handle()Jiri Slaby (SUSE)2025-04-071-1/+1
|/ | | | | | | | | | of_node_to_fwnode() is irqdomain's reimplementation of the "officially" defined of_fwnode_handle(). The former is in the process of being removed, so use the latter instead. Signed-off-by: Jiri Slaby (SUSE) <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Link: https://patch.msgid.link/[email protected]
* Merge branch 'pci/controller/dwc-cpu-addr-fixup'Bjorn Helgaas2025-03-271-19/+38
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Ioremap() msg_res region using res->start (the CPU address), not the ATU 'cpu_addr', which will be replaced with the ATU input address (which may not be the CPU address) (Frank Li) - Rename struct dw_pcie_ob_atu_cfg.cpu_addr to 'parent_bus_addr' (Frank Li) - Call devm_pci_alloc_host_bridge() early in dw_pcie_host_init() to keep devicetree-related code together (Frank Li) - Consolidate devicetree handling in dw_pcie_host_get_resources() (Bjorn Helgaas) - Add dw_pcie_parent_bus_offset() to look up the parent bus address of a specified 'reg' property and return the offset from the CPU physical address (Frank Li) - Add cross-checking with .cpu_addr_fixup() and debug logging to dw_pcie_parent_bus_offset() (Frank Li) - Use devicetree 'reg[config]' via dw_pcie_parent_bus_offset() to derive CPU -> ATU addr offset for host controller (Frank Li) - Call epc_create() early in dw_pcie_ep_init() to keep devicetree-related code together (Bjorn Helgaas) - Consolidate devicetree handling in dw_pcie_ep_get_resources() (Bjorn Helgaas) - Use devicetree 'reg[addr_space]' via dw_pcie_parent_bus_offset() to derive CPU -> ATU addr offset for endpoint controller (Frank Li) - Update dw_pcie_find_index() to remove assumption that ATU input address is non-zero (Frank Li) - Apply struct dw_pcie.parent_bus_offset in ATU users to remove use of .cpu_addr_fixup() when programming ATU (Frank Li) - Remove imx_pcie_cpu_addr_fixup() since dwc core can now derive the ATU input address (using parent_bus_offset) from devicetree (Frank Li) - Remove intel_pcie_cpu_addr() since dwc core can now derive the ATU input address (using parent_bus_offset) from devicetree (Frank Li) * pci/controller/dwc-cpu-addr-fixup: PCI: intel-gw: Remove intel_pcie_cpu_addr() PCI: imx6: Remove imx_pcie_cpu_addr_fixup() PCI: dwc: Use parent_bus_offset to remove need for .cpu_addr_fixup() PCI: dwc: ep: Ensure proper iteration over outbound map windows PCI: dwc: ep: Use devicetree 'reg[addr_space]' to derive CPU -> ATU addr offset PCI: dwc: ep: Consolidate devicetree handling in dw_pcie_ep_get_resources() PCI: dwc: ep: Call epc_create() early in dw_pcie_ep_init() PCI: dwc: Use devicetree 'reg[config]' to derive CPU -> ATU addr offset PCI: dwc: Add dw_pcie_parent_bus_offset() checking and debug PCI: dwc: Add dw_pcie_parent_bus_offset() PCI: dwc: Consolidate devicetree handling in dw_pcie_host_get_resources() PCI: dwc: Call devm_pci_alloc_host_bridge() early in dw_pcie_host_init() PCI: dwc: Rename cpu_addr to parent_bus_addr for ATU configuration PCI: dwc: Use resource start as ioremap() input in dw_pcie_pme_turn_off() # Conflicts: # drivers/pci/controller/dwc/pcie-designware.c # drivers/pci/controller/dwc/pcie-designware.h
| * PCI: dwc: Use parent_bus_offset to remove need for .cpu_addr_fixup()Frank Li2025-03-241-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We know the parent_bus_offset, either computed from a DT reg property (the offset is the CPU physical addr - the 'config'/'addr_space' address on the parent bus) or from a .cpu_addr_fixup() (which may have used a host bridge window offset). Apply that parent_bus_offset instead of calling .cpu_addr_fixup() when programming the ATU. This assumes all intermediate addresses are at the same offset from the CPU physical addresses. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Frank Li <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * PCI: dwc: Use devicetree 'reg[config]' to derive CPU -> ATU addr offsetFrank Li2025-03-241-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'ranges' property of a PCI controller's parent can indicate address translation information. Most system use 1:1 map between CPU physical and PCI controller input addresses. But some hardware, like i.MX8QXP, doesn't use 1:1 map. See below diagram: ┌─────────┐ ┌────────────┐ ┌─────┐ │ │ IA: 0x8ff8_0000 │ │ │ CPU ├───►│ ┌────►├─────────────────┐ │ PCI │ └─────┘ │ │ │ IA: 0x8ff0_0000 │ │ │ CPU Addr │ │ ┌─►├─────────────┐ │ │ Controller │ 0x7ff8_0000─┼───┘ │ │ │ │ │ │ │ │ │ │ │ │ │ PCI Addr 0x7ff0_0000─┼──────┘ │ │ └──► IOSpace ─┼────────────► │ │ │ │ │ 0 0x7000_0000─┼────────►├─────────┐ │ │ │ └─────────┘ │ └──────► CfgSpace ─┼────────────► Bus Fabric │ │ │ 0 │ │ │ └──────────► MemSpace ─┼────────────► IA: 0x8000_0000 │ │ 0x8000_0000 └────────────┘ bus@5f000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x80000000 0x0 0x70000000 0x10000000>; pcie@5f010000 { compatible = "fsl,imx8q-pcie"; reg = <0x5f010000 0x10000>, <0x8ff00000 0x80000>; reg-names = "dbi", "config"; ... }; }; Intermediate address (IA) here means the PCIe controller input address. The pcie@5f010000 'reg[config]' address is the parent bus (PCIe controller input) address of CfgSpace. The ATU in MemSpace is not explicitly described via devicetree, so we assume the offset from CPU address to intermediate MemSpace address is the same as that for CfgSpace. We could use bus@5f000000 'ranges' for the same purpose. Set parent_bus_offset using dw_pcie_init_parent_bus_offset(). The parent_bus_offset is not used yet, so no functional change intended. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Frank Li <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * PCI: dwc: Consolidate devicetree handling in dw_pcie_host_get_resources()Bjorn Helgaas2025-03-171-12/+25
| | | | | | | | | | | | | | | | | | Consolidate devicetree resource handling in dw_pcie_host_get_resources(). No functional change intended. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Frank Li <[email protected]>
| * PCI: dwc: Call devm_pci_alloc_host_bridge() early in dw_pcie_host_init()Frank Li2025-03-171-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move devm_pci_alloc_host_bridge() to the beginning of dw_pcie_host_init(). devm_pci_alloc_host_bridge() is generic code that doesn't depend on any DWC resource, so moving it earlier keeps all the subsequent devicetree-related code together. [bhelgaas: reorder earlier in series] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Frank Li <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * PCI: dwc: Rename cpu_addr to parent_bus_addr for ATU configurationFrank Li2025-03-171-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Rename 'cpu_addr' to 'parent_bus_addr' in the DesignWare ATU configuration. The ATU translates parent bus addresses to PCI addresses, which are often the same as CPU addresses but can differ in systems where the bus fabric translates addresses before passing them to the PCIe controller. This renaming clarifies the purpose and avoids confusion. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Frank Li <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
| * PCI: dwc: Use resource start as ioremap() input in dw_pcie_pme_turn_off()Frank Li2025-03-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The msg_res region translates writes into PCIe Message TLPs. Previously we mapped this region using atu.cpu_addr, the input address programmed into the ATU. "cpu_addr" is a misnomer because when a bus fabric translates addresses between the CPU and the ATU, the ATU input address is different from the CPU address. A future patch will rename "cpu_addr" and correct the value to be the ATU input address instead of the CPU physical address. Map the msg_res region before writing to it using the msg_res resource start, a CPU physical address. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Frank Li <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
* | PCI: dwc: Add debugfs based Silicon Debug support for DWCShradha Todi2025-03-061-0/+4
|/ | | | | | | | | | | | | | | | | | | | | | Add support to provide Silicon Debug interface to userspace. This set of debug registers are part of the RAS DES feature present in DesignWare PCIe controllers. Co-developed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Shradha Todi <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Fan Ni <[email protected]> Tested-by: Hrishikesh Deleep <[email protected]> Link: https://lore.kernel.org/r/[email protected] [kwilczynski: commit log, tidy up Kconfig and drop "default y", tidy up code comments, squashed patch that fixes a NULL pointer dereference when debugfs is already unavailable during clean-up from https://lore.kernel.org/linux-pci/[email protected], refactor dwc_pcie_debugfs_init() to not return errors, squashed patch that changes how lack of the RAS DES capability is handled from https://lore.kernel.org/linux-pci/20250304151814.6xu7cbpwpqrvcad5@thinkpad] Signed-off-by: Krzysztof Wilczyński <[email protected]>
* PCI: dwc: Simplify config resource lookupBjorn Helgaas2025-01-201-9/+9
| | | | | | | | | | If platform_get_resource_byname("config") fails, return error immediately and unindent the normal path. No functional change intended. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* PCI: dwc: Remove LTSSM state test in dw_pcie_suspend_noirq()Richard Zhu2025-01-181-10/+17
| | | | | | | | | | | | | | | | | | It's safe to send PME_TURN_OFF message regardless of whether the link is up or down, so don't test the LTSSM state before sending the PME_TURN_OFF message. Only print an error message when the LTSSM is not in DETECT or POLL. There shouldn't be an error when no Endpoint is connected at all. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Richard Zhu <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* PCI: dwc: Always stop link in the dw_pcie_suspend_noirqRichard Zhu2025-01-181-0/+1
| | | | | | | | | | | | | | | | | | On the i.MX8QM, PCIe link can't be re-established again in dw_pcie_resume_noirq(), if the LTSSM_EN bit is not cleared properly in dw_pcie_suspend_noirq(). So, add dw_pcie_stop_link() to dw_pcie_suspend_noirq() to fix this issue and to align the suspend/resume functions since there is dw_pcie_start_link() in dw_pcie_resume_noirq() already. Fixes: 4774faf854f5 ("PCI: dwc: Implement generic suspend/resume functionality") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Richard Zhu <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* PCI: dwc: Don't wait for link up if driver can detect Link Up eventKrishna chaitanya chundru2025-01-181-2/+8
| | | | | | | | | | | | | | | If the driver can detect the Link Up event and enumerate downstream devices at that time, we need not wait here. Skip waiting for link to come up if the driver supports 'use_linkup_irq'. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krishna chaitanya chundru <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> [bhelgaas: wrap comment, update commit log] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Niklas Cassel <[email protected]>
* PCI: dwc: Use of_property_present() for non-boolean propertiesRob Herring (Arm)2024-11-161-2/+2
| | | | | | | | | | | | The use of of_property_read_bool() for non-boolean properties is deprecated in favor of of_property_present() when testing for property presence. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring (Arm) <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
* PCI: dwc: Silence 'set affinity failed' warningMarek Vasut2024-07-291-9/+3
| | | | | | | | | | | | | | | | | Use MSI_FLAG_NO_AFFINITY, which keeps .irq_set_affinity() unset and allows migrate_one_irq() to exit right away, without warnings like this: IRQ...: set affinity failed(-22) Remove the .irq_set_affinity() implementation that is no longer needed. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Marek Vasut <[email protected]> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Damien Le Moal <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Acked-by: Thomas Gleixner <[email protected]>
* PCI: dwc: Add generic MSG TLP support for sending PME_Turn_Off when system ↵Frank Li2024-07-091-5/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | suspend Instead of relying on the vendor specific implementations to send the PME_Turn_Off message, introduce a generic way of sending the message using the MSG TLP. This is achieved by reserving a region for MSG TLP of size 'pci->region_align', at the end of the first IORESOURCE_MEM window of the host bridge. And then sending the PME_Turn_Off message during system suspend with the help of iATU. The reason for reserving the MSG TLP region at the end of the IORESOURCE_MEM is to avoid generating holes in between, because when the region is allocated using allocate_resource(), memory will be allocated from the start of the window. Later, if memory gets allocated for an endpoint of size bigger than 'region_align', there will be a hole between MSG TLP region and endpoint memory. This generic implementation is optional for the glue drivers and can be overridden by a custom 'pme_turn_off' callback. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Frank Li <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* PCI: dwc: Consolidate args of dw_pcie_prog_outbound_atu() into a structureYoshihiro Shimoda2024-07-091-16/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparation before adding the Msg-type outbound iATU mapping. The respective update will require two more arguments added to __dw_pcie_prog_outbound_atu(). That will make the already complicated function prototype even more hard to comprehend accepting _eight_ arguments. To prevent that and keep the code more-or-less readable, move all the outbound iATU-related arguments to a new config structure: struct dw_pcie_ob_atu_cfg, and pass a pointer to dw_pcie_prog_outbound_atu(). The structure should be locally defined and populated with the outbound iATU settings implied by the caller context. As a result of this change there is no longer need in having the two distinctive methods for the Host and Endpoint outbound iATU setups since the code can directly call the dw_pcie_prog_outbound_atu() method with the config structure populated, so drop dw_pcie_prog_ep_outbound_atu(). [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Frank Li <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Serge Semin <[email protected]>
* PCI: dwc: Strengthen the MSI address allocation logicAjay Agarwal2024-03-101-8/+13
| | | | | | | | | | | | | | | | | | | There can be platforms that do not use/have 32-bit DMA addresses. The current implementation of 32-bit IOVA allocation can fail for such platforms, eventually leading to the probe failure. Try to allocate a 32-bit msi_data. If this allocation fails, attempt a 64-bit address allocation. Please note that if the 64-bit MSI address is allocated, then the EPs supporting 32-bit MSI address only will not work. Link: https://lore.kernel.org/linux-pci/[email protected] Tested-by: Will McVicker <[email protected]> Signed-off-by: Ajay Agarwal <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Serge Semin <[email protected]> Reviewed-by: Will McVicker <[email protected]>
* PCI: dwc: Drop host prefix from struct dw_pcie_host_ops membersYoshihiro Shimoda2024-01-061-15/+15
| | | | | | | | | | | | | | | | | | | Since the name of the dw_pcie_host_ops struct makes it obvious that it's for the PCIe Host, drop the host prefix from the struct members. [kwilczynski: commit log] Suggested-by: Serge Semin <[email protected]> Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Serge Semin <[email protected]> Reviewed-by: Thomas Petazzoni <[email protected]> Acked-by: Heiko Stuebner <[email protected]> Acked-by: Jesper Nilsson <[email protected]> Acked-by: Kunihiko Hayashi <[email protected]> Acked-by: Lei Chuanhua <[email protected]> Acked-by: Nobuhiro Iwamatsu <[email protected]>
* PCI: dwc: Add host_post_init() callbackManivannan Sadhasivam2023-10-141-0/+3
| | | | | | | | | | This callback can be used by the platform drivers to do configuration once all the devices are scanned. Like changing LNKCTL of all downstream devices to enable ASPM etc... Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]>
* Merge tag 'pci-v6.6-changes' of ↵Linus Torvalds2023-08-311-0/+71
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci Pull PCI updates from Bjorn Helgaas: "Enumeration: - Add locking to read/modify/write PCIe Capability Register accessors for Link Control and Root Control - Use pci_dev_id() when possible instead of manually composing ID from dev->bus->number and dev->devfn Resource management: - Move prototypes for __weak sysfs resource files to linux/pci.h to fix 'no previous prototype' warnings - Make more I/O port accesses depend on HAS_IOPORT - Use devm_platform_get_and_ioremap_resource() instead of open-coding platform_get_resource() followed by devm_ioremap_resource() Power management: - Ensure devices are powered up while accessing VPD - If device is powered-up, keep it that way while polling for PME - Only read PCI_PM_CTRL register when available, to avoid reading the wrong register and corrupting dev->current_state Virtualization: - Avoid Secondary Bus Reset on NVIDIA T4 GPUs Error handling: - Remove unused pci_disable_pcie_error_reporting() - Unexport pci_enable_pcie_error_reporting(), used only by aer.c - Unexport pcie_port_bus_type, used only by PCI core VGA: - Simplify and clean up typos in VGA arbiter Apple PCIe controller driver: - Initialize pcie->nvecs (number of available MSIs) before use Broadcom iProc PCIe controller driver: - Use of_property_read_bool() instead of low-level accessors for boolean properties Broadcom STB PCIe controller driver: - Assert PERST# when probing BCM2711 because some bootloaders don't do it Freescale i.MX6 PCIe controller driver: - Add .host_deinit() callback so we can clean up things like regulators on probe failure or driver unload Freescale Layerscape PCIe controller driver: - Add support for link-down notification so the endpoint driver can process LINK_DOWN events - Add suspend/resume support, including manual PME_Turn_off/PME_TO_Ack handshake - Save Link Capabilities during probe so they can be restored when handling a link-up event, since the controller loses the Link Width and Link Speed values during reset Intel VMD host bridge driver: - Fix disable of bridge windows during domain reset; previously we cleared the base/limit registers, which actually left the windows enabled Marvell MVEBU PCIe controller driver: - Remove unused busn member Microchip PolarFlare PCIe controller driver: - Fix interrupt bit definitions so the SEC and DED interrupt handlers work correctly - Make driver buildable as a module - Read FPGA MSI configuration parameters from hardware instead of hard-coding them Microsoft Hyper-V host bridge driver: - To avoid a NULL pointer dereference, skip MSI restore after hibernate if MSI/MSI-X hasn't been enabled NVIDIA Tegra194 PCIe controller driver: - Revert 'PCI: tegra194: Enable support for 256 Byte payload' because Linux doesn't know how to reduce MPS from to 256 to 128 bytes for endpoints below a switch (because other devices below the switch might already be operating), which leads to 'Malformed TLP' errors Qualcomm PCIe controller driver: - Add DT and driver support for interconnect bandwidth voting for 'pcie-mem' and 'cpu-pcie' interconnects - Fix broken SDX65 'compatible' DT property - Configure controller so MHI bus master clock will be switched off while in ASPM L1.x states - Use alignment restriction from EPF core in EPF MHI driver - Add Endpoint eDMA support - Add MHI eDMA support - Add Snapdragon SM8450 support to the EPF MHI driversupport - Add MHI eDMA support - Add Snapdragon SM8450 support to the EPF MHI driversupport - Add MHI eDMA support - Add Snapdragon SM8450 support to the EPF MHI driversupport - Add MHI eDMA support - Add Snapdragon SM8450 support to the EPF MHI driver - Use iATU for EPF MHI transfers smaller than 4K to avoid eDMA setup latency - Add sa8775p DT binding and driver support Rockchip PCIe controller driver: - Use 64-bit mask on MSI 64-bit PCI address to avoid zeroing out the upper 32 bits SiFive FU740 PCIe controller driver: - Set the supported number of MSI vectors so we can use all available MSI interrupts Synopsys DesignWare PCIe controller driver: - Add generic dwc suspend/resume APIs (dw_pcie_suspend_noirq() and dw_pcie_resume_noirq()) to be called by controller driver suspend/resume ops, and a controller callback to send PME_Turn_Off MicroSemi Switchtec management driver: - Add support for PCIe Gen5 devices Miscellaneous: - Reorder and compress to reduce size of struct pci_dev - Fix race in DOE destroy_work_on_stack() - Add stubs to avoid casts between incompatible function types - Explicitly include correct DT includes to untangle headers" * tag 'pci-v6.6-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (96 commits) PCI: qcom-ep: Add ICC bandwidth voting support dt-bindings: PCI: qcom: ep: Add interconnects path PCI: qcom-ep: Treat unknown IRQ events as an error dt-bindings: PCI: qcom: Fix SDX65 compatible PCI: endpoint: Add kernel-doc for pci_epc_mem_init() API PCI: epf-mhi: Use iATU for small transfers PCI: epf-mhi: Add support for SM8450 PCI: epf-mhi: Add eDMA support PCI: qcom-ep: Add eDMA support PCI: epf-mhi: Make use of the alignment restriction from EPF core PCI/PM: Only read PCI_PM_CTRL register when available PCI: qcom: Add support for sa8775p SoC dt-bindings: PCI: qcom: Add sa8775p compatible PCI: qcom-ep: Pass alignment restriction to the EPF core PCI: Simplify pcie_capability_clear_and_set_word() control flow PCI: Tidy config space save/restore messages PCI: Fix code formatting inconsistencies PCI: Fix typos in docs and comments PCI: Fix pci_bus_resetable(), pci_slot_resetable() name typos PCI: Simplify pci_dev_driver() ...
| * PCI: dwc: Implement generic suspend/resume functionalityFrank Li2023-08-241-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce an helper function (dw_pcie_get_ltssm()) to retrieve SMLH_LTSS_STATE. Add common dw_pcie_suspend(resume)_noirq() API to implement the DWC controller generic suspend/resume functionality. Add a controller specific callback to send the PME_Turn_Off message (ie .pme_turn_off) for controller platform specific PME handling. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Frank Li <[email protected]> [[email protected]: commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
* | Revert "PCI: dwc: Wait for link up only if link is started"Johan Hovold2023-07-261-9/+4
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit da56a1bfbab55189595e588f1d984bdfb5cf5924. Bjorn Andersson, Fabio Estevam, Xiaolei Wang, and Jon Hunter reported that da56a1bfbab5 ("PCI: dwc: Wait for link up only if link is started") broke controller probing by returning an error in case the link does not come up during host initialisation, for example when the slot is empty. As explained in commit 886a9c134755 ("PCI: dwc: Move link handling into common code") and as indicated by the comment "Ignore errors, the link may come up later" in the code, waiting for link up and ignoring errors is the intended behaviour: Let's standardize this to succeed as there are usecases where devices (and the link) appear later even without hotplug. For example, a reconfigured FPGA device. Reverting the offending commit specifically fixes a regression on Qualcomm platforms like the Lenovo ThinkPad X13s which no longer reach the interconnect sync state if a slot does not have a device populated (e.g. an optional modem). Note that enabling asynchronous probing by default as was done for Qualcomm platforms by commit c0e1eb441b1d ("PCI: qcom: Enable async probe by default"), should take care of any related boot time concerns. Finally, note that the intel-gw driver is the only driver currently not providing a .start_link() callback and instead starts the link in its .host_init() callback, which may avoid an additional one-second timeout during probe by making the link-up wait conditional. If anyone cares, that can be done in a follow-up patch with a proper motivation. [bhelgaas: add Fabio Estevam, Xiaolei Wang, Jon Hunter reports] Fixes: da56a1bfbab5 ("PCI: dwc: Wait for link up only if link is started") Link: https://lore.kernel.org/r/[email protected] Reported-by: Bjorn Andersson <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Reported-by: Fabio Estevam <[email protected]> Link: https://lore.kernel.org/r/[email protected]/ Reported-by: Xiaolei Wang <[email protected]> Link: https://lore.kernel.org/r/[email protected]/ Reported-by: Jon Hunter <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Cc: Sajid Dalvi <[email protected]> Cc: Ajay Agarwal <[email protected]>
* PCI: dwc: Wait for link up only if link is startedAjay Agarwal2023-05-261-4/+9
| | | | | | | | | | | | | | | | | In dw_pcie_host_init() regardless of whether the link has been started or not, the code waits for the link to come up. Even in cases where start_link() is not defined the code ends up spinning in a loop for 1 second. Since in some systems dw_pcie_host_init() gets called during probe, this one second loop for each pcie interface instance ends up extending the boot time. Wait for the link up in only if the start_link() is defined. Link: https://lore.kernel.org/r/[email protected] Tested-by: Will McVicker <[email protected]> Signed-off-by: Sajid Dalvi <[email protected]> Signed-off-by: Ajay Agarwal <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
* PCI: dwc: Add Root Port and Endpoint controller eDMA engine supportSerge Semin2023-02-221-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the DW eDMA core now supports eDMA controllers embedded in locally accessible DW PCIe Root Ports and Endpoints, register these controllers when possible. To do that the DW PCIe core driver needs to perform some preparations first. First of all, it needs to find the eDMA controller CSRs base address, whether they are accessible over the Port Logic or iATU unrolled space. Afterwards it can try to auto-detect the eDMA controller availability and number of read/write channels. If none are found the procedure silently returns without error. Secondly, the platform is supposed to provide either combined or per-channel IRQ signals. If no valid IRQs set is found, the procedure returns without error to be backward compatible with platforms where DW PCIe controllers have eDMA but lack the IRQ description. Finally, before actually probing the eDMA device we need to allocate LLP items buffers. After that the DW eDMA can be registered. If registration is successful, a message regarding the number of detected Read/Write eDMA channels will be printed to the system as is done for the iATU settings. Note: the DW PCI controller driver (either host or endpoint mode) is currently always built-in, so if the DW eDMA core is built as a module (CONFIG_DW_EDMA=m), eDMA controllers will not be registered even if the dw-edma module is later loaded. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Acked-by: Vinod Koul <[email protected]>
* PCI: dwc: Restrict only coherent DMA mask for MSI address allocationSerge Semin2023-02-221-1/+11
| | | | | | | | | | | | | | | | | | | | | The MSI target address must be in the lowest 4GB memory to support PCI peripherals without 64-bit MSI support. Since the allocation is done from DMA coherent memory, set only the coherent DMA mask, leaving the streaming DMA mask alone. Thus streaming DMA operations will work with no artificial limitations. It will be specifically useful for the eDMA-capable controllers so the corresponding DMA engine clients would map the DMA buffers with no need for SWIOTLB for buffers allocated above 4GB. Add a brief comment about the reason allocating the MSI target address below 4GB. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Robin Murphy <[email protected]>
* PCI: dwc: Introduce generic resources getterSerge Semin2022-11-231-11/+4
| | | | | | | | | | | | | | | | | | | | | | | | Currently the DW PCIe Root Port and Endpoint CSR spaces are retrieved in the separate parts of the DW PCIe core driver. It doesn't really make sense since the both controller types have identical set of the core CSR regions: DBI, DBI CS2 and iATU/eDMA. Thus we can simplify the DW PCIe Host and EP initialization methods by moving the platform-specific registers space getting and mapping into a common method. It gets to be even more justified seeing the CSRs base address pointers are preserved in the common DW PCIe descriptor. Note all the OF-based common DW PCIe settings initialization will be moved to the new method too in order to have a single function for all the generic platform properties handling in single place. A nice side-effect of this change is that the pcie-designware-host.c and pcie-designware-ep.c drivers are cleaned up from all the direct dw_pcie storage modification, which makes the DW PCIe core, Root Port and Endpoint modules more coherent. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
* PCI: dwc: Introduce dma-ranges property support for RC-hostSerge Semin2022-11-231-3/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In accordance with the generic PCIe Root Port DT-bindings the "dma-ranges" property has the same format as the "ranges" property. The only difference is in their semantics. The "dma-ranges" property describes the PCIe-to-CPU memory mapping in opposite to the CPU-to-PCIe mapping of the "ranges" property. Even though the DW PCIe controllers are normally equipped with the internal Address Translation Unit which inbound and outbound tables can be used to implement both properties semantics, it was surprising for me to discover that the host-related part of the DW PCIe driver currently supports the "ranges" property only while the "dma-ranges" windows are just ignored. Having the "dma-ranges" supported in the driver would be very handy for the platforms, that don't tolerate the 1:1 CPU-PCIe memory mapping and require a customized PCIe memory layout. So let's fix that by introducing the "dma-ranges" property support. First of all we suggest to rename the dw_pcie_prog_inbound_atu() method to dw_pcie_prog_ep_inbound_atu() and create a new version of the dw_pcie_prog_inbound_atu() function. Thus we'll have two methods for the RC and EP controllers respectively in the same way as it has been developed for the outbound ATU setup methods. Secondly aside with the memory window index and type the new dw_pcie_prog_inbound_atu() function will accept CPU address, PCIe address and size as its arguments. These parameters define the PCIe and CPU memory ranges which will be used to setup the respective inbound ATU mapping. The passed parameters need to be verified against the ATU ranges constraints in the same way as it is done for the outbound ranges. Finally the DMA-ranges detected for the PCIe controller need to be converted to the inbound ATU entries during the host controller initialization procedure. It will be done in the framework of the dw_pcie_iatu_setup() method. Note before setting the inbound ranges up we need to disable all the inbound ATU entries in order to prevent unexpected PCIe TLPs translations defined by some third party software like bootloaders. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* PCI: dwc: Drop dependency on ZONE_DMA32Will McVicker2022-08-291-21/+7
| | | | | | | | | | | | | | | | | Re-work the msi_msg DMA allocation logic to use dmam_alloc_coherent() which uses the coherent DMA mask to try to return an allocation within the DMA mask limits. With that, we now can drop the msi_page parameter in struct dw_pcie_rp. This allows kernel configurations that disable ZONE_DMA32 to continue supporting a 32-bit DMA mask. Without this patch, the PCIe host device will fail to probe when ZONE_DMA32 is disabled. Link: https://lore.kernel.org/r/[email protected] Fixes: 35797e672ff0 ("PCI: dwc: Fix MSI msi_msg DMA mapping") Reported-by: Isaac J. Manjarres <[email protected]> Signed-off-by: Will McVicker <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Jingoo Han <[email protected]>
* PCI: dwc: Handle MSIs routed to multiple GIC interruptsDmitry Baryshkov2022-08-011-3/+58
| | | | | | | | | | | | | | | | | On some Qualcomm platforms each group of 32 MSI vectors is routed to a separate GIC interrupt. Implement support for such configurations by parsing "msi0" ... "msiX" interrupts and attaching them to the chained handler. Note that if DT doesn't list an array of MSI interrupts and uses a single "msi" IRQ, the driver will limit the number of supported MSI vectors to 32. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* PCI: dwc: Convert struct pcie_port.msi_irq to an arrayDmitry Baryshkov2022-08-011-11/+18
| | | | | | | | | | | | | | | The Qualcomm DWC PCIe controller supports more than 32 MSI interrupts, but they are routed to separate interrupts in groups of 32 vectors. To support this configuration, change the msi_irq field to an array. Let the DWC core handle all interrupts that were set in this array. [bhelgaas: reorder, drop "irq" temporary to make patch cleaner] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* PCI: dwc: Split MSI IRQ parsing/allocation to a separate functionDmitry Baryshkov2022-08-011-42/+54
| | | | | | | | | | | | | Split handling of MSI host IRQs to a separate dw_pcie_msi_host_init() function. The code is complex enough to warrant a separate function. [bhelgaas: reorder patch earlier] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi()Dmitry Baryshkov2022-08-011-1/+1
| | | | | | | | | | | | | | | | The dwc-based drivers set pp->msi_irq to -ENODEV if they do not want the dwc core to do anything with pp->msi_irq. dw_pcie_host_init() sets the handler and data when "pp->msi_irq > 0", so use the same condition when removing the handler and data in dw_pcie_free_msi(). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* PCI: dwc: Fix MSI msi_msg DMA mappingWill McVicker2022-08-011-6/+8
| | | | | | | | | | | | | | | | | | | | | As of 07940c369a6b ("PCI: dwc: Fix MSI page leakage in suspend/resume"), the PCIe designware host driver has been using the driver data allocation for the msi_msg DMA mapping which can result in a DMA_MAPPING_ERROR due to the DMA overflow check in dma_direct_map_page() when the address is greater than 32 bits (reported in [1]). The commit was trying to address a memory leak on suspend/resume by moving the MSI mapping to dw_pcie_host_init(), but subsequently dropped the page allocation thinking it wasn't needed. To fix the DMA mapping issue as well as make msi_msg DMA'able, switch back to allocating a 32-bit page for the msi_msg. To avoid the suspend/resume leak, allocate the page in dw_pcie_host_init() since that shouldn't be called during suspend/resume. [1] https://lore.kernel.org/all/[email protected]/ Signed-off-by: Will McVicker <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]>
* PCI: dwc: Check iATU in/outbound range setup statusSerge Semin2022-08-011-53/+100
| | | | | | | | | | | | | | | | Make the DWC PCIe RC/EP safer and more verbose for invalid or failed inbound and outbound iATU window setups. Silently ignoring iATU regions setup errors may cause unpredictable errors. For instance if a cfg or IO window fails to be activated, then any CFG/IO requested won't reach target PCIe devices and the corresponding accessors will return platform-specific random values. [bhelgaas: trim commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* PCI: dwc: Drop enum dw_pcie_region_type in favor of PCIE_ATU_REGION_DIR_IB/OBSerge Semin2022-08-011-1/+1
| | | | | | | | | | | | | | | | | | | | Previously callers of dw_pcie_disable_atu() supplied enum dw_pcie_region_type (DW_PCIE_REGION_INBOUND, DW_PCIE_REGION_OUTBOUND), which dw_pcie_disable_atu() converted to the PCIE_ATU_REGION_DIR_IB or PCIE_ATU_REGION_DIR_OB values needed to program the ATU registers. Simplify the code by dropping the dw_pcie_region_type enum and passing PCIE_ATU_REGION_DIR_IB or PCIE_ATU_REGION_DIR_OB directly. Reorder dw_pcie_disable_atu() arguments to (dir, index) since "index" indicates an ATU window in the regions of the corresponding direction. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* PCI: dwc: Add dw_pcie_ops.host_deinit() callbackSerge Semin2022-08-011-5/+16
| | | | | | | | | | | | | dw_pcie_host_init() calls the dw_pcie_ops.host_init() callback to do platform-specific host initialization. Add a dw_pcie_ops.host_deinit() callback to perform the corresponding cleanups in dw_pcie_host_deinit() and in dw_pcie_host_init() failure paths. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* PCI: dwc: Read DWC IP core version from registerSerge Semin2022-08-011-0/+2
| | | | | | | | | | | | | | | | | | | Since DWC PCIe v4.70a, the controller version and version type can be read from the PORT_LOGIC.PCIE_VERSION_OFF and PORT_LOGIC.PCIE_VERSION_TYPE_OFF registers respectively. Read the version from those registers and warn if if's different from the version we got from the device tree. We can only read the version after platform-specific drivers have done any DBI-related initialization, such as reference clock activation. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* PCI: dwc: Rename struct pcie_port to dw_pcie_rpSerge Semin2022-07-061-18/+18
| | | | | | | | | | | | | | | | | | All of the DW PCIe core driver entities except the pcie_port struct have names with the "dw_" prefix to distinguish local and common PCIe name spaces, and endpoint-related entities have an "_ep" suffix. Rename struct pcie_port to dw_pcie_rp to make it more consistent with other names. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Acked-by: Jesper Nilsson <[email protected]>
* PCI: dwc: Move io_cfg_atu_shared to struct pcie_portSerge Semin2022-07-061-3/+3
| | | | | | | | | | | | | | | | The io_cfg_atu_shared flag is set if there is an outbound iATU window used for both config space accesses and IO port transfers. Since the flag semantic is purely Root Port specific, it's not used in either the DW PCIe common code or in the DW PCIe Endpoint driver. Move it to the struct pcie_port and rename to cfg0_io_shared. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* PCI: dwc: Add start_link/stop_link inlinesSerge Semin2022-07-061-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Factor out this pattern: if (!pci->ops || !pci->ops->start_link) return -EINVAL; return pci->ops->start_link(pci); into a new dw_pcie_start_link() wrapper and do the same for the stop_link() method. Note that dw_pcie_ep_start() previously returned -EINVAL if there was no platform start_link() method, which didn't make much sense since that is not an error. It will now return 0 in that case. As a side-effect, drop the empty start_link() and dummy dw_pcie_ops instances from the generic DW PCIe and Layerscape EP platform drivers. [bhelgaas: commit log] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
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