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path: root/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
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* drm/amd/display: Refactor HWSS into component folderMounika Adhuri2023-10-091-493/+0
| | | | | | | | | | | | | | | | | | | [why] Rename hw_sequencer to hwseq. Move all hwseq files to unique folder hwss. [how] creating hwss repo in dc, and moved the dcnxx_hwseq.c and .h files into corresponding new folders inside the hwss and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by: Martin Leung <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Mounika Adhuri <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Adjust code style for hw_sequencer.hAurabindo Pillai2023-10-041-33/+23
| | | | | | | | | | | [Why&How] * Rearrange some definitions for consistency * Drop legacy code Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Improve x86 and dmub ips handshakeDuncan Ma2023-09-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | [Why] There is a race condition between x86 and dmcub fw when attempting to exit IPS2. Scenarios including exiting IPS2 before IPS2 has been entered. This can cause unexpected hang when DMCUB attempt to exit while PMFW still tries to enter IPS2. [How] A new design has been introduced to remove race conditions and improve the handshake between x86 and DMCUB. An AON scratch register is borrowed from PMFW to determine whether DMCUB has committed to IPS entry or not. In the case when dmcub has committed IPS entry, x86 must poll until an exit event occurred either from DMCUB(IPS1) or PMFW(IPS2). x86 will wait upperbound of evaluation and IPS entry time to ensure IPS2 exit event has been sent to PMFW. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Duncan Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add seamless pipe topology transition checkWenjing Liu2023-09-111-0/+3
| | | | | | | | | | | | | | | [why] We have a few cases where we need to perform update topology update in dc update interface. However some of the updates are not seamless This could cause user noticible glitches. To enforce seamless transition we are adding a checking condition and error logging so the corruption as result of non seamless transition can be easily spotted. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Blank phantom OTG before enablingAlvin Lee2023-09-111-0/+5
| | | | | | | | | | | | [Description] Before enabling the phantom OTG for an update we must enable DPG to avoid underflow. Reviewed-by: Samson Tam <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add DCN35 HWSEQQingqing Zhuo2023-08-301-0/+10
| | | | | | | | | [Why & How] Add HWSEQ handling for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Write flip addr to scratch reg for subvpAlvin Lee2023-08-301-0/+10
| | | | | | | | | | | | | | | | | [Description] SubVP needs to "calculate" the earliest in use META address by using the current primary / meta addresses, but this leads to a race condition where FW and driver can read/write the address at the same time and intermittently produce inconsistent address offsets. To mitigate this issue without locking (too slow), save each surface flip addr into scratch registers and use this to keep track of the earliest in use META addres. Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Include CSC updates in new fast update pathAlvin Lee2023-06-151-0/+32
| | | | | | | | | | | | | | [Description] - Missed color / CSC updates in fast update path which caused Custom Color to break. - Add color / CSC updates to new fast update path to fix custom color Acked-by: Stylon Wang <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Reviewed-by: Jun Lei <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Refactor fast update to use new HWSS build sequenceAlvin Lee2023-06-091-0/+126
| | | | | | | | | | | | | | [Description] - Refactor HW sequencer to use a build / execute sequence - Also move gamma updates to become fast v2: squash in build fix ("drm/amd/display: Fix guarding of 'if (dc->debug.visual_confirm)'") Acked-by: Stylon Wang <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Reviewed-by: Jun Lei <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add visual confirm color support for MCLK switchLeo (Hanghong) Ma2023-06-091-1/+8
| | | | | | | | | | | | | | | [Why && How] We would like to have visual confirm color support for MCLK switch. 1. Set visual confirm color to yellow: Vblank MCLK switch. 2. Set visual confirm color to cyan: FPO + Vblank MCLK switch. 3. Set visual confirm color to pink: Vactive MCLK switch. Reviewed-by: Jun Lei <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Leo (Hanghong) Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Turn on phantom OTG before disabling phantom pipeAlvin Lee2023-01-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | [Description] - Proper phantom pipe disable sequence was missing in commit_planes_for_stream - If disabling phantom pipe, turn on phantom OTG first, and turn off the phantom OTG after the plane is disabled - Also update sequence for enabling / disabling phantom streams (apply_ctx_to_hw). When enabling phantom pipes, enable before doing front end programming for phantom pipes. If disabling phantom pipes, disable after front end programming (i.e. after phantom plane disable) - TODO: Still need to properly handle transition case when a phantom pipe is transitioned directly into a real pipe (need to fully disable the phantom pipe first) Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Reviewed-by: Jun Lei <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix Subvp phantom pipe transitionAlvin Lee2022-11-151-0/+1
| | | | | | | | | | | | | | | | | [Description] - When transitioning a pipe in use (non-phantom) to become a phantom pipe, we must fully disable the pipe first before doing any phantom pipe programming - Move phantom OTG enablement to after "regular" front-end programming sequence (including wait for vupdate) - If a pipe is being transitioned into a phantom pipe, fully disable it first Reviewed-by: Jun Lei <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix various dynamic ODM transitions on DCN32Dillon Varone2022-09-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why&How] Several transitions were fixed that will allow Dynamic ODM and MPO transitions to be supported on DCN32. 1) Due to resource limitations, in certain scenarios that require an MPO plane to be split, the features cannot be combined with the current policy. This is due to unsafe transitions being required (OPP instance per MPCC being switched on active pipe is not supported by DCN), to support the split plane with ODM active as it moves across the viewport. Dynamic ODM will now be disabled when MPO is required. 2) When exiting MPO and re-entering ODM, DC assigns an inactive pipe for the next ODM pipe, which under previous power gating policy would result in programming a gated DSC HW block. New policy dynamically gates/un-gates DSC blocks when Dynamic ODM is active to support transitions on DCN32 only. 3) Entry and exit from 3 plane MPO and Dynamic ODM requires a minimal transition so that all pipes which require their MPCC OPP instance to be changed have a full frame to be disabled before reprogramming. To solve this, the Dynamic ODM policy now utilizes minimal state transitions when entering or exiting 3 plane scenarios. 4) Various fixes to DCN32 pipe merge/split algorithm to support Dynamic ODM and MPO transitions. In summary, this commit fixes various transitions to support ODM->MPO and MPO->ODM. Reviewed-by: Martin Leung <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Remove interface for periodic interrupt 1Aric Cyr2022-09-291-7/+1
| | | | | | | | | | | | | | | [why] Only a single VLINE interrupt is available so interface should not expose the second one which is used by DMU firmware. [how] Remove references to periodic_interrupt1 and VLINE1 from DC interfaces. Reviewed-by: Jaehyun Chung <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: rework recent update PHY state commitWenjing Liu2022-09-191-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] Original change 594b237b9a07 ("drm/amd/display: Add interface to track PHY state") was implemented by assuming stream's dpms off is equivalent to PHY power off. This assumption doesn't hold in following situations: 1. MST multiple stream scenario, where multiple streams are sharing the same PHY output. Toggle dpms off for one of the stream doesn't power off the PHY due to the presence of other streams. 2. enable stream failure scenario, where enable stream fails due to failure of link training. This will cause DPMS off is set to false, while the actual PHY power state is off in certain cases. Due to the problematic assumption, the logic will skip disabling other streams for MST multiple stream scenario, therefore PHY is not actually powered off. [how] 1. Rework this refactor by moving PHY state update down to hardware level, where we update PHY state in place when hardware sequencer is actually changing the power state of the PHY hardware. 2. Reimplement symclk on TX off workaround in place when we are actually calling transmitter control to power off PHY in dcn32. Note the workaround is added due to the lack of proper software interface to set TX while keeping symclk on. We plan to address this interface problem so we can set TX off only without affecting symclk in future dcn versions. Fixes: 594b237b9a07 ("drm/amd/display: Add interface to track PHY state") Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Update viewport position for phantom pipesAlvin Lee2022-09-131-0/+5
| | | | | | | | | | | | | [Description] In some cases the viewport position of the main pipes can change without triggering a full update. In this case the subvp phantom viewports must be updated accordingly. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add visual confirm color support for SubVPLeo (Hanghong) Ma2022-08-291-0/+5
| | | | | | | | | | | | | | | | | [Why && How] We would like to have visual confirm color support for SubVP. 1. Set visual confirm color to red: SubVP is enable on this display; 2. Set visual confirm color to green: SubVP is enable on other display and DRR is on this display; 3. Set visual confirm color to blue: SubVP is enable on other display and DRR is off on this display; Reviewed-by: Alvin Lee <[email protected]> Acked-by: Brian Chang <[email protected]> Signed-off-by: Leo (Hanghong) Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add interface to track PHY stateAlvin Lee2022-08-251-0/+2
| | | | | | | | | | | | | | | | [Why] Sometimes pixel clock needs to remain active after transmitter disable. [How] Use update_phy_state to track PHY state after stream enable/disable and program pixel clock as needed. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Brian Chang <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add SubVP required codeAlvin Lee2022-07-051-0/+7
| | | | | | | | | | | | | | | | | | | This commit enables the SubVP feature. To achieve that, we need to: - Don't force p-state disallow on SubVP (can't block dummy p-state) - Send calculated watermark to DMCUB for SubVP - Adjust CAB mode message to PMFW - Add a proper locking sequence for SubVP - Various fixes to SubVP static analysis and determining SubVP config - Currently SubVP not supported with pipe split so merge all pipes before setting up SubVp Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add dependant changes for DCN32/321Aurabindo Pillai2022-06-031-0/+2
| | | | | | | | | | | | [Why&How] This patch adds necessary changes needed in DC files outside DCN32/321 specific tree v2: squash in updates (Alex) Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: implement dc_mode_memclkMartin Leung2021-12-141-0/+1
| | | | | | | | | | | | | | | | | | | | | why: Need interface to lower clocks when in dc (power save) mode. Must be able to work with p_state unsupported cases Can cause flicker when OS notifies us of dc state change how: added dal3 interface for KMD added pathway to query smu for this softmax added blank before clock change to override underflow added logic to change clk based on pstatesupport and softmax added logic in prepare/optimize_bw to conform while changing clocks Reviewed-by: Aric Cyr <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Martin Leung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add periodic detection when zstate is enabledEric Yang2021-09-141-1/+1
| | | | | | | | | | | | | | | | [Why] When system is in Z10 HPD interrupts cannot fire, we may miss display configuration changes. [How] When Zstate is enabled, if DMUB indicate DCN has lost power, do a complete detection periodically. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Mikita Lipski <[email protected]> Signed-off-by: Eric Yang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Ensure DCN save after VM setupJake Wang2021-08-161-0/+1
| | | | | | | | | | | | | | | | | | [Why] DM initializes VM context after DMCUB initialization. This results in loss of DCN_VM_CONTEXT registers after z10. [How] Notify DMCUB when VM setup is complete, and have DMCUB save init registers. v2: squash in CONFIG_DRM_AMD_DC_DCN3_1 fix Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Jake Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCNAlex Deucher2021-06-221-2/+0
| | | | | | | | No need for a separate flag now that DCN3.1 is not in bring up. Fold into DRM_AMD_DC_DCN like previous DCN IPs. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add swizzle visual confirm modePo-Ting Chen2021-06-081-1/+3
| | | | | | | | | | | | [Why] To support a new visual confirm mode: swizzle to show the specific color at the screen border according to different surface swizzle mode. Currently we only support the Linear mode with red color. Signed-off-by: Po-Ting Chen <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Refactor visual confirmWyatt Wood2021-06-081-0/+16
| | | | | | | | | | | | | | | | | | | | [Why + How] Visual confirm has no asic-specific logic, so we can refactor and unify these functions that are currently spread out across multiple dcn files. Add a new hw sequencer interface update_visual_confirm_color, and a new mpc function pointer set_bg_color. This will allow visual confirm to updated independently of MPCC blending updates. v2: squash in DCN3.1 fixes Signed-off-by: Wyatt Wood <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add DCN3.1 HWSEQNicholas Kazlauskas2021-06-041-0/+4
| | | | | | | | | | | Add DCN3.1 specific hardware sequence programming - extending off of our existing DCN3/DCN2 support. Extend stream hardware sequencing to include new DCCG programming. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Revert "drm/amd/display: Refactor and add visual confirm for HW Flip Queue"Qingqing Zhuo2021-05-271-4/+0
| | | | | | | | | | | | | | This reverts commit 3ca402375a2197579d1029e7fa9d856847fe0e7b. Recent visual confirm changes are regressing the driver, causing a black screen on boot in some green sardine configs, or visual confirm is not updated at all. Signed-off-by: Qingqing Zhuo <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Refactor and add visual confirm for HW Flip QueueWyatt Wood2021-05-201-0/+4
| | | | | | | | | | | | | | | | | | | | | | | [Why] Visual confirm will indicate if driver is programming the surface address. Refactor is required because much of the visual confirm logic is buried deep in the mpcc files. In addition, visual confirm is not updated during fast updates. [How] In order to have visual confirm for driver flips, visual confirm needs to be updated on every frame, including fast updates. Add a new hw sequencer interface update_visual_confirm_color, and a new mpc function pointer set_bg_color. v2: drop unused variable (Alex) Signed-off-by: Wyatt Wood <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add function and debugfs to dump DCC_EN bitVictor Lu2021-04-091-0/+2
| | | | | | | | | | | | | | | | | | | [why] Currently to view the DCC_EN bit the entire DTN log must be dumped. A compact method to view the DCC_EN bit is desirable. [how] Introduce new debugfs interface that only dumps the DCC_EN bit. Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en Signed-off-by: Victor Lu <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Change input parameter for set_drrAlvin Lee2021-04-091-2/+1
| | | | | | | | | | | | | | [Why] Change set_drr to pass in the entire dc_crtc_timing_adjust structure instead of passing in the parameters individually. This is to more easily pass in required parameters in the adjust structure when it gets updated. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Solomon Chiu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Synchronize displays with different timingsVladimir Stempen2021-02-221-0/+3
| | | | | | | | | | | | | | | [why] Vendor based fan noise improvement [how] Report timing synchronizable when DP streams time frame difference is less than 0.05 percent. Adjust DP DTOs and sync displays using MASTER_UPDATE_LOCK_DB_X_Y Signed-off-by: Vladimir Stempen <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Old sequence for HUBP blankAurabindo Pillai2021-02-181-4/+0
| | | | | | | | | | | | New proposed sequence for HUBP blanking causes regressions where the hardware would fail to enter blank which triggers an assert in the new sequence. This change brings back the old sequence. Fixes: 985faf2c4ecb60 ("drm/amd/display: New sequence for HUBP blank") Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Dynamic cursor cache size for MALL eligibility checkBhawanpreet Lakha2021-01-211-1/+2
| | | | | | | | | | | | | | | | [Why] Currently we use the maximum possible cursor cache size when deciding if we should attempt to enable MALL, but this prevents us from enabling the feature for certain key use cases. [How] - consider cursor bpp when calculating if the cursor fits Signed-off-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: New sequence for HUBP blankWesley Chalmers2021-01-141-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | [WHY] DCN30 has a bug where blanking HUBP blocks pstate allow unless HUBP_DISABLE is toggled afterwards. [HOW] Create a HW sequence for blanking HUBP. 1. Wait for enter VBLANK 2. Set HUBP_BLANK 3. Make sure HUBP_IN_BLANK = 1 4. Toggle HUBP_DISABLE on and off to perform soft reset All existing calls to hubp->funcs->set_blank should be replaced with this new sequence. In wait_for_mpcc_disconnect, only blank the pipe being disconnected, and leave all other pipes unmodified. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: implement T12 complianceJun Lei2021-01-141-0/+1
| | | | | | | | | | | | | | | | | | [why] When OS reboots, and panel is turned off, T12 may not be maintained. T12 is defined as the interval between VDDC off (occurs at shutdown) and the next VDDC on (occurs when eDP is POST-ed) [how] DC already tracks panel power off time. Add a DC interface which DM can call during shutdown. Ideally this should be as late as possible during the shutdown sequence so the extra delay is minimal. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Update idle optimization handlingJoshua Aberback2021-01-051-0/+2
| | | | | | | | | | | | [How] - use dc interface instead of hwss interface in cursor functions, to keep dc->idle_optimizations_allowed updated - add dc interface to check if idle optimizations might apply to a plane Signed-off-by: Joshua Aberback <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)Alex Deucher2020-11-041-4/+0
| | | | | | | | | | Avoids confusion in configurations. v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code Reviewed-by: Luben Tuikov <[email protected]> (v1) Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Blank HUBP during pixel data blank for DCN30 v2Joshua Aberback2020-11-021-0/+8
| | | | | | | | | | | | | | | | | | | [Why] Prior commit "Blank HUBP during pixel data blank for DCN30" missed the call to set_disp_pattern_generator from set_crtc_test_pattern, which re-exposed the issue for which we initially blocked active-only p-state switching. [How] - remove dcn30_blank_pixel_data, set dcn30 back to dcn20 version - new hwss funciton set_disp_pattern_generator - dcn20 version just calls opp_set_disp_pattern_generator - dcn30 version implements the HUBP blank Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Update GSL state if leaving immediate flipAlvin Lee2020-10-261-2/+0
| | | | | | | | | | | | | | | | | [Why] We should leave GSL if we're not doing immediate flip no matter if we're doing pipe split or not [How] Check for updating GSL state whenever we're not doing immediate flip v2: Squash in build fix (Alex) Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Revert check for flip pending before locking pipesIsabel Zhang2020-10-261-1/+1
| | | | | | | | | | | | [Why] Causes underflow regression [How] This reverts commit 99d1437aa0ac1f598e9aabca8bf0e8a40c38f8a1 Signed-off-by: Isabel Zhang <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Block ABM in case of eDP ODMYongqiang Sun2020-10-051-0/+2
| | | | | | | | | | | | | | [Why] enable ODM on eDP panel with ABM will result in color difference on the panel due to only one ABM module to set one pipe. [How] Block ABM in case of ODM enabled on eDP. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Force enable pstate on driver unloadJoshua Aberback2020-10-051-0/+3
| | | | | | | | | | | | | | | | | | | | | | | [Why] During driver unload, it is expected that p-state switching is supported. If it's not supported, PMFW will hang due to a forced p-state switch. Even if the current timing does not support p-state normally, we still want to force allow because the worst that can happen is underflow. This will match Navi10 behaviour. [How] - new hubbub func to control the force pstate register - force allow when releasing display ownership - registers are inaccessible after due to m_cgs.hwNotAvailable - explicitly disable force signal during hw_init - if driver is disabled and re-enabled, register not cleared otherwise Also, remove DCN3 part of dcn10_init_hw, we will not be going back to it. Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Check for flip pending before locking pipesAric Cyr2020-10-051-1/+1
| | | | | | | | | | | | | | | | | | | [Why] When running games or benchmarking with v-sync disabled, disabling a plane (which is v-sync) can cause underflow. This is caused by flips pending before pipe locking being applied after locks are released and pipes could have been re-arranged or disconnected. This could potentially apply a flip on incorrect pipe. Also, previous logic of always locking pipes was unnecessary. [How] Only lock the pipes when there is a pipe being disabled to increase efficiency. Before the pipes are locked, check that any pending flips are cleared to ensure the flips are applied to the correct pipe. Signed-off-by: Aric Cyr <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Revert check for flip pending before locking pipesAric Cyr2020-09-291-1/+1
| | | | | | Signed-off-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Check for flip pending before locking pipes.Taimur Hassan2020-09-221-1/+1
| | | | | | | | | | | | | | | | | | [Why] When running a game/benchmark with v-sync disabled, disabling a plane (which is v-sync) can cause an underflow. This is due to flips that are pending before pipe locking being applied after locks are released and pipes have been re-arranged or disconnected. This can potentially apply a flip on the incorrect pipe. [How] Check that any pending flips are cleared before locking any pipes to ensure flips are applied on the correct pipes. Signed-off-by: Taimur Hassan <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Disconnect pipe separetely when disable pipe splitAlvin Lee2020-08-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | | [Why] When changing pixel formats for HDR (e.g. ARGB -> FP16) there are configurations that change from 2 pipes to 1 pipe. In these cases, it seems that disconnecting MPCC and doing a surface update at the same time(after unlocking) causes some registers to be updated slightly faster than others after unlocking (e.g. if the pixel format is updated to FP16 before the new surface address is programmed, we get corruption on the screen because the pixel formats aren't matching). We separate disconnecting MPCC from the rest of the pipe programming sequence to prevent this. [How] Move MPCC disconnect into separate operation than the rest of the pipe programming. Signed-off-by: Alvin Lee <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Revert regressionAlvin Lee2020-08-101-4/+0
| | | | | | | | | | [Why] Caused pipe split regression Signed-off-by: Alvin Lee <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Separate pipe disconnect from rest of progrmamingAlvin Lee2020-08-041-0/+4
| | | | | | | | | | | | | | | | | | | | | | | [Why] When changing pixel formats for HDR (e.g. ARGB -> FP16) there are configurations that change from 2 pipes to 1 pipe. In these cases, it seems that disconnecting MPCC and doing a surface update at the same time(after unlocking) causes some registers to be updated slightly faster than others after unlocking (e.g. if the pixel format is updated to FP16 before the new surface address is programmed, we get corruption on the screen because the pixel formats aren't matching). We separate disconnecting MPCC from the rest of the pipe programming sequence to prevent this. [How] Move MPCC disconnect into separate operation than the rest of the pipe programming. Signed-off-by: Alvin Lee <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Allow asic specific FSFT timing optimizationReza Amini2020-07-301-0/+5
| | | | | | | | | | | | | [Why] Each asic can optimize best based on its capabilities [How] Optimizing timing for a new pixel clock Signed-off-by: Reza Amini <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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