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path: root/drivers/gpu/drm/amd/amdgpu/soc15d.h
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* drm/amdgpu: Add PACKET3_RUN_CLEANER_SHADER_9_0 for Cleaner Shader executionSrinivasan Shanmugam2025-04-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | This commit introduces the PACKET3_RUN_CLEANER_SHADER_9_0 definition, which is a command packet utilized to instruct the GPU to execute the cleaner shader for the GFX9.0 graphics architecture. The cleaner shader is a piece of GPU code that is responsible for clearing or initializing essential GPU resources, such as Local Data Share (LDS), Vector General Purpose Registers (VGPRs), and Scalar General Purpose Registers (SGPRs). Properly clearing these resources is vital for ensuring data isolation and security between different workloads executed on the GPU. When the GPU receives this packet, it fetches and runs the cleaner shader instructions from the specified location in the packet. Thus by preventing data leaks and ensuring that previous job states do not interfere with subsequent workloads. Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: update and cleanup PM4 headersAlex Deucher2025-02-131-0/+139
| | | | | | | | | | Consolidate PM4 definitions. Most of these were previously only defined in UMDs. Add them here as well and sync with latest packets. Also no need to include soc15d.h on gfx10+. Reviewed-by: Feifei Xu <[email protected]> Suggested-by: Saurabh Verma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Add PACKET3_RUN_CLEANER_SHADER for cleaner shader executionSrinivasan Shanmugam2024-08-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the PACKET3_RUN_CLEANER_SHADER definition. This packet is a command packet used to instruct the GPU to execute the cleaner shader. The cleaner shader is a piece of GPU code that is used to clear or initialize certain GPU resources, such as Local Data Share (LDS), Vector General Purpose Registers (VGPRs), and Scalar General Purpose Registers (SGPRs). Clearing these resources is important for ensuring data isolation between different workloads running on the GPU. The PACKET3_RUN_CLEANER_SHADER packet is used to trigger the execution of the cleaner shader on the GPU. The packet consists of a header followed by a RESERVED field, which is programmed to zero. When the GPU receives this packet, it fetches and executes the cleaner shader instructions from the location specified in the packet. The cleaner shader feature helps to enhances security and reliability by preventing data leaks between workloads. Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/amdgpu: command submission parser for JPEGDavid (Ming Qiang) Wu2024-08-131-0/+6
| | | | | | | | | Add JPEG IB command parser to ensure registers in the command are within the JPEG IP block. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: David (Ming Qiang) Wu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Modify unmap_queue format for gfx9 (v6)Jiadong.Zhu2022-12-021-0/+2
| | | | | | | | | | | | | | | | | | | | 1. Modify the unmap_queue package on gfx9. Add trailing fence to track the preemption done. 2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs. v2: Restyle code not to use ternary operator. v3: Modify code format. v4: Enable Mid-Command Buffer Preemption for gfx9 by default. v5: Optimize the flag bit set for emit_fence. v6: Modify log message for preemption timeout. Cc: Christian Koenig <[email protected]> Cc: Michel Dänzer <[email protected]> Cc: Luben Tuikov <[email protected]> Signed-off-by: Jiadong.Zhu <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintionAndrey Grodzovsky2020-05-141-1/+24
| | | | | | | | | | Add this for gfx10 and gfx9. v2: Fix identation Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add tmz bit in frame control packetHuang Rui2020-04-281-0/+1
| | | | | | | | | This patch adds tmz bit in frame control pm4 packet, and it will used in future. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add jpeg packet defines to soc15d.hBoyuan Zhang2018-06-151-0/+23
| | | | | | | | Add new packet for vcn jpeg, including condition checks, types and packet Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Merge branch 'drm-next-4.18' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2018-05-151-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next Main changes for 4.18. I'd like to do a separate pull for vega20 later this week or next. Highlights: - Reserve pre-OS scanout buffer during init for seemless transition from console to driver - VEGAM support - Improved GPU scheduler documentation - Initial gfxoff support for raven - SR-IOV fixes - Default to non-AGP on PowerPC for radeon - Fine grained clock voltage control for vega10 - Power profiles for vega10 - Further clean up of powerplay/driver interface - Underlay fixes - Display link bw updates - Gamma fixes - Scatter/Gather display support on CZ/ST - Misc bug fixes and clean ups [airlied: fixup v3d vs scheduler API change] Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Dave Airlie <[email protected]>
| * drm/amdgpu: optionally do a writeback but don't invalidate TC for IB fencesMarek Olšák2018-05-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | There is a new IB flag that enables this new behavior. Full invalidation is unnecessary for RELEASE_MEM and doesn't make sense when draw calls from two adjacent gfx IBs run in parallel. This will be the new default for Mesa. v2: bump the version Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | drm/amdgpu: Add GFXv9 TLB invalidation packet definitionFelix Kuehling2018-04-101-0/+5
|/ | | | | | | | Signed-off-by: Shaoyun Liu <[email protected]> Signed-off-by: Jay Cornwall <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Oded Gabbay <[email protected]> Signed-off-by: Oded Gabbay <[email protected]>
* drm/amdgpu: fix vega10 graphic hang issue in S3 testKen Wang2017-08-181-0/+1
| | | | | | | | | | mmVGT_INDEX_TYPE has no default value, need to make sure it's initialized when gfx is initialized. Signed-off-by: Ken Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/gfx9: move define to header fileAlex Deucher2017-05-241-0/+1
| | | | | | | | rather than defining it locally. Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu:new PM4 entry for VI/AIMonk Liu2017-05-241-0/+7
| | | | | | | | TMZ package will be used for VULKAN/CHAINED-IB MCBP Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add KIQ packet defines to soc15d.hAlex Deucher2017-05-241-0/+82
| | | | | | | | Will be used in subsequent commits rather rather than magic numbers. Reviewed-by: monk liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu:enable mcbp for gfx9(v2)Monk Liu2017-03-301-0/+1
| | | | | | | | | | | | set bit 21 of IB.control filed to actually enable MCBP for SRIOV v2: add flag for preemption enable bit for soc15 and use this flag instead of hardcode. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: init kiq and kcq for vega10Xiangliang Yu2017-03-301-0/+2
| | | | | | | | | | Init kiq via cpu mmio and init kcq through kiq. Signed-off-by: Xiangliang Yu <[email protected]> Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add common soc15 headersKen Wang2017-03-301-0/+285
These are used by various IP modules. Acked-by: Christian König <[email protected]> Signed-off-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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