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path: root/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
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* drm/amd/pm: add inst to dpm_set_powergating_by_smuBoyuan Zhang2024-12-101-1/+1
| | | | | | | | | | | | | | | | | | Add an instance parameter to amdgpu_dpm_set_powergating_by_smu() function, and use the instance to call set_powergating_by_smu(). v2: remove duplicated functions. remove for-loop in amdgpu_dpm_set_powergating_by_smu(), and temporarily move it to amdgpu_dpm_enable_vcn(), in order to keep the exact same logic as before, until further separation in next patch. v3: drop SI logic in amdgpu_dpm_enable_vcn(). Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: init saw registers for mmhub v1.0Zhu Lingshan2024-10-221-0/+49
| | | | | | | | | | This commits init registers in the Stand Along Walker for mmhub v1.0, to support ISP use cases. Signed-off-by: Zhu Lingshan <[email protected]> Reported-and-tested-by: Du Bin <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: apply the RV2 system aperture fix to RN/CZN as wellAlex Deucher2024-01-051-1/+3
| | | | | | | | | These chips needs the same fix. This was previously not seen on then since the AGP aperture expanded the system aperture, but this showed up again when AGP was disabled. Reviewed-and-tested-by: Jiadong Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add hub->ctx_distance in setup_vmid_configYifan Zhang2023-10-091-1/+1
| | | | | | | | | | | | add hub->ctx_distance when read CONTEXT1_CNTL, align w/ write back operation. v2: fix coding style errors reported by checkpatch.pl (Christian) Signed-off-by: Yifan Zhang <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: introduce vmhub definition for multi-partition cases (v3)Hawking Zhang2023-06-091-5/+5
| | | | | | | | | | | | | | | | | | | v1: Each partition has its own gfxhub or mmhub. adjust the num of MAX_VMHUBS and the GFXHUB/MMHUB layout (Le) v2: re-design the AMDGPU_GFXHUB/AMDGPU_MMHUB layout (Le) v3: apply the gfxhub/mmhub layout to new IPs (Hawking) v4: fix up gmc11 (Alex) v5: rebase (Alex) Signed-off-by: Le Ma <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: rename vram_scratch into mem_scratchChristian König2023-01-031-1/+1
| | | | | | | | | | | | | Rename vram_scratch into mem_scratch and allow allocating it into GTT as well. The only problem with that is that we won't have a default page for the system aperture any more. Signed-off-by: Christian König <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: mmVM_L2_CNTL3 register not initialized correctlyQu Huang2022-08-251-0/+1
| | | | | | | The mmVM_L2_CNTL3 register is not assigned an initial value Signed-off-by: Qu Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: expand cg_flags from u32 to u64Evan Quan2022-04-081-1/+1
| | | | | | | | | With this, we can support more CG flags. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Modify mmhub block to fit for the unified ras block data and opsyipechai2022-01-141-3/+7
| | | | | | | | | | | | | | | 1.Modify mmhub block to fit for the unified ras block data and ops. 2.Change amdgpu_mmhub_ras_funcs to amdgpu_mmhub_ras, and the corresponding variable name remove _funcs suffix. 3.Remove the const flag of mmhub ras variable so that mmhub ras block can be able to be inserted into amdgpu device ras block link list. 4.Invoke amdgpu_ras_register_ras_block function to register mmhub ras block into amdgpu device ras block link list. 5.Remove the redundant code about mmhub in amdgpu_ras.c after using the unified ras block. 5.Remove the redundant code about mmhub in amdgpu_ras.c after using the unified ras block. 6.Fill unified ras block .name .block .ras_late_init and .ras_fini for all of mmhub versions. If .ras_late_init and .ras_fini had been defined by the selected mmhub version, the defined functions will take effect; if not defined, default fill them with amdgpu_mmhub_ras_late_init and amdgpu_mmhub_ras_fini. Signed-off-by: yipechai <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: John Clements <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: correct the wrong cached state for GMC on PICASSOEvan Quan2021-12-141-4/+4
| | | | | | | | | | | | | Pair the operations did in GMC ->hw_init and ->hw_fini. That can help to maintain correct cached state for GMC and avoid unintention gate operation dropping due to wrong cached state. BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1828 Signed-off-by: Evan Quan <[email protected]> Acked-by: Guchun Chen <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: don't override default ECO_BITs settingHawking Zhang2021-12-131-1/+0
| | | | | | | | Leave this bit as hardware default setting Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Calling address translation functions to simplify codesOak Zeng2021-04-151-2/+1
| | | | | | | | | | Use amdgpu_gmc_vram_pa and amdgpu_gmc_vram_cpu_pa to simplify codes. No logic change. Signed-off-by: Oak Zeng <[email protected]> Signed-off-by: Harish Kasiviswanathan <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: split mmhub callbacks into ras and non-ras onesHawking Zhang2021-04-091-1/+5
| | | | | | | | | | mmhub ras is only avaiable in cerntain mmhub ip generation. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: use AMDGPU_NUM_VMID when possibleNirmoy Das2020-12-091-1/+1
| | | | | | | | Replace hardcoded vmid number with AMDGPU_NUM_VMID macro. Signed-off-by: Nirmoy Das <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: improve code indentation and alignmentDeepak R Varma2020-11-021-2/+2
| | | | | | | | | | General code indentation and alignment changes such as replace spaces by tabs or align function arguments as per the coding style guidelines. The patch covers various .c files for this driver. Issue reported by checkpatch script. Signed-off-by: Deepak R Varma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: store noretry parameter per driver instanceAlex Deucher2020-09-251-1/+1
| | | | | | | | | This will allow us to have different defaults per asic in a future patch. Reviewed-by: Christian König <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: remove unintended executable modeLukas Bulwahn2020-08-241-0/+0
| | | | | | | | | | | | | | | | | | Besides the intended change, commit 4cc1178e166a ("drm/amdgpu: replace DRM prefix with PCI device info for gfx/mmhub") also set the source files mmhub_v1_0.c and gfx_v9_4.c to be executable, i.e., changed fromold mode 644 to new mode 755. Commit 241b2ec9317e ("drm/amd/display: Add dcn30 Headers (v2)") added the four header files {dpcs,dcn}_3_0_0_{offset,sh_mask}.h as executable, i.e., mode 755. Set to the usual modes for source and headers files and clean up those mistakes. No functional change. Reviewed-by: Christian König <[email protected]> Signed-off-by: Lukas Bulwahn <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/powerplay: drop unnecessary pp_funcs checkerEvan Quan2020-08-141-2/+1
| | | | | | | | | | It's redundant. Also, the callers should not care about the implementation details. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Use function pointer for some mmhub functionsOak Zeng2020-08-141-9/+18
| | | | | | | | | | | Add more function pointers to amdgpu_mmhub_funcs. ASIC specific implementation of most mmhub functions are called from a general function pointer, instead of calling different function for different ASIC. Simplify the code by deleting duplicate functions Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: use register distance member instead of hardcode in mmhub v1Huang Rui2020-07-081-15/+24
| | | | | | | | | | This patch updates to use register distance member instead of hardcode in mmhub v1. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add register distance members into vmhub structureHuang Rui2020-07-081-0/+6
| | | | | | | | | | | This patch is to abstract register distances between two continuous context domains and invalidation engines. In different ip headers, these distances may be differences. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add apu flags (v2)Alex Deucher2020-05-221-1/+1
| | | | | | | | | | | | | Add some APU flags to simplify handling of different APU variants. It's easier to understand the special cases if we use names flags rather than checking device ids and silicon revisions. v2: rebase on latest code Acked-by: Evan Quan <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: replace DRM prefix with PCI device info for gfx/mmhubDennis Li2020-04-221-4/+8
| | | | | | | | | Prefix RAS message printing in gfx/mmhub with PCI device info, which assists the debug in multiple GPU case. Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Dennis Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add reset_ras_error_count function for MMHUBHawking Zhang2020-03-051-0/+12
| | | | | | | | | | | MMHUB ras error counters are dirty ones after cold reboot Read operation is needed to reset them to 0 Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: remove unnecessary conversion to boolNirmoy Das2020-01-221-2/+2
| | | | | | | | Better clean that up before some automation starts to complain about it Signed-off-by: Nirmoy Das <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: initialize vm_inv_eng0_sem for gfxhub and mmhubchangzhu2019-11-221-0/+2
| | | | | | | | | | | | SW must acquire/release one of the vm_invalidate_eng*_sem around the invalidation req/ack. Through this way,it can avoid losing invalidate acknowledge state across power-gating off cycle. To use vm_invalidate_eng*_sem, it needs to initialize vm_invalidate_eng*_sem firstly. Signed-off-by: changzhu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: refine query function of mmhub EDC counter in vg20Dennis Li2019-11-221-50/+178
| | | | | | | | | | | | | | | Add codes to print the detail EDC info for the subblock of mmhub v2: Move the EDC_CNT registers' defintion from mmhub_9_4 header files to mmhub_1_0 ones. Add mmhub_v1_0_ prefix for the local static variable and function. v3: squash in DC fix Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: remove duplicated include from mmhub_v1_0.cYueHaibing2019-10-071-1/+0
| | | | | | | Remove duplicated include. Signed-off-by: YueHaibing <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Disable retry faults in VMID0Felix Kuehling2019-09-161-0/+2
| | | | | | | | | There is no point retrying page faults in VMID0. Those faults are always fatal. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-and-Tested-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mmhub: switch to amdgpu_mmhub_ras_late_init helper functionHawking Zhang2019-09-131-31/+1
| | | | | | | | | | amdgpu_mmhub_ras_late_init is used to init mmhub specfic ras debugfs/sysfs node and mmhub specific interrupt handler. It can be shared among mmhub generations Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: set ip specific ras interface pointer to NULL after free itHawking Zhang2019-09-131-1/+3
| | | | | | | | to prevent access to dangling pointers Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: fix memory leak when ras is not supported on specific ip blockHawking Zhang2019-09-131-1/+1
| | | | | | | | free ras_if if ras is not supported Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add mmhub ras_late_init callback function (v2)Hawking Zhang2019-09-131-0/+30
| | | | | | | | | | | | | The function will be called in late init phase to do mmhub ras init v2: check ras_late_init function pointer before invoking the function Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mmhub1: set mmhub clock gating for rnPrike Liang2019-08-221-0/+1
| | | | | | | | setup mmhub clockgating. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: implement querying ras error count for mmhubTao Zhou2019-08-151-0/+55
| | | | | | | | get mmhub ea ras error count by accessing EDC_CNT register Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: split athub clock gating from mmhubLe Ma2019-08-121-43/+12
| | | | | | | | | Untie the bind of get/set athub CG state from mmhub, for cosmetic fix and Asic not using mmhub 1.0. Besides, also fix wrong athub CG state in amdgpu_pm_info. Signed-off-by: Le Ma <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add amdgpu_mmhub_funcs definitionTao Zhou2019-08-121-0/+9
| | | | | | | | | add amdgpu_mmhub_funcs definition and initialize it, prepare for mmhub ras enablement Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: cleanup vega10 SRIOV code pathMonk Liu2019-08-021-5/+5
| | | | | | | | | | | | | | | | | | we can simplify all those unnecessary function under SRIOV for vega10 since: 1) PSP L1 policy is by force enabled in SRIOV 2) original logic always set all flags which make itself a dummy step besides, 1) the ih_doorbell_range set should also be skipped for VEGA10 SRIOV. 2) the gfx_common registers should also be skipped for VEGA10 SRIOV. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: rename AMDGPU_GFXHUB/MMHUB macro with hub numberLe Ma2019-07-181-1/+1
| | | | | | | | The number of GFXHUB/MMHUB may be expanded in later ASICs. Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdkfd: Consistently apply noretry settingFelix Kuehling2019-07-161-1/+2
| | | | | | | | | | | | | | Apply the same setting to SH_MEM_CONFIG and VM_CONTEXT1_CNTL. This makes the noretry param no longer KFD-specific. On GFX10 I'm not changing SH_MEM_CONFIG in this commit because GFX10 has different retry behaviour in the SQ and I don't have a way to test it at the moment. Suggested-by: Christian König <[email protected]> CC: Philip Yang <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by : Shaoyun.liu < [email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Skip setting some regs under Vega10 VFTrigger Huang2019-05-241-5/+20
| | | | | | | | | | For Vega10 SR-IOV VF, skip setting some regs due to: 1, host will program them 2, avoid VF register programming violations Signed-off-by: Trigger Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Merge tag 'drm-next-2019-05-09' of git://anongit.freedesktop.org/drm/drmLinus Torvalds2019-05-091-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull drm updates from Dave Airlie: "This has two exciting community drivers for ARM Mali accelerators. Since ARM has never been open source friendly on the GPU side of the house, the community has had to create open source drivers for the Mali GPUs. Lima covers the older t4xx and panfrost the newer 6xx/7xx series. Well done to all involved and hopefully this will help ARM head in the right direction. There is also now the ability if you don't have any of the legacy drivers enabled (pre-KMS) to remove all the pre-KMS support code from the core drm, this saves 10% or so in codesize on my machine. i915 also enable Icelake/Elkhart Lake Gen11 GPUs by default, vboxvideo moves out of staging. There are also some rcar-du patches which crossover with media tree but all should be acked by Mauro. Summary: uapi changes: - Colorspace connector property - fourcc - new YUV formts - timeline sync objects initially merged - expose FB_DAMAGE_CLIPS to atomic userspace new drivers: - vboxvideo: moved out of staging - aspeed: ASPEED SoC BMC chip display support - lima: ARM Mali4xx GPU acceleration driver support - panfrost: ARM Mali6xx/7xx Midgard/Bitfrost acceleration driver support core: - component helper docs - unplugging fixes - devm device init - MIPI/DSI rate control - shmem backed gem objects - connector, display_info, edid_quirks cleanups - dma_buf fence chain support - 64-bit dma-fence seqno comparison fixes - move initial fb config code to core - gem fence array helpers for Lima - ability to remove legacy support code if no drivers requires it (removes 10% of drm.ko size) - lease fixes ttm: - unified DRM_FILE_PAGE_OFFSET handling - Account for kernel allocations in kernel zone only panel: - OSD070T1718-19TS panel support - panel-tpo-td028ttec1 backlight support - Ronbo RB070D30 MIPI/DSI - Feiyang FY07024DI26A30-D MIPI-DSI panel - Rocktech jh057n00900 MIPI-DSI panel i915: - Comet Lake (Gen9) PCI IDs - Updated Icelake PCI IDs - Elkhartlake (Gen11) support - DP MST property addtions - plane and watermark fixes - Icelake port sync and VEBOX disable fixes - struct_mutex usage reduction - Icelake gamma fix - GuC reset fixes - make mmap more asynchronous - sound display power well race fixes - DDI/MIPI-DSI clocks for Icelake - Icelake RPS frequency changing support - Icelake workarounds amdgpu: - Use HMM for userptr - vega20 experimental smu11 support - RAS support for vega20 - BACO support for vega12 + fixes for vega20 - reworked IH interrupt handling - amdkfd RAS support - Freesync improvements - initial timeline sync object support - DC Z ordering fixes - NV12 planes support - colorspace properties for planes= - eDP opts if eDP already initialized nouveau: - misc fixes etnaviv: - misc fixes msm: - GPU zap shader support expansion - robustness ABI addition exynos: - Logging cleanups tegra: - Shared reset fix - CPU cache maintenance fix cirrus: - driver rewritten using simple helpers meson: - G12A support vmwgfx: - Resource dirtying management improvements - Userspace logging improvements virtio: - PRIME fixes rockchip: - rk3066 hdmi support sun4i: - DSI burst mode support vc4: - load tracker to detect underflow v3d: - v3d v4.2 support malidp: - initial Mali D71 support in komeda driver tfp410: - omap related improvement omapdrm: - drm bridge/panel support - drop some omap specific panels rcar-du: - Display writeback support" * tag 'drm-next-2019-05-09' of git://anongit.freedesktop.org/drm/drm: (1507 commits) drm/msm/a6xx: No zap shader is not an error drm/cma-helper: Fix drm_gem_cma_free_object() drm: Fix timestamp docs for variable refresh properties. drm/komeda: Mark the local functions as static drm/komeda: Fixed warning: Function parameter or member not described drm/komeda: Expose bus_width to Komeda-CORE drm/komeda: Add sysfs attribute: core_id and config_id drm: add non-desktop quirk for Valve HMDs drm/panfrost: Show stored feature registers drm/panfrost: Don't scream about deferred probe drm/panfrost: Disable PM on probe failure drm/panfrost: Set DMA masks earlier drm/panfrost: Add sanity checks to submit IOCTL drm/etnaviv: initialize idle mask before querying the HW db drm: introduce a capability flag for syncobj timeline support drm: report consistent errors when checking syncobj capibility drm/nouveau/nouveau: forward error generated while resuming objects tree drm/nouveau/fb/ramgk104: fix spelling mistake "sucessfully" -> "successfully" drm/nouveau/i2c: Disable i2c bus access after ->fini() drm/nouveau: Remove duplicate ACPI_VIDEO_NOTIFY_PROBE definition ...
| * drm/amdgpu: re-enable retry faultsChristian König2019-03-211-1/+1
| | | | | | | | | | | | | | | | | | Now that we have re-reoute faults to the other IH ring we can enable retries again. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0Yong Zhao2019-03-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is recommended by HW designers. Previously when it was set to 1, the PDE walk error in VM fault will be treated as PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT. As a result, the retry control in VM_CONTEXT*_CNTL will change accordingly. The above behavior is kind of abnormal. Furthermore, the PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs and it never made it way to production. Therefore, we should set it to 0. Signed-off-by: Yong Zhao <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | drm/amdgpu/gmc9: fix VM_L2_CNTL3 programmingAlex Deucher2019-04-121-0/+1
|/ | | | | | | | | Got accidently dropped when 2+1 level support was added. Fixes: 6a42fd6fbf534096 ("drm/amdgpu: implement 2+1 PD support for Raven v3") Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* Merge branch 'drm-next-4.21' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2018-11-191-7/+12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next New features for 4.21: amdgpu: - Support for SDMA paging queue on vega - Put compute EOP buffers into vram for better performance - Share more code with amdkfd - Support for scanout with DCC on gfx9 - Initial kerneldoc for DC - Updated SMU firmware support for gfx8 chips - Rework CSA handling for eventual support for preemption - XGMI PSP support - Clean up RLC handling - Enable GPU reset by default on VI, SOC15 dGPUs - Ring and IB test cleanups amdkfd: - Share more code with amdgpu ttm: - Move global init out of the drivers scheduler: - Track if schedulers are ready for work - Timeout/fault handling changes to facilitate GPU recovery Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
| * drm/amdgpu: Expose *_setup_vm_pt_regs for kfd to useYong Zhao2018-11-051-7/+12
| | | | | | | | | | | | | | | | | | | | | | kfd has the same need to set the VM page table base register, so expose them for kfd to use for better maintainability. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | drm/amdgpu: set system aperture to cover whole FB regionshaoyunl2018-11-121-3/+3
|/ | | | | | | | | | In XGMI configuration, the FB region covers vram region from peer device, adjust system aperture to cover all of them Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: shaoyunl <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Fix null point errorRex Zhu2018-10-251-1/+1
| | | | | | | | | | need to check adev->powerplay.pp_funcs first, becasue from AI, the smu ip can be disabled by user, and the pp_handle is null in this case. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: fix the page fault of raven2Huang Rui2018-09-271-1/+2
| | | | | | | | | | | | | | | | While the apg_end address is 0xffffffff, if add 1 with it, the value will be overflow and roll back to 0. So when 0 is written to mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, the system aperture is actually disabled. And so any access to vram will trigger a page fault. Raven2's HW issue only need increase the vram end address, and needn't do it on the agp. Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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