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path: root/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
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* drm/amdgpu/mes: add compatibility checks for set_hw_resource_1Alex Deucher2025-06-241-1/+2
| | | | | | | | | | | | | | | Seems some older MES firmware versions do not properly support this packet. Add back some the compatibility checks. v2: switch to fw version check (Shaoyun) Fixes: f81cd793119e ("drm/amd/amdgpu: Fix MES init sequence") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4295 Cc: Shaoyun Liu <[email protected]> Reviewed-by: shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]> (cherry picked from commit 0180e0a5dd5c6ff118043ee42dbbbddaf881f283) Cc: [email protected]
* drm/amdgpu/mes: use correct MES pipe for resetsAlex Deucher2025-04-301-1/+1
| | | | | | | | | | | Use the KIQ pipe for kernel queues and the SCHED pipe for user queues. Fixes: 2408b0272b04 ("drm/amdgpu/mes: consolidate on a single mes reset callback") Cc: Michael Chen <[email protected]> Cc: Shaoyun Liu <[email protected]> Reviewed-by: Michael Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes: consolidate on a single mes reset callbackAlex Deucher2025-04-301-4/+4
| | | | | | | | Use the legacy one as it covers both kernel queues and user queues. Reviewed-by: Sunil Khatri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes: remove more unused functionsAlex Deucher2025-04-301-27/+0
| | | | | | | These were leftover from mes bring up and are unused. Reviewed-by: Sunil Khatri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Fix API status offset for MES queue resetJesse.Zhang2025-04-301-1/+1
| | | | | | | | | | | | | | | The mes_v11_0_reset_hw_queue and mes_v12_0_reset_hw_queue functions were using the wrong union type (MESAPI__REMOVE_QUEUE) when getting the offset for api_status. Since these functions handle queue reset operations, they should use MESAPI__RESET union instead. This fixes the polling of API status during hardware queue reset operations in the MES for both v11 and v12 versions. Signed-off-by: Jesse Zhang <[email protected]> Reviewed-By: Shaoyun.liu <[email protected]> Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: add conversion for priority levelsAlex Deucher2025-04-211-2/+19
| | | | | | | | | | Convert driver priority levels to MES11 priority levels. At the moment they are the same, but they may not always be. Reviewed-by: Sunil Khatri <[email protected]> Reviewed-by: Jesse.Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: adjust enforce_isolation handlingAlex Deucher2025-04-111-1/+1
| | | | | | | | | | | | Switch from a bool to an enum and allow more options for enforce isolation. There are now 3 modes of operation: - Disabled (0) - Enabled (serialization and cleaner shader) (1) - Enabled in legacy mode (no serialization or cleaner shader) (2) This provides better flexibility for more use cases. Acked-by: Srinivasan Shanmugam <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: use the device value for enforce isolationAlex Deucher2025-04-111-1/+1
| | | | | | | Use the local setting rather than the global parameter. Acked-by: Srinivasan Shanmugam <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes: centralize gfx_hqd mask managementAlex Deucher2025-04-081-12/+3
| | | | | | | | | | | | Move it to amdgpu_mes to align with the compute and sdma hqd masks. No functional change. v2: rebase on new changes v3: misc optimizations Reviewed-by: Prike Liang <[email protected]> Reviewed-by: Sunil Khatri<[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Remove the MES self testArunpravin Paneer Selvam2025-04-081-12/+1
| | | | | | | | | | | | Remove MES self test as this conflicts the userqueue fence interrupts. v2:(Christian) - remove the amdgpu_mes_self_test() function and any now unused code. Signed-off-by: Arunpravin Paneer Selvam <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: fix MES GFX maskArvind Yadav2025-04-081-3/+12
| | | | | | | | | | | | | | | | | Current MES GFX mask prevents FW to enable oversubscription. This patch does the following: - Fixes the mask values and adds a description for the same - Removes the central mask setup and makes it IP specific, as it would be different when the number of pipes and queues are different. v2: squash in fix from Shashank Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Shashank Sharma <[email protected]> Signed-off-by: Arvind Yadav <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: optimize MES pipe FW version fetchingAlex Deucher2025-04-081-9/+12
| | | | | | | | | | Don't fetch it again if we already have it. It seems the registers don't reliably have the value at resume in some cases. Fixes: 785f0f9fe742 ("drm/amdgpu: Add mes v12_0 ip block support (v4)") Reviewed-by: Shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/amdgpu: Fix MES init sequenceShaoyun Liu2025-03-141-23/+20
| | | | | | | | | | When MES is been used , the set_hw_resource_1 API is required to initialize MES internal context correctly Signed-off-by: Shaoyun Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Srinivasan Shanmugam <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: drop amdgpu_mes_suspend()/amdgpu_mes_resume() callsAlex Deucher2025-02-271-13/+1
| | | | | | | | | | They are noops on GFX12. There is no suspend/resume all support in firmware so the function doesn't do anything. KFD already handles its own queues and they should already be unmapped at this point so even if this runs, it's not doing anything. Reviewed-by: Shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes: keep enforce isolation up to dateAlex Deucher2025-02-251-0/+4
| | | | | | | | | | | | Re-send the mes message on resume to make sure the mes state is up to date. Fixes: 8521e3c5f058 ("drm/amd/amdgpu: limit single process inside MES") Acked-by: Srinivasan Shanmugam <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: Shaoyun Liu <[email protected]> Cc: Srinivasan Shanmugam <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: correct the name of mes_pipe structureLikun Gao2025-02-251-7/+7
| | | | | | | | Correct the structure name admgpu_mes_pipe to amdgpu_mes_pipe. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Mukul Joshi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: allocate hw_resource_1 buffer onceAlex Deucher2025-02-171-20/+17
| | | | | | | | Allocate the buffer at sw init time so we don't alloc and free it for every suspend/resume or reset cycle. Reviewed-by: Shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes: Add cleaner shader fence address handling in MES for GFX12Alex Deucher2025-02-131-0/+22
| | | | | | | | | | | | | | | | | | | | | | This commit introduces enhancements to the handling of the cleaner shader fence in the AMDGPU MES driver: - The MES (Microcode Execution Scheduler) now sends a PM4 packet to the KIQ (Kernel Interface Queue) to request the cleaner shader, ensuring that requests are handled in a controlled manner and avoiding the race conditions. - The CP (Compute Processor) firmware has been updated to use a private bus for accessing specific registers, avoiding unnecessary operations that could lead to issues in VF (Virtual Function) mode. - The cleaner shader fence memory address is now set correctly in the `mes_set_hw_res_pkt` structure, allowing for proper synchronization of the cleaner shader execution. Cc: Christian König <[email protected]> Cc: Srinivasan Shanmugam <[email protected]> Suggested-by: Shaoyun Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/amdgpu: Enable scratch data dump for mes 12Shaoyun Liu2025-01-241-13/+36
| | | | | | | | | | MES internal will check CP_MES_MSCRATCH_LO/HI register to set scratch data location during ucode start, driver side need to start the MES one by one with different setting for each pipe Signed-off-by: Shaoyun Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: Implement reset gfx/compute queue function by mmio[email protected]2024-12-111-1/+87
| | | | | | | | Reset gfx/compute queue through mmio based on me_id and queue_id. Signed-off-by: Jesse Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: Implement reset sdmav7 queue function by mmio[email protected]2024-12-111-0/+46
| | | | | | | | Reset sdma queue through mmio based on me_id and queue_id. Signed-off-by: Jesse Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: reduce the mmio writes in kiq settingPrike Liang2024-12-101-3/+1
| | | | | | | | | | There's no need to perform the two MMIO writes in the KIQ Setting registers programmed period, and reducing the MMIO writes will save the driver loading time. Signed-off-by: Prike Liang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/amdgpu: limit single process inside MESShaoyun Liu2024-11-121-0/+11
| | | | | | | | This is for MES to limit only one process for the user queues Signed-off-by: Shaoyun Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: correct kiq unmap latencyJack Xiao2024-11-111-1/+1
| | | | | | | | Correct kiq unmap queue timeout value. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes: fix issue of writing to the same log buffer from 2 MES pipesMichael Chen2024-10-151-2/+2
| | | | | | | | | With Unified MES enabled in gfx12, need separate event log buffer for the 2 MES pipes to avoid data overwrite. Signed-off-by: Michael Chen <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: update the handle ptr in hw_finiSunil Khatri2024-10-071-13/+12
| | | | | | | | | | | | | Update the *handle to amdgpu_ip_block ptr for all functions pointers of hw_fini. Also update the ip_block ptr where ever needed as there were cyclic dependency of hw_fini on suspend and some followed clean up. Signed-off-by: Sunil Khatri <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: update the handle ptr in hw_initSunil Khatri2024-10-071-7/+13
| | | | | | | | | | | | | | Update the *handle to amdgpu_ip_block ptr for all functions pointers of hw_init. Also update the ip_block ptr where ever needed as there were cyclic dependency of hw_init on resume. v2: squash in isp fix Signed-off-by: Sunil Khatri <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: update the handle ptr in resumeSunil Khatri2024-10-071-2/+2
| | | | | | | | | Update the *handle to amdgpu_ip_block ptr for all functions pointers of resume. Signed-off-by: Sunil Khatri <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: update the handle ptr in suspendSunil Khatri2024-10-071-2/+2
| | | | | | | | | Update the *handle to amdgpu_ip_block ptr for all functions pointers of suspend. Signed-off-by: Sunil Khatri <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: update the handle ptr in sw_finiSunil Khatri2024-10-011-2/+2
| | | | | | | | | update the *handle to amdgpu_ip_block ptr for all functions pointers of sw_fini. Signed-off-by: Sunil Khatri <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: update the handle ptr in sw_initSunil Khatri2024-10-011-2/+2
| | | | | | | | | update the *handle to amdgpu_ip_block ptr for all functions pointers of sw_init. Signed-off-by: Sunil Khatri <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: update the handle ptr in late_initSunil Khatri2024-10-011-2/+2
| | | | | | | | | Update the ptr handle to amdgpu_ip_block ptr in all the functions of late_init function ptr. Signed-off-by: Sunil Khatri <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: update the handle ptr in early_initSunil Khatri2024-10-011-2/+2
| | | | | | | | | update the handle ptr to amdgpu_ip_block ptr for all functions pointers on early_init. Signed-off-by: Sunil Khatri <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: set enable_level_process_quantum_checkJack Xiao2024-09-251-0/+1
| | | | | | | | | | enable_level_process_quantum_check is requried to enable process quantum based scheduling. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.11.x
* drm/amdgpu/mes12: reduce timeoutAlex Deucher2024-09-181-1/+1
| | | | | | | | | | The firmware timeout is 2s. Reduce the driver timeout to 2.1 seconds to avoid back pressure on queue submissions. Fixes: 94b51a3d01ed ("drm/amdgpu/mes12: increase mes submission timeout") Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.11.x
* drm/amdgpu/mes12: switch SET_SHADER_DEBUGGER pkt to mes schq pipeJack Xiao2024-09-181-5/+6
| | | | | | | | | | The SET_SHADER_DEBUGGER packet must work with the added hardware queue, switch the packet submitting to mes schq pipe. Signed-off-by: Jack Xiao <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.11.x
* drm/amdgpu/mes: add mes mapping legacy queue switchJack Xiao2024-08-291-3/+6
| | | | | | | | | | | | For mes11 old firmware has issue to map legacy queue, add a flag to switch mes to map legacy queue. Fixes: f9d8c5c7855d ("drm/amdgpu/gfx: enable mes to map legacy queue support") Reported-by: Andrew Worsley <[email protected]> Link: https://lists.freedesktop.org/archives/amd-gfx/2024-August/112773.html Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: add API for user queue resetAlex Deucher2024-08-161-0/+27
| | | | | | | Add API for resetting user queues. Acked-by: Vitaly Prosyak <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: sw/hw fini for unified mesJack Xiao2024-08-131-11/+20
| | | | | | | | | Free memory for two pipes and unmap pipe0 via pipe1. Signed-off-by: Jack Xiao <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: configure two pipes hardware resourcesJack Xiao2024-08-131-20/+23
| | | | | | | | | Configure two pipes with different hardware resources. Signed-off-by: Jack Xiao <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: adjust mes12 sw/hw init for multiple pipesJack Xiao2024-08-131-46/+69
| | | | | | | | | | | Adjust mes12 sw/hw initiailization for both pipe0 and pipe1 enablement. The two pipes are almost identical pipe. Pipe0 behaves like schq and pipe1 like kiq, pipe0 was mapped by pipe1. Signed-off-by: Jack Xiao <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: add mes pipe switch supportJack Xiao2024-08-131-26/+34
| | | | | | | | | | Add mes pipe switch to let caller choose pipe to submit packet. Signed-off-by: Jack Xiao <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: load unified mes fw on pipe0 and pipe1Jack Xiao2024-08-131-24/+3
| | | | | | | | | Enable unified mes firmware to load on pipe0 and pipe1. Signed-off-by: Jack Xiao <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes: add multiple mes ring instances supportJack Xiao2024-08-131-17/+17
| | | | | | | | | | Add multiple mes ring instances in mes structure to support multiple mes pipes. Signed-off-by: Jack Xiao <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: add API for legacy queue resetAlex Deucher2024-08-131-0/+33
| | | | | | | Add API for resetting kernel queues. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes: fix mes ring buffer overflowJack Xiao2024-08-131-4/+14
| | | | | | | | | | | | | wait memory room until enough before writing mes packets to avoid ring buffer overflow. v2: squash in sched_hw_submission fix Fixes: de3246254156 ("drm/amdgpu: cleanup MES11 command submission") Fixes: fffe347e1478 ("drm/amdgpu: cleanup MES12 command submission") Signed-off-by: Jack Xiao <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: increase mes log buffer size for gfx12Michael Chen2024-07-271-2/+6
| | | | | | | | | MES firmware requires larger log buffer for gfx12. Allocate proper buffer respectively for gfx11 and gfx12. Signed-off-by: Michael Chen <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: add missing opcode stringAlex Deucher2024-07-121-0/+1
| | | | | | | Fixes the indexing of the string array. Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: cleanup MES12 command submissionAlex Deucher2024-06-191-28/+48
| | | | | | | | | | | | | | | | The approach of having a separate WB slot for each submission doesn't really work well and for example breaks GPU reset. Use a status query packet for the fence update instead since those should always succeed we can use the fence of the original packet to signal the state of the operation. While at it cleanup the coding style. Fixes: ade887c63394 ("drm/amdgpu/mes12: Use a separate fence per transaction") Reviewed-by: Mukul Joshi <[email protected]> Suggested-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/mes12: mes hw_fini fix for mode1 resetJack Xiao2024-05-231-3/+4
| | | | | | | | Port mes11 hw_fini to mes12, fix for mode1 reset. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
generated by cgit (git 2.51.2) at 2025-11-30 20:31:21 +0000