| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | ACPI: RISC-V: Fix FFH_CPPC_CSR error handling | Anup Patel | 2025-09-04 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | The cppc_ffh_csr_read() and cppc_ffh_csr_write() returns Linux error code in "data->ret.error" so cpc_read_ffh() and cpc_write_ffh() must not use sbi_err_map_linux_errno() for FFH_CPPC_CSR. Fixes: 30f3ffbee86b ("ACPI: RISC-V: Add CPPC driver") Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Andrew Jones <[email protected]> Reviewed-by: Troy Mitchell <[email protected]> Reviewed-by: Sunil V L <[email protected]> Reviewed-by: Nutty Liu <[email protected]> Reviewed-by: Atish Patra <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Paul Walmsley <[email protected]> | ||||
| * | ACPI: RISC-V: Remove unnecessary CPPC debug message | Sunil V L | 2025-07-16 | 1 | -2/+0 |
| | | | | | | | | | | | | | | | The presence or absence of the CPPC SBI extension is currently logged on every boot. This message is not particularly useful and can clutter the boot log. Remove this debug message to reduce noise during boot. This change has no functional impact. Signed-off-by: Sunil V L <[email protected]> Reviewed-by: Anup Patel <[email protected]> Tested-by: Drew Fustini <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]> | ||||
| * | ACPI: RISC-V: Add CPPC driver | Sunil V L | 2024-03-20 | 1 | -0/+157 |
| Add cpufreq driver based on ACPI CPPC for RISC-V. The driver uses either SBI CPPC interfaces or the CSRs to access the CPPC registers as defined by the RISC-V FFH spec. Signed-off-by: Sunil V L <[email protected]> Reviewed-by: Pierre Gondois <[email protected]> Acked-by: Rafael J. Wysocki <[email protected]> Acked-by: Sudeep Holla <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]> | |||||
