diff options
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/Kconfig | 14 | ||||
| -rw-r--r-- | drivers/clk/Makefile | 3 | ||||
| -rw-r--r-- | drivers/clk/bcm/clk-bcm2835.c | 210 | ||||
| -rw-r--r-- | drivers/clk/clk-hifiberry-dachd.c | 331 | ||||
| -rw-r--r-- | drivers/clk/clk-hifiberry-dacpro.c | 180 | ||||
| -rw-r--r-- | drivers/clk/clk-rp1-sdio.c | 599 | ||||
| -rw-r--r-- | drivers/clk/clk-rp1.c | 1697 |
7 files changed, 2002 insertions, 1032 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 3a1611008e48..cc95f10ed01b 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -89,13 +89,19 @@ config COMMON_CLK_RK808 config COMMON_CLK_RP1 tristate "Raspberry Pi RP1-based clock support" - depends on MISC_RP1 || COMPILE_TEST + depends on MISC_RP1 || MFD_RP1 || COMPILE_TEST default MISC_RP1 help Enable common clock framework support for Raspberry Pi RP1. This multi-function device has 3 main PLLs and several clock generators to drive the internal sub-peripherals. +config COMMON_CLK_RP1_SDIO + tristate "Clock driver for the RP1 SDIO interfaces" + depends on MFD_RP1 + help + SDIO clock driver for the RP1 support chip + config COMMON_CLK_HI655X tristate "Clock driver for Hi655x" if EXPERT depends on (MFD_HI655X_PMIC || COMPILE_TEST) @@ -106,6 +112,12 @@ config COMMON_CLK_HI655X multi-function device has one fixed-rate oscillator, clocked at 32KHz. +config COMMON_CLK_HIFIBERRY_DACPLUSHD + tristate + +config COMMON_CLK_HIFIBERRY_DACPRO + tristate + config COMMON_CLK_SCMI tristate "Clock driver controlled via SCMI interface" depends on ARM_SCMI_PROTOCOL || COMPILE_TEST diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index b74a1767ca27..2c81320a0ad0 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -72,6 +72,8 @@ obj-$(CONFIG_COMMON_CLK_LAN966X) += clk-lan966x.o obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o obj-$(CONFIG_MACH_LOONGSON32) += clk-loongson1.o obj-$(CONFIG_COMMON_CLK_LOONGSON2) += clk-loongson2.o +obj-$(CONFIG_COMMON_CLK_HIFIBERRY_DACPRO) += clk-hifiberry-dacpro.o +obj-$(CONFIG_COMMON_CLK_HIFIBERRY_DACPLUSHD) += clk-hifiberry-dachd.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o obj-$(CONFIG_ARCH_MILBEAUT_M10V) += clk-milbeaut.o @@ -86,6 +88,7 @@ obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o obj-$(CONFIG_COMMON_CLK_RP1) += clk-rp1.o +obj-$(CONFIG_COMMON_CLK_RP1_SDIO) += clk-rp1-sdio.o obj-$(CONFIG_COMMON_CLK_RPMI) += clk-rpmi.o obj-$(CONFIG_COMMON_CLK_HI655X) += clk-hi655x.o obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 02215ea79403..9ba61a9d9890 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -36,6 +36,7 @@ #include <linux/platform_device.h> #include <linux/slab.h> #include <dt-bindings/clock/bcm2835.h> +#include <soc/bcm2835/raspberrypi-firmware.h> #define CM_PASSWORD 0x5a000000 @@ -106,6 +107,7 @@ #define CM_UARTDIV 0x0f4 #define CM_VECCTL 0x0f8 #define CM_VECDIV 0x0fc +#define CM_DSI0HSCK 0x120 #define CM_PULSECTL 0x190 #define CM_PULSEDIV 0x194 #define CM_SDCCTL 0x1a8 @@ -296,6 +298,8 @@ #define SOC_BCM2711 BIT(1) #define SOC_ALL (SOC_BCM2835 | SOC_BCM2711) +#define VCMSG_ID_CORE_CLOCK 4 + /* * Names of clocks used within the driver that need to be replaced * with an external parent's name. This array is in the order that @@ -314,6 +318,7 @@ static const char *const cprman_parent_names[] = { struct bcm2835_cprman { struct device *dev; void __iomem *regs; + struct rpi_firmware *fw; spinlock_t regs_lock; /* spinlock for all clocks */ unsigned int soc; @@ -648,15 +653,17 @@ static int bcm2835_pll_on(struct clk_hw *hw) spin_unlock(&cprman->regs_lock); /* Wait for the PLL to lock. */ - timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); - while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { - if (ktime_after(ktime_get(), timeout)) { - dev_err(cprman->dev, "%s: couldn't lock PLL\n", - clk_hw_get_name(hw)); - return -ETIMEDOUT; - } + if (strcmp(data->name, "pllh")) { + timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); + while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { + if (ktime_after(ktime_get(), timeout)) { + dev_err(cprman->dev, "%s: couldn't lock PLL\n", + clk_hw_get_name(hw)); + return -ETIMEDOUT; + } - cpu_relax(); + cpu_relax(); + } } cprman_write(cprman, data->a2w_ctrl_reg, @@ -1044,6 +1051,30 @@ static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, return rate; } +static unsigned long bcm2835_clock_get_rate_vpu(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); + struct bcm2835_cprman *cprman = clock->cprman; + + if (cprman->fw) { + struct { + u32 id; + u32 val; + } packet; + + packet.id = VCMSG_ID_CORE_CLOCK; + packet.val = 0; + + if (!rpi_firmware_property(cprman->fw, + RPI_FIRMWARE_GET_MAX_CLOCK_RATE, + &packet, sizeof(packet))) + return packet.val; + } + + return bcm2835_clock_get_rate(hw, parent_rate); +} + static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) { struct bcm2835_cprman *cprman = clock->cprman; @@ -1102,8 +1133,10 @@ static int bcm2835_clock_on(struct clk_hw *hw) return 0; } -static int bcm2835_clock_set_rate(struct clk_hw *hw, - unsigned long rate, unsigned long parent_rate) +static int bcm2835_clock_set_rate_and_parent(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate, + u8 parent) { struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct bcm2835_cprman *cprman = clock->cprman; @@ -1113,15 +1146,24 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw, spin_lock(&cprman->regs_lock); - /* - * Setting up frac support - * - * In principle it is recommended to stop/start the clock first, - * but as we set CLK_SET_RATE_GATE during registration of the - * clock this requirement should be take care of by the - * clk-framework. + ctl = cprman_read(cprman, data->ctl_reg); + + /* If the clock is running, we have to pause clock generation while + * updating the control and div regs. This is glitchless (no clock + * signals generated faster than the rate) but each reg access is two + * OSC cycles so the clock will slow down for a moment. */ - ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; + if (ctl & CM_ENABLE) { + cprman_write(cprman, data->ctl_reg, ctl & ~CM_ENABLE); + bcm2835_clock_wait_busy(clock); + } + + if (parent != 0xff) { + ctl &= ~(CM_SRC_MASK << CM_SRC_SHIFT); + ctl |= parent << CM_SRC_SHIFT; + } + + ctl &= ~CM_FRAC; ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; cprman_write(cprman, data->ctl_reg, ctl); @@ -1132,6 +1174,12 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw, return 0; } +static int bcm2835_clock_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + return bcm2835_clock_set_rate_and_parent(hw, rate, parent_rate, 0xff); +} + static bool bcm2835_clk_is_pllc(struct clk_hw *hw) { @@ -1315,6 +1363,7 @@ static const struct clk_ops bcm2835_clock_clk_ops = { .unprepare = bcm2835_clock_off, .recalc_rate = bcm2835_clock_get_rate, .set_rate = bcm2835_clock_set_rate, + .set_rate_and_parent = bcm2835_clock_set_rate_and_parent, .determine_rate = bcm2835_clock_determine_rate, .set_parent = bcm2835_clock_set_parent, .get_parent = bcm2835_clock_get_parent, @@ -1332,7 +1381,7 @@ static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) */ static const struct clk_ops bcm2835_vpu_clock_clk_ops = { .is_prepared = bcm2835_vpu_clock_is_on, - .recalc_rate = bcm2835_clock_get_rate, + .recalc_rate = bcm2835_clock_get_rate_vpu, .set_rate = bcm2835_clock_set_rate, .determine_rate = bcm2835_clock_determine_rate, .set_parent = bcm2835_clock_set_parent, @@ -1340,6 +1389,8 @@ static const struct clk_ops bcm2835_vpu_clock_clk_ops = { .debug_init = bcm2835_clock_debug_init, }; +static bool bcm2835_clk_is_claimed(const char *name); + static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, const void *data) { @@ -1357,6 +1408,9 @@ static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, init.ops = &bcm2835_pll_clk_ops; init.flags = pll_data->flags | CLK_IGNORE_UNUSED; + if (!bcm2835_clk_is_claimed(pll_data->name)) + init.flags |= CLK_IS_CRITICAL; + pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) return NULL; @@ -1412,6 +1466,13 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, divider->div.hw.init = &init; divider->div.table = NULL; + if (!(cprman_read(cprman, divider_data->cm_reg) & divider_data->hold_mask)) { + if (!bcm2835_clk_is_claimed(divider_data->source_pll)) + init.flags |= CLK_IS_CRITICAL; + if (!bcm2835_clk_is_claimed(divider_data->name)) + divider->div.flags |= CLK_IS_CRITICAL; + } + divider->cprman = cprman; divider->data = divider_data; @@ -1466,6 +1527,15 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, init.flags = clock_data->flags | CLK_IGNORE_UNUSED; /* + * Some GPIO clocks for ethernet/wifi PLLs are marked as + * critical (since some platforms use them), but if the + * firmware didn't have them turned on then they clearly + * aren't actually critical. + */ + if ((cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE) == 0) + init.flags &= ~CLK_IS_CRITICAL; + + /* * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate * rate changes on at least of the parents. */ @@ -1476,7 +1546,6 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, init.ops = &bcm2835_vpu_clock_clk_ops; } else { init.ops = &bcm2835_clock_clk_ops; - init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; /* If the clock wasn't actually enabled at boot, it's not * critical. @@ -1701,16 +1770,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .hold_mask = CM_PLLA_HOLDCORE, .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), - [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( - SOC_ALL, - .name = "plla_per", - .source_pll = "plla", - .cm_reg = CM_PLLA, - .a2w_reg = A2W_PLLA_PER, - .load_mask = CM_PLLA_LOADPER, - .hold_mask = CM_PLLA_HOLDPER, - .fixed_divider = 1, - .flags = CLK_SET_RATE_PARENT), + + /* + * PLLA_PER is used for gpu clocks. Controlled by firmware, see + * clk-raspberrypi.c. + */ + [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( SOC_ALL, .name = "plla_dsi0", @@ -2011,14 +2076,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .int_bits = 6, .frac_bits = 0, .tcnt_mux = 3), - [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK( - SOC_ALL, - .name = "v3d", - .ctl_reg = CM_V3DCTL, - .div_reg = CM_V3DDIV, - .int_bits = 4, - .frac_bits = 8, - .tcnt_mux = 4), + + /* + * CLOCK_V3D is used for v3d clock. Controlled by firmware, see + * clk-raspberrypi.c. + */ + /* * VPU clock. This doesn't have an enable bit, since it drives * the bus for everything else, and is special so it doesn't need @@ -2181,21 +2244,6 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .tcnt_mux = 28, .round_up = true), - /* TV encoder clock. Only operating frequency is 108Mhz. */ - [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( - SOC_ALL, - .name = "vec", - .ctl_reg = CM_VECCTL, - .div_reg = CM_VECDIV, - .int_bits = 4, - .frac_bits = 0, - /* - * Allow rate change propagation only on PLLH_AUX which is - * assigned index 7 in the parent array. - */ - .set_rate_parent = BIT(7), - .tcnt_mux = 29), - /* dsi clocks */ [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( SOC_ALL, @@ -2245,6 +2293,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_PERIICTL), }; +static bool bcm2835_clk_claimed[ARRAY_SIZE(clk_desc_array)]; + /* * Permanently take a reference on the parent of the SDRAM clock. * @@ -2264,6 +2314,21 @@ static int bcm2835_mark_sdc_parent_critical(struct clk *sdc) return clk_prepare_enable(parent); } +static bool bcm2835_clk_is_claimed(const char *name) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(clk_desc_array); i++) { + if (clk_desc_array[i].data) { + const char *clk_name = *(const char **)(clk_desc_array[i].data); + if (!strcmp(name, clk_name)) + return bcm2835_clk_claimed[i]; + } + } + + return false; +} + static int bcm2835_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -2272,7 +2337,9 @@ static int bcm2835_clk_probe(struct platform_device *pdev) const struct bcm2835_clk_desc *desc; const size_t asize = ARRAY_SIZE(clk_desc_array); const struct cprman_plat_data *pdata; + struct device_node *fw_node; size_t i; + u32 clk_id; int ret; pdata = of_device_get_match_data(&pdev->dev); @@ -2291,6 +2358,24 @@ static int bcm2835_clk_probe(struct platform_device *pdev) if (IS_ERR(cprman->regs)) return PTR_ERR(cprman->regs); + /* Mux DSI0 clock to PLLD */ + cprman_write(cprman, CM_DSI0HSCK, 1); + + fw_node = of_parse_phandle(dev->of_node, "firmware", 0); + if (fw_node) { + struct rpi_firmware *fw = rpi_firmware_get(fw_node); + if (!fw) + return -EPROBE_DEFER; + cprman->fw = fw; + } + + memset(bcm2835_clk_claimed, 0, sizeof(bcm2835_clk_claimed)); + for (i = 0; + !of_property_read_u32_index(pdev->dev.of_node, "claim-clocks", + i, &clk_id); + i++) + bcm2835_clk_claimed[clk_id]= true; + memcpy(cprman->real_parent_names, cprman_parent_names, sizeof(cprman_parent_names)); of_clk_parent_fill(dev->of_node, cprman->real_parent_names, @@ -2324,8 +2409,15 @@ static int bcm2835_clk_probe(struct platform_device *pdev) if (ret) return ret; - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, &cprman->onecell); + if (ret) + return ret; + + /* note that we have registered all the clocks */ + dev_dbg(dev, "registered %zd clocks\n", asize); + + return 0; } static const struct cprman_plat_data cprman_bcm2835_plat_data = { @@ -2351,7 +2443,15 @@ static struct platform_driver bcm2835_clk_driver = { .probe = bcm2835_clk_probe, }; -builtin_platform_driver(bcm2835_clk_driver); +static int __init __bcm2835_clk_driver_init(void) +{ + return platform_driver_register(&bcm2835_clk_driver); +} +#ifdef CONFIG_IMA +subsys_initcall(__bcm2835_clk_driver_init); +#else +postcore_initcall(__bcm2835_clk_driver_init); +#endif MODULE_AUTHOR("Eric Anholt <[email protected]>"); MODULE_DESCRIPTION("BCM2835 clock driver"); diff --git a/drivers/clk/clk-hifiberry-dachd.c b/drivers/clk/clk-hifiberry-dachd.c new file mode 100644 index 000000000000..5280b5100559 --- /dev/null +++ b/drivers/clk/clk-hifiberry-dachd.c @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock Driver for HiFiBerry DAC+ HD + * + * Author: Joerg Schambacher, i2Audio GmbH for HiFiBerry + * Copyright 2020 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/clk.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/slab.h> +#include <linux/platform_device.h> +#include <linux/i2c.h> +#include <linux/regmap.h> + +#define NO_PLL_RESET 0 +#define PLL_RESET 1 +#define HIFIBERRY_PLL_MAX_REGISTER 256 +#define DEFAULT_RATE 44100 + +static struct reg_default hifiberry_pll_reg_defaults[] = { + {0x02, 0x53}, {0x03, 0x00}, {0x07, 0x20}, {0x0F, 0x00}, + {0x10, 0x0D}, {0x11, 0x1D}, {0x12, 0x0D}, {0x13, 0x8C}, + {0x14, 0x8C}, {0x15, 0x8C}, {0x16, 0x8C}, {0x17, 0x8C}, + {0x18, 0x2A}, {0x1C, 0x00}, {0x1D, 0x0F}, {0x1F, 0x00}, + {0x2A, 0x00}, {0x2C, 0x00}, {0x2F, 0x00}, {0x30, 0x00}, + {0x31, 0x00}, {0x32, 0x00}, {0x34, 0x00}, {0x37, 0x00}, + {0x38, 0x00}, {0x39, 0x00}, {0x3A, 0x00}, {0x3B, 0x01}, + {0x3E, 0x00}, {0x3F, 0x00}, {0x40, 0x00}, {0x41, 0x00}, + {0x5A, 0x00}, {0x5B, 0x00}, {0x95, 0x00}, {0x96, 0x00}, + {0x97, 0x00}, {0x98, 0x00}, {0x99, 0x00}, {0x9A, 0x00}, + {0x9B, 0x00}, {0xA2, 0x00}, {0xA3, 0x00}, {0xA4, 0x00}, + {0xB7, 0x92}, + {0x1A, 0x3D}, {0x1B, 0x09}, {0x1E, 0xF3}, {0x20, 0x13}, + {0x21, 0x75}, {0x2B, 0x04}, {0x2D, 0x11}, {0x2E, 0xE0}, + {0x3D, 0x7A}, + {0x35, 0x9D}, {0x36, 0x00}, {0x3C, 0x42}, + { 177, 0xAC}, +}; +static struct reg_default common_pll_regs[HIFIBERRY_PLL_MAX_REGISTER]; +static int num_common_pll_regs; +static struct reg_default dedicated_192k_pll_regs[HIFIBERRY_PLL_MAX_REGISTER]; +static int num_dedicated_192k_pll_regs; +static struct reg_default dedicated_96k_pll_regs[HIFIBERRY_PLL_MAX_REGISTER]; +static int num_dedicated_96k_pll_regs; +static struct reg_default dedicated_48k_pll_regs[HIFIBERRY_PLL_MAX_REGISTER]; +static int num_dedicated_48k_pll_regs; +static struct reg_default dedicated_176k4_pll_regs[HIFIBERRY_PLL_MAX_REGISTER]; +static int num_dedicated_176k4_pll_regs; +static struct reg_default dedicated_88k2_pll_regs[HIFIBERRY_PLL_MAX_REGISTER]; +static int num_dedicated_88k2_pll_regs; +static struct reg_default dedicated_44k1_pll_regs[HIFIBERRY_PLL_MAX_REGISTER]; +static int num_dedicated_44k1_pll_regs; + +/** + * struct clk_hifiberry_drvdata - Common struct to the HiFiBerry DAC HD Clk + * @hw: clk_hw for the common clk framework + */ +struct clk_hifiberry_drvdata { + struct regmap *regmap; + struct clk *clk; + struct clk_hw hw; + unsigned long rate; +}; + +#define to_hifiberry_clk(_hw) \ + container_of(_hw, struct clk_hifiberry_drvdata, hw) + +static int clk_hifiberry_dachd_write_pll_regs(struct regmap *regmap, + struct reg_default *regs, + int num, int do_pll_reset) +{ + int i; + int ret = 0; + char pll_soft_reset[] = { 177, 0xAC, }; + + for (i = 0; i < num; i++) { + ret |= regmap_write(regmap, regs[i].reg, regs[i].def); + if (ret) + return ret; + } + if (do_pll_reset) { + ret |= regmap_write(regmap, pll_soft_reset[0], + pll_soft_reset[1]); + mdelay(10); + } + return ret; +} + +static unsigned long clk_hifiberry_dachd_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return to_hifiberry_clk(hw)->rate; +} + +static long clk_hifiberry_dachd_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + return rate; +} + +static int clk_hifiberry_dachd_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + int ret; + struct clk_hifiberry_drvdata *drvdata = to_hifiberry_clk(hw); + + switch (rate) { + case 44100: + ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap, + dedicated_44k1_pll_regs, num_dedicated_44k1_pll_regs, + PLL_RESET); + break; + case 88200: + ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap, + dedicated_88k2_pll_regs, num_dedicated_88k2_pll_regs, + PLL_RESET); + break; + case 176400: + ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap, + dedicated_176k4_pll_regs, num_dedicated_176k4_pll_regs, + PLL_RESET); + break; + case 48000: + ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap, + dedicated_48k_pll_regs, num_dedicated_48k_pll_regs, + PLL_RESET); + break; + case 96000: + ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap, + dedicated_96k_pll_regs, num_dedicated_96k_pll_regs, + PLL_RESET); + break; + case 192000: + ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap, + dedicated_192k_pll_regs, num_dedicated_192k_pll_regs, + PLL_RESET); + break; + default: + ret = -EINVAL; + break; + } + to_hifiberry_clk(hw)->rate = rate; + + return ret; +} + +const struct clk_ops clk_hifiberry_dachd_rate_ops = { + .recalc_rate = clk_hifiberry_dachd_recalc_rate, + .round_rate = clk_hifiberry_dachd_round_rate, + .set_rate = clk_hifiberry_dachd_set_rate, +}; + +static int clk_hifiberry_get_prop_values(struct device *dev, + char *prop_name, + struct reg_default *regs) +{ + int ret; + int i; + u8 tmp[2 * HIFIBERRY_PLL_MAX_REGISTER]; + + ret = of_property_read_variable_u8_array(dev->of_node, prop_name, + tmp, 0, 2 * HIFIBERRY_PLL_MAX_REGISTER); + if (ret < 0) + return ret; + if (ret & 1) { + dev_err(dev, + "%s <%s> -> #%i odd number of bytes for reg/val pairs!", + __func__, + prop_name, + ret); + return -EINVAL; + } + ret /= 2; + for (i = 0; i < ret; i++) { + regs[i].reg = (u32)tmp[2 * i]; + regs[i].def = (u32)tmp[2 * i + 1]; + } + return ret; +} + + +static int clk_hifiberry_dachd_dt_parse(struct device *dev) +{ + num_common_pll_regs = clk_hifiberry_get_prop_values(dev, + "common_pll_regs", common_pll_regs); + num_dedicated_44k1_pll_regs = clk_hifiberry_get_prop_values(dev, + "44k1_pll_regs", dedicated_44k1_pll_regs); + num_dedicated_88k2_pll_regs = clk_hifiberry_get_prop_values(dev, + "88k2_pll_regs", dedicated_88k2_pll_regs); + num_dedicated_176k4_pll_regs = clk_hifiberry_get_prop_values(dev, + "176k4_pll_regs", dedicated_176k4_pll_regs); + num_dedicated_48k_pll_regs = clk_hifiberry_get_prop_values(dev, + "48k_pll_regs", dedicated_48k_pll_regs); + num_dedicated_96k_pll_regs = clk_hifiberry_get_prop_values(dev, + "96k_pll_regs", dedicated_96k_pll_regs); + num_dedicated_192k_pll_regs = clk_hifiberry_get_prop_values(dev, + "192k_pll_regs", dedicated_192k_pll_regs); + return 0; +} + + +static int clk_hifiberry_dachd_remove(struct device *dev) +{ + of_clk_del_provider(dev->of_node); + return 0; +} + +const struct regmap_config hifiberry_pll_regmap = { + .reg_bits = 8, + .val_bits = 8, + .max_register = HIFIBERRY_PLL_MAX_REGISTER, + .reg_defaults = hifiberry_pll_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(hifiberry_pll_reg_defaults), + .cache_type = REGCACHE_RBTREE, +}; +EXPORT_SYMBOL_GPL(hifiberry_pll_regmap); + + +static int clk_hifiberry_dachd_i2c_probe(struct i2c_client *i2c) +{ + struct clk_hifiberry_drvdata *hdclk; + int ret = 0; + struct clk_init_data init; + struct device *dev = &i2c->dev; + struct device_node *dev_node = dev->of_node; + struct regmap_config config = hifiberry_pll_regmap; + + hdclk = devm_kzalloc(&i2c->dev, + sizeof(struct clk_hifiberry_drvdata), GFP_KERNEL); + if (!hdclk) + return -ENOMEM; + + i2c_set_clientdata(i2c, hdclk); + + hdclk->regmap = devm_regmap_init_i2c(i2c, &config); + + if (IS_ERR(hdclk->regmap)) + return PTR_ERR(hdclk->regmap); + + /* start PLL to allow detection of DAC */ + ret = clk_hifiberry_dachd_write_pll_regs(hdclk->regmap, + hifiberry_pll_reg_defaults, + ARRAY_SIZE(hifiberry_pll_reg_defaults), + PLL_RESET); + if (ret) + return ret; + + clk_hifiberry_dachd_dt_parse(dev); + + /* restart PLL with configs from DTB */ + ret = clk_hifiberry_dachd_write_pll_regs(hdclk->regmap, common_pll_regs, + num_common_pll_regs, PLL_RESET); + if (ret) + return ret; + + init.name = "clk-hifiberry-dachd"; + init.ops = &clk_hifiberry_dachd_rate_ops; + init.flags = 0; + init.parent_names = NULL; + init.num_parents = 0; + + hdclk->hw.init = &init; + + hdclk->clk = devm_clk_register(dev, &hdclk->hw); + if (IS_ERR(hdclk->clk)) { + dev_err(dev, "unable to register %s\n", init.name); + return PTR_ERR(hdclk->clk); + } + + ret = of_clk_add_provider(dev_node, of_clk_src_simple_get, hdclk->clk); + if (ret != 0) { + dev_err(dev, "Cannot of_clk_add_provider"); + return ret; + } + + ret = clk_set_rate(hdclk->hw.clk, DEFAULT_RATE); + if (ret != 0) { + dev_err(dev, "Cannot set rate : %d\n", ret); + return -EINVAL; + } + + return ret; +} + +static void clk_hifiberry_dachd_i2c_remove(struct i2c_client *i2c) +{ + clk_hifiberry_dachd_remove(&i2c->dev); +} + +static const struct i2c_device_id clk_hifiberry_dachd_i2c_id[] = { + { "dachd-clk", }, + { } +}; +MODULE_DEVICE_TABLE(i2c, clk_hifiberry_dachd_i2c_id); + +static const struct of_device_id clk_hifiberry_dachd_of_match[] = { + { .compatible = "hifiberry,dachd-clk", }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_hifiberry_dachd_of_match); + +static struct i2c_driver clk_hifiberry_dachd_i2c_driver = { + .probe = clk_hifiberry_dachd_i2c_probe, + .remove = clk_hifiberry_dachd_i2c_remove, + .id_table = clk_hifiberry_dachd_i2c_id, + .driver = { + .name = "dachd-clk", + .of_match_table = of_match_ptr(clk_hifiberry_dachd_of_match), + }, +}; + +module_i2c_driver(clk_hifiberry_dachd_i2c_driver); + + +MODULE_DESCRIPTION("HiFiBerry DAC+ HD clock driver"); +MODULE_AUTHOR("Joerg Schambacher <[email protected]>"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:clk-hifiberry-dachd"); diff --git a/drivers/clk/clk-hifiberry-dacpro.c b/drivers/clk/clk-hifiberry-dacpro.c new file mode 100644 index 000000000000..0cbc0349f9f6 --- /dev/null +++ b/drivers/clk/clk-hifiberry-dacpro.c @@ -0,0 +1,180 @@ +/* + * Clock Driver for HiFiBerry DAC Pro + * + * Author: Stuart MacLean + * Copyright 2015 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/clkdev.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/slab.h> +#include <linux/platform_device.h> + +struct ext_clk_rates { + /* Clock rate of CLK44EN attached to GPIO6 pin */ + unsigned long clk_44en; + /* Clock rate of CLK48EN attached to GPIO3 pin */ + unsigned long clk_48en; +}; + +/** + * struct hifiberry_dacpro_clk - Common struct to the HiFiBerry DAC Pro + * @hw: clk_hw for the common clk framework + * @mode: 0 => CLK44EN, 1 => CLK48EN + */ +struct clk_hifiberry_hw { + struct clk_hw hw; + uint8_t mode; + struct ext_clk_rates clk_rates; +}; + +#define to_hifiberry_clk(_hw) container_of(_hw, struct clk_hifiberry_hw, hw) + +static const struct ext_clk_rates hifiberry_dacpro_clks = { + .clk_44en = 22579200UL, + .clk_48en = 24576000UL, +}; + +static const struct ext_clk_rates allo_dac_clks = { + .clk_44en = 45158400UL, + .clk_48en = 49152000UL, +}; + +static const struct of_device_id clk_hifiberry_dacpro_dt_ids[] = { + { .compatible = "hifiberry,dacpro-clk", &hifiberry_dacpro_clks }, + { .compatible = "allo,dac-clk", &allo_dac_clks }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_hifiberry_dacpro_dt_ids); + +static unsigned long clk_hifiberry_dacpro_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_hifiberry_hw *clk = to_hifiberry_clk(hw); + return (clk->mode == 0) ? clk->clk_rates.clk_44en : + clk->clk_rates.clk_48en; +} + +static long clk_hifiberry_dacpro_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + struct clk_hifiberry_hw *clk = to_hifiberry_clk(hw); + long actual_rate; + + if (rate <= clk->clk_rates.clk_44en) { + actual_rate = (long)clk->clk_rates.clk_44en; + } else if (rate >= clk->clk_rates.clk_48en) { + actual_rate = (long)clk->clk_rates.clk_48en; + } else { + long diff44Rate = (long)(rate - clk->clk_rates.clk_44en); + long diff48Rate = (long)(clk->clk_rates.clk_48en - rate); + + if (diff44Rate < diff48Rate) + actual_rate = (long)clk->clk_rates.clk_44en; + else + actual_rate = (long)clk->clk_rates.clk_48en; + } + return actual_rate; +} + + +static int clk_hifiberry_dacpro_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + struct clk_hifiberry_hw *clk = to_hifiberry_clk(hw); + unsigned long actual_rate; + + actual_rate = (unsigned long)clk_hifiberry_dacpro_round_rate(hw, rate, + &parent_rate); + clk->mode = (actual_rate == clk->clk_rates.clk_44en) ? 0 : 1; + return 0; +} + + +const struct clk_ops clk_hifiberry_dacpro_rate_ops = { + .recalc_rate = clk_hifiberry_dacpro_recalc_rate, + .round_rate = clk_hifiberry_dacpro_round_rate, + .set_rate = clk_hifiberry_dacpro_set_rate, +}; + +static int clk_hifiberry_dacpro_probe(struct platform_device *pdev) +{ + const struct of_device_id *of_id; + struct clk_hifiberry_hw *proclk; + struct clk *clk; + struct device *dev; + struct clk_init_data init; + int ret; + + dev = &pdev->dev; + of_id = of_match_node(clk_hifiberry_dacpro_dt_ids, dev->of_node); + if (!of_id) + return -EINVAL; + + proclk = kzalloc(sizeof(struct clk_hifiberry_hw), GFP_KERNEL); + if (!proclk) + return -ENOMEM; + + init.name = "clk-hifiberry-dacpro"; + init.ops = &clk_hifiberry_dacpro_rate_ops; + init.flags = 0; + init.parent_names = NULL; + init.num_parents = 0; + + proclk->mode = 0; + proclk->hw.init = &init; + memcpy(&proclk->clk_rates, of_id->data, sizeof(proclk->clk_rates)); + + clk = devm_clk_register(dev, &proclk->hw); + if (!IS_ERR(clk)) { + ret = of_clk_add_provider(dev->of_node, of_clk_src_simple_get, + clk); + } else { + dev_err(dev, "Fail to register clock driver\n"); + kfree(proclk); + ret = PTR_ERR(clk); + } + return ret; +} + +static void clk_hifiberry_dacpro_remove(struct platform_device *pdev) +{ + of_clk_del_provider(pdev->dev.of_node); +} + +static struct platform_driver clk_hifiberry_dacpro_driver = { + .probe = clk_hifiberry_dacpro_probe, + .remove = clk_hifiberry_dacpro_remove, + .driver = { + .name = "clk-hifiberry-dacpro", + .of_match_table = clk_hifiberry_dacpro_dt_ids, + }, +}; + +static int __init clk_hifiberry_dacpro_init(void) +{ + return platform_driver_register(&clk_hifiberry_dacpro_driver); +} +core_initcall(clk_hifiberry_dacpro_init); + +static void __exit clk_hifiberry_dacpro_exit(void) +{ + platform_driver_unregister(&clk_hifiberry_dacpro_driver); +} +module_exit(clk_hifiberry_dacpro_exit); + +MODULE_DESCRIPTION("HiFiBerry DAC Pro clock driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:clk-hifiberry-dacpro"); diff --git a/drivers/clk/clk-rp1-sdio.c b/drivers/clk/clk-rp1-sdio.c new file mode 100644 index 000000000000..c459bab0575c --- /dev/null +++ b/drivers/clk/clk-rp1-sdio.c @@ -0,0 +1,599 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * SDIO clock driver for RP1 + * + * Copyright (C) 2023 Raspberry Pi Ltd. + */ + +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +// Register : MODE +#define MODE 0x00000000 +#define MODE_BITS 0x70030000 +#define MODE_RESET 0x00000000 +// Field : MODE_STEPS_PER_CYCLE +#define MODE_STEPS_PER_CYCLE_RESET 0x0 +#define MODE_STEPS_PER_CYCLE_BITS 0x70000000 +#define MODE_STEPS_PER_CYCLE_MSB 30 +#define MODE_STEPS_PER_CYCLE_LSB 28 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_20 0x0 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_10 0x1 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_16 0x2 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_8 0x3 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_12 0x4 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_6 0x5 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_5 0x6 +#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_4 0x7 +// Field : MODE_SRC_SEL +#define MODE_SRC_SEL_RESET 0x0 +#define MODE_SRC_SEL_BITS 0x00030000 +#define MODE_SRC_SEL_MSB 17 +#define MODE_SRC_SEL_LSB 16 +#define MODE_SRC_SEL_VALUE_STOP 0x0 +#define MODE_SRC_SEL_VALUE_CLK_ALT_SRC 0x1 +#define MODE_SRC_SEL_VALUE_PLL_SYS_VCO 0x2 +#define MODE_SRC_SEL_VALUE_PLL_SYS_VCO_AGAIN 0x3 +// Register : FROMIP +#define FROMIP 0x00000004 +#define FROMIP_BITS 0x0f9713ff +#define FROMIP_RESET 0x00000000 +// Field : FROMIP_TUNING_CCLK_SEL +#define FROMIP_TUNING_CCLK_SEL_RESET 0x0 +#define FROMIP_TUNING_CCLK_SEL_BITS 0x0f000000 +#define FROMIP_TUNING_CCLK_SEL_MSB 27 +#define FROMIP_TUNING_CCLK_SEL_LSB 24 +// Field : FROMIP_TUNING_CCLK_UPDATE +#define FROMIP_TUNING_CCLK_UPDATE_RESET 0x0 +#define FROMIP_TUNING_CCLK_UPDATE_BITS 0x00800000 +#define FROMIP_TUNING_CCLK_UPDATE_MSB 23 +#define FROMIP_TUNING_CCLK_UPDATE_LSB 23 +// Field : FROMIP_SAMPLE_CCLK_SEL +#define FROMIP_SAMPLE_CCLK_SEL_RESET 0x0 +#define FROMIP_SAMPLE_CCLK_SEL_BITS 0x00100000 +#define FROMIP_SAMPLE_CCLK_SEL_MSB 20 +#define FROMIP_SAMPLE_CCLK_SEL_LSB 20 +// Field : FROMIP_CLK2CARD_ON +#define FROMIP_CLK2CARD_ON_RESET 0x0 +#define FROMIP_CLK2CARD_ON_BITS 0x00040000 +#define FROMIP_CLK2CARD_ON_MSB 18 +#define FROMIP_CLK2CARD_ON_LSB 18 +// Field : FROMIP_CARD_CLK_STABLE +#define FROMIP_CARD_CLK_STABLE_RESET 0x0 +#define FROMIP_CARD_CLK_STABLE_BITS 0x00020000 +#define FROMIP_CARD_CLK_STABLE_MSB 17 +#define FROMIP_CARD_CLK_STABLE_LSB 17 +// Field : FROMIP_CARD_CLK_EN +#define FROMIP_CARD_CLK_EN_RESET 0x0 +#define FROMIP_CARD_CLK_EN_BITS 0x00010000 +#define FROMIP_CARD_CLK_EN_MSB 16 +#define FROMIP_CARD_CLK_EN_LSB 16 +// Field : FROMIP_CLK_GEN_SEL +#define FROMIP_CLK_GEN_SEL_RESET 0x0 +#define FROMIP_CLK_GEN_SEL_BITS 0x00001000 +#define FROMIP_CLK_GEN_SEL_MSB 12 +#define FROMIP_CLK_GEN_SEL_LSB 12 +// Field : FROMIP_FREQ_SEL +#define FROMIP_FREQ_SEL_RESET 0x000 +#define FROMIP_FREQ_SEL_BITS 0x000003ff +#define FROMIP_FREQ_SEL_MSB 9 +#define FROMIP_FREQ_SEL_LSB 0 +// Register : LOCAL +#define LOCAL 0x00000008 +#define LOCAL_BITS 0x1f9713ff +#define LOCAL_RESET 0x00000000 +// Field : LOCAL_TUNING_CCLK_SEL +#define LOCAL_TUNING_CCLK_SEL_RESET 0x00 +#define LOCAL_TUNING_CCLK_SEL_BITS 0x1f000000 +#define LOCAL_TUNING_CCLK_SEL_MSB 28 +#define LOCAL_TUNING_CCLK_SEL_LSB 24 +// Field : LOCAL_TUNING_CCLK_UPDATE +#define LOCAL_TUNING_CCLK_UPDATE_RESET 0x0 +#define LOCAL_TUNING_CCLK_UPDATE_BITS 0x00800000 +#define LOCAL_TUNING_CCLK_UPDATE_MSB 23 +#define LOCAL_TUNING_CCLK_UPDATE_LSB 23 +// Field : LOCAL_SAMPLE_CCLK_SEL +#define LOCAL_SAMPLE_CCLK_SEL_RESET 0x0 +#define LOCAL_SAMPLE_CCLK_SEL_BITS 0x00100000 +#define LOCAL_SAMPLE_CCLK_SEL_MSB 20 +#define LOCAL_SAMPLE_CCLK_SEL_LSB 20 +// Field : LOCAL_CLK2CARD_ON +#define LOCAL_CLK2CARD_ON_RESET 0x0 +#define LOCAL_CLK2CARD_ON_BITS 0x00040000 +#define LOCAL_CLK2CARD_ON_MSB 18 +#define LOCAL_CLK2CARD_ON_LSB 18 +// Field : LOCAL_CARD_CLK_STABLE +#define LOCAL_CARD_CLK_STABLE_RESET 0x0 +#define LOCAL_CARD_CLK_STABLE_BITS 0x00020000 +#define LOCAL_CARD_CLK_STABLE_MSB 17 +#define LOCAL_CARD_CLK_STABLE_LSB 17 +// Field : LOCAL_CARD_CLK_EN +#define LOCAL_CARD_CLK_EN_RESET 0x0 +#define LOCAL_CARD_CLK_EN_BITS 0x00010000 +#define LOCAL_CARD_CLK_EN_MSB 16 +#define LOCAL_CARD_CLK_EN_LSB 16 +// Field : LOCAL_CLK_GEN_SEL +#define LOCAL_CLK_GEN_SEL_RESET 0x0 +#define LOCAL_CLK_GEN_SEL_BITS 0x00001000 +#define LOCAL_CLK_GEN_SEL_MSB 12 +#define LOCAL_CLK_GEN_SEL_LSB 12 +#define LOCAL_CLK_GEN_SEL_VALUE_PROGCLOCKMODE 0x0 +#define LOCAL_CLK_GEN_SEL_VALUE_DIVCLOCKMODE 0x1 +// Field : LOCAL_FREQ_SEL +#define LOCAL_FREQ_SEL_RESET 0x000 +#define LOCAL_FREQ_SEL_BITS 0x000003ff +#define LOCAL_FREQ_SEL_MSB 9 +#define LOCAL_FREQ_SEL_LSB 0 +// Register : USE_LOCAL +#define USE_LOCAL 0x0000000c +#define USE_LOCAL_BITS 0x01951001 +#define USE_LOCAL_RESET 0x00000000 +// Field : USE_LOCAL_TUNING_CCLK_SEL +#define USE_LOCAL_TUNING_CCLK_SEL_RESET 0x0 +#define USE_LOCAL_TUNING_CCLK_SEL_BITS 0x01000000 +#define USE_LOCAL_TUNING_CCLK_SEL_MSB 24 +#define USE_LOCAL_TUNING_CCLK_SEL_LSB 24 +// Field : USE_LOCAL_TUNING_CCLK_UPDATE +#define USE_LOCAL_TUNING_CCLK_UPDATE_RESET 0x0 +#define USE_LOCAL_TUNING_CCLK_UPDATE_BITS 0x00800000 +#define USE_LOCAL_TUNING_CCLK_UPDATE_MSB 23 +#define USE_LOCAL_TUNING_CCLK_UPDATE_LSB 23 +// Field : USE_LOCAL_SAMPLE_CCLK_SEL +#define USE_LOCAL_SAMPLE_CCLK_SEL_RESET 0x0 +#define USE_LOCAL_SAMPLE_CCLK_SEL_BITS 0x00100000 +#define USE_LOCAL_SAMPLE_CCLK_SEL_MSB 20 +#define USE_LOCAL_SAMPLE_CCLK_SEL_LSB 20 +// Field : USE_LOCAL_CLK2CARD_ON +#define USE_LOCAL_CLK2CARD_ON_RESET 0x0 +#define USE_LOCAL_CLK2CARD_ON_BITS 0x00040000 +#define USE_LOCAL_CLK2CARD_ON_MSB 18 +#define USE_LOCAL_CLK2CARD_ON_LSB 18 +// Field : USE_LOCAL_CARD_CLK_EN +#define USE_LOCAL_CARD_CLK_EN_RESET 0x0 +#define USE_LOCAL_CARD_CLK_EN_BITS 0x00010000 +#define USE_LOCAL_CARD_CLK_EN_MSB 16 +#define USE_LOCAL_CARD_CLK_EN_LSB 16 +// Field : USE_LOCAL_CLK_GEN_SEL +#define USE_LOCAL_CLK_GEN_SEL_RESET 0x0 +#define USE_LOCAL_CLK_GEN_SEL_BITS 0x00001000 +#define USE_LOCAL_CLK_GEN_SEL_MSB 12 +#define USE_LOCAL_CLK_GEN_SEL_LSB 12 +// Field : USE_LOCAL_FREQ_SEL +#define USE_LOCAL_FREQ_SEL_RESET 0x0 +#define USE_LOCAL_FREQ_SEL_BITS 0x00000001 +#define USE_LOCAL_FREQ_SEL_MSB 0 +#define USE_LOCAL_FREQ_SEL_LSB 0 +// Register : SD_DELAY +#define SD_DELAY 0x00000010 +#define SD_DELAY_BITS 0x0000001f +#define SD_DELAY_RESET 0x00000000 +// Field : SD_DELAY_STEPS +#define SD_DELAY_STEPS_RESET 0x00 +#define SD_DELAY_STEPS_BITS 0x0000001f +#define SD_DELAY_STEPS_MSB 4 +#define SD_DELAY_STEPS_LSB 0 +// Register : RX_DELAY +#define RX_DELAY 0x00000014 +#define RX_DELAY_BITS 0x19f3331f +#define RX_DELAY_RESET 0x00000000 +// Field : RX_DELAY_BYPASS +#define RX_DELAY_BYPASS_RESET 0x0 +#define RX_DELAY_BYPASS_BITS 0x10000000 +#define RX_DELAY_BYPASS_MSB 28 +#define RX_DELAY_BYPASS_LSB 28 +// Field : RX_DELAY_FAIL_ACTUAL +#define RX_DELAY_FAIL_ACTUAL_RESET 0x0 +#define RX_DELAY_FAIL_ACTUAL_BITS 0x08000000 +#define RX_DELAY_FAIL_ACTUAL_MSB 27 +#define RX_DELAY_FAIL_ACTUAL_LSB 27 +// Field : RX_DELAY_ACTUAL +#define RX_DELAY_ACTUAL_RESET 0x00 +#define RX_DELAY_ACTUAL_BITS 0x01f00000 +#define RX_DELAY_ACTUAL_MSB 24 +#define RX_DELAY_ACTUAL_LSB 20 +// Field : RX_DELAY_OFFSET +#define RX_DELAY_OFFSET_RESET 0x0 +#define RX_DELAY_OFFSET_BITS 0x00030000 +#define RX_DELAY_OFFSET_MSB 17 +#define RX_DELAY_OFFSET_LSB 16 +// Field : RX_DELAY_OVERFLOW +#define RX_DELAY_OVERFLOW_RESET 0x0 +#define RX_DELAY_OVERFLOW_BITS 0x00003000 +#define RX_DELAY_OVERFLOW_MSB 13 +#define RX_DELAY_OVERFLOW_LSB 12 +#define RX_DELAY_OVERFLOW_VALUE_ALLOW 0x0 +#define RX_DELAY_OVERFLOW_VALUE_CLAMP 0x1 +#define RX_DELAY_OVERFLOW_VALUE_FAIL 0x2 +// Field : RX_DELAY_MAP +#define RX_DELAY_MAP_RESET 0x0 +#define RX_DELAY_MAP_BITS 0x00000300 +#define RX_DELAY_MAP_MSB 9 +#define RX_DELAY_MAP_LSB 8 +#define RX_DELAY_MAP_VALUE_DIRECT 0x0 +#define RX_DELAY_MAP_VALUE 0x1 +#define RX_DELAY_MAP_VALUE_STRETCH 0x2 +// Field : RX_DELAY_FIXED +#define RX_DELAY_FIXED_RESET 0x00 +#define RX_DELAY_FIXED_BITS 0x0000001f +#define RX_DELAY_FIXED_MSB 4 +#define RX_DELAY_FIXED_LSB 0 +// Register : NDIV +#define NDIV 0x00000018 +#define NDIV_BITS 0x1fff0000 +#define NDIV_RESET 0x00110000 +// Field : NDIV_DIVB +#define NDIV_DIVB_RESET 0x001 +#define NDIV_DIVB_BITS 0x1ff00000 +#define NDIV_DIVB_MSB 28 +#define NDIV_DIVB_LSB 20 +// Field : NDIV_DIVA +#define NDIV_DIVA_RESET 0x1 +#define NDIV_DIVA_BITS 0x000f0000 +#define NDIV_DIVA_MSB 19 +#define NDIV_DIVA_LSB 16 +// Register : CS +#define CS 0x0000001c +#define CS_BITS 0x00111101 +#define CS_RESET 0x00000001 +// Field : CS_RX_DEL_UPDATED +#define CS_RX_DEL_UPDATED_RESET 0x0 +#define CS_RX_DEL_UPDATED_BITS 0x00100000 +#define CS_RX_DEL_UPDATED_MSB 20 +#define CS_RX_DEL_UPDATED_LSB 20 +// Field : CS_RX_CLK_RUNNING +#define CS_RX_CLK_RUNNING_RESET 0x0 +#define CS_RX_CLK_RUNNING_BITS 0x00010000 +#define CS_RX_CLK_RUNNING_MSB 16 +#define CS_RX_CLK_RUNNING_LSB 16 +// Field : CS_SD_CLK_RUNNING +#define CS_SD_CLK_RUNNING_RESET 0x0 +#define CS_SD_CLK_RUNNING_BITS 0x00001000 +#define CS_SD_CLK_RUNNING_MSB 12 +#define CS_SD_CLK_RUNNING_LSB 12 +// Field : CS_TX_CLK_RUNNING +#define CS_TX_CLK_RUNNING_RESET 0x0 +#define CS_TX_CLK_RUNNING_BITS 0x00000100 +#define CS_TX_CLK_RUNNING_MSB 8 +#define CS_TX_CLK_RUNNING_LSB 8 +// Field : CS_RESET +#define CS_RESET_RESET 0x1 +#define CS_RESET_BITS 0x00000001 +#define CS_RESET_MSB 0 +#define CS_RESET_LSB 0 + +#define FPGA_SRC_RATE 400000000 + +/* Base number of steps to delay in relation to tx clk. + * The relationship of the 3 clocks are as follows: + * tx_clk: This clock is provided to the controller. Data is sent out + * to the pads using this clock. + * sd_clk: This clock is sent out to the card. + * rx_clk: This clock is used to sample the data coming back from the card. + * This may need to be several steps ahead of the tx_clk. The default rx delay + * is used as a base delay, and can be further adjusted by the sd host + * controller during the tuning process if using a DDR50 or faster SD card + */ +/* + * PRJY-1813 - the default SD clock delay needs to be set to ~60% of the total + * number of steps to meet tISU (>6ns) and tIH (>2ns) in high-speed mode. + * On FPGA this means delay SDCLK by 5, and sample RX with a delay of 6. + */ +#define DEFAULT_RX_DELAY 6 +#define DEFAULT_SD_DELAY 5 + +struct rp1_sdio_clkgen { + struct device *dev; + + /* Source clock. Either PLL VCO or fixed freq on FPGA */ + struct clk *src_clk; + /* Desired base frequency. Max freq card can go */ + struct clk *base_clk; + + struct clk_hw hw; + void __iomem *regs; + + /* Starting value of local register before changing freq */ + u32 local_base; +}; + +static inline void clkgen_write(struct rp1_sdio_clkgen *clkgen, u32 reg, u32 val) +{ + dev_dbg(clkgen->dev, "%s: write reg 0x%x: 0x%x\n", __func__, reg, val); + writel(val, clkgen->regs + reg); +} + +static inline u32 clkgen_read(struct rp1_sdio_clkgen *clkgen, u32 reg) +{ + u32 val = readl(clkgen->regs + reg); + + dev_dbg(clkgen->dev, "%s: read reg 0x%x: 0x%x\n", __func__, reg, val); + return val; +} + +static int get_steps(unsigned int steps) +{ + int ret = -1; + + if (steps == 4) + ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_4; + else if (steps == 5) + ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_5; + else if (steps == 6) + ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_6; + else if (steps == 8) + ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_8; + else if (steps == 10) + ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_10; + else if (steps == 12) + ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_12; + else if (steps == 16) + ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_16; + else if (steps == 20) + ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_20; + return ret; +} + +static int rp1_sdio_clk_init(struct rp1_sdio_clkgen *clkgen) +{ + unsigned long src_rate = clk_get_rate(clkgen->src_clk); + unsigned long base_rate = clk_get_rate(clkgen->base_clk); + unsigned int steps = src_rate / base_rate; + u32 reg = 0; + int steps_value = 0; + + dev_dbg(clkgen->dev, "init: src_rate %lu, base_rate %lu, steps %d\n", + src_rate, base_rate, steps); + + /* Assert reset while we set up clkgen */ + clkgen_write(clkgen, CS, CS_RESET_BITS); + + /* Pick clock source */ + if (src_rate == FPGA_SRC_RATE) { + /* Using ALT SRC */ + reg |= MODE_SRC_SEL_VALUE_CLK_ALT_SRC << MODE_SRC_SEL_LSB; + } else { + /* Assume we are using PLL SYS VCO */ + reg |= MODE_SRC_SEL_VALUE_PLL_SYS_VCO << MODE_SRC_SEL_LSB; + } + + /* How many delay steps are available in one cycle for this source */ + steps_value = get_steps(steps); + if (steps_value < 0) { + dev_err(clkgen->dev, "Invalid step value: %d\n", steps); + return -EINVAL; + } + reg |= steps_value << MODE_STEPS_PER_CYCLE_LSB; + + /* Mode register is done now*/ + clkgen_write(clkgen, MODE, reg); + + /* Now set delay mode */ + /* Clamp value if out of range rx delay is used */ + reg = RX_DELAY_OVERFLOW_VALUE_CLAMP << RX_DELAY_OVERFLOW_LSB; + /* SD tuning bus goes from 0x0 to 0xf but we don't necessarily have that + * many steps available depending on the source so map 0x0 -> 0xf to one + * cycle of rx delay + */ + reg |= RX_DELAY_MAP_VALUE_STRETCH << RX_DELAY_MAP_LSB; + + /* Default RX delay */ + dev_dbg(clkgen->dev, "default rx delay %d\n", DEFAULT_RX_DELAY); + reg |= (DEFAULT_RX_DELAY & RX_DELAY_FIXED_BITS) << RX_DELAY_FIXED_LSB; + clkgen_write(clkgen, RX_DELAY, reg); + + /* Default SD delay */ + dev_dbg(clkgen->dev, "default sd delay %d\n", DEFAULT_SD_DELAY); + reg = (DEFAULT_SD_DELAY & SD_DELAY_STEPS_BITS) << SD_DELAY_STEPS_LSB; + clkgen_write(clkgen, SD_DELAY, reg); + + /* We select freq, we turn on tx clock, we turn on sd clk, + * we pick clock generator mode + */ + reg = USE_LOCAL_FREQ_SEL_BITS | USE_LOCAL_CARD_CLK_EN_BITS | + USE_LOCAL_CLK2CARD_ON_BITS | USE_LOCAL_CLK_GEN_SEL_BITS; + clkgen_write(clkgen, USE_LOCAL, reg); + + /* Deassert reset. Reset bit is only writable bit of CS + * reg so fine to write a 0. + */ + clkgen_write(clkgen, CS, 0); + + return 0; +} + +#define RUNNING \ + (CS_TX_CLK_RUNNING_BITS | CS_RX_CLK_RUNNING_BITS | \ + CS_SD_CLK_RUNNING_BITS) +static int rp1_sdio_clk_is_prepared(struct clk_hw *hw) +{ + struct rp1_sdio_clkgen *clkgen = + container_of(hw, struct rp1_sdio_clkgen, hw); + u32 status; + + dev_dbg(clkgen->dev, "is_prepared\n"); + status = clkgen_read(clkgen, CS); + return ((status & RUNNING) == RUNNING); +} + +/* Can define an additional divider if an sd card isn't working at full speed */ +/* #define SLOWDOWN 3 */ + +static unsigned long rp1_sdio_clk_get_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + /* Get the current rate */ + struct rp1_sdio_clkgen *clkgen = + container_of(hw, struct rp1_sdio_clkgen, hw); + unsigned long actual_rate = 0; + u32 ndiv_diva; + u32 ndiv_divb; + u32 tmp; + u32 div; + + tmp = clkgen_read(clkgen, LOCAL); + if ((tmp & LOCAL_CLK2CARD_ON_BITS) == 0) { + dev_dbg(clkgen->dev, "get_rate 0\n"); + return 0; + } + + tmp = clkgen_read(clkgen, NDIV); + ndiv_diva = (tmp & NDIV_DIVA_BITS) >> NDIV_DIVA_LSB; + ndiv_divb = (tmp & NDIV_DIVB_BITS) >> NDIV_DIVB_LSB; + div = ndiv_diva * ndiv_divb; + actual_rate = (clk_get_rate(clkgen->base_clk) / div); + +#ifdef SLOWDOWN + actual_rate *= SLOWDOWN; +#endif + + dev_dbg(clkgen->dev, "get_rate. ndiv_diva %d, ndiv_divb %d = %lu\n", + ndiv_diva, ndiv_divb, actual_rate); + + return actual_rate; +} + +static int rp1_sdio_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct rp1_sdio_clkgen *clkgen = + container_of(hw, struct rp1_sdio_clkgen, hw); + u32 div; + u32 reg; + + dev_dbg(clkgen->dev, "set_rate %lu\n", rate); + + if (rate == 0) { + /* Keep tx clock running */ + clkgen_write(clkgen, LOCAL, LOCAL_CARD_CLK_EN_BITS); + return 0; + } + +#ifdef SLOWDOWN + rate /= SLOWDOWN; +#endif + + div = (clk_get_rate(clkgen->base_clk) / rate) - 1; + reg = LOCAL_CLK_GEN_SEL_BITS | LOCAL_CARD_CLK_EN_BITS | + LOCAL_CLK2CARD_ON_BITS | (div << LOCAL_FREQ_SEL_LSB); + clkgen_write(clkgen, LOCAL, reg); + + return 0; +} + +#define MAX_NDIV (256 * 8) +static int rp1_sdio_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long rate; + struct rp1_sdio_clkgen *clkgen = + container_of(hw, struct rp1_sdio_clkgen, hw); + unsigned long base_rate = clk_get_rate(clkgen->base_clk); + u32 div; + + /* What is the actual rate I can get if I request xyz */ + if (req->rate) { + div = min((u32)(base_rate / req->rate), (u32)MAX_NDIV); + rate = base_rate / div; + req->rate = rate; + dev_dbg(clkgen->dev, "determine_rate %lu: %lu / %d = %lu\n", + req->rate, base_rate, div, rate); + } else { + rate = 0; + dev_dbg(clkgen->dev, "determine_rate %lu: %lu\n", req->rate, + rate); + } + + return 0; +} + +static const struct clk_ops rp1_sdio_clk_ops = { + .is_prepared = rp1_sdio_clk_is_prepared, + .recalc_rate = rp1_sdio_clk_get_rate, + .set_rate = rp1_sdio_clk_set_rate, + .determine_rate = rp1_sdio_clk_determine_rate, +}; + +static int rp1_sdio_clk_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct rp1_sdio_clkgen *clkgen; + void __iomem *regs; + struct clk_init_data init = {}; + int ret; + + clkgen = devm_kzalloc(&pdev->dev, sizeof(*clkgen), GFP_KERNEL); + if (!clkgen) + return -ENOMEM; + platform_set_drvdata(pdev, clkgen); + + clkgen->dev = &pdev->dev; + + /* Source freq */ + clkgen->src_clk = devm_clk_get(&pdev->dev, "src"); + if (IS_ERR(clkgen->src_clk)) { + int err = PTR_ERR(clkgen->src_clk); + + dev_err(&pdev->dev, "failed to get src clk: %d\n", err); + return err; + } + + /* Desired maximum output freq (i.e. base freq) */ + clkgen->base_clk = devm_clk_get(&pdev->dev, "base"); + if (IS_ERR(clkgen->base_clk)) { + int err = PTR_ERR(clkgen->base_clk); + + dev_err(&pdev->dev, "failed to get base clk: %d\n", err); + return err; + } + + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + init.name = node->name; + init.ops = &rp1_sdio_clk_ops; + init.flags = CLK_GET_RATE_NOCACHE; + + clkgen->hw.init = &init; + clkgen->regs = regs; + + dev_info(&pdev->dev, "loaded %s\n", init.name); + + ret = devm_clk_hw_register(&pdev->dev, &clkgen->hw); + if (ret) + return ret; + + ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &clkgen->hw); + if (ret) + return ret; + + ret = rp1_sdio_clk_init(clkgen); + return ret; +} + +static void rp1_sdio_clk_remove(struct platform_device *pdev) +{ +} + +static const struct of_device_id rp1_sdio_clk_dt_ids[] = { + { .compatible = "raspberrypi,rp1-sdio-clk", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rp1_sdio_clk_dt_ids); + +static struct platform_driver rp1_sdio_clk_driver = { + .probe = rp1_sdio_clk_probe, + .remove = rp1_sdio_clk_remove, + .driver = { + .name = "rp1-sdio-clk", + .of_match_table = rp1_sdio_clk_dt_ids, + }, +}; +module_platform_driver(rp1_sdio_clk_driver); + +MODULE_AUTHOR("Liam Fraser <[email protected]>"); +MODULE_DESCRIPTION("RP1 SDIO clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/clk-rp1.c b/drivers/clk/clk-rp1.c index fd144755b879..ab74f20d4e5b 100644 --- a/drivers/clk/clk-rp1.c +++ b/drivers/clk/clk-rp1.c @@ -15,259 +15,259 @@ #include <dt-bindings/clock/raspberrypi,rp1-clocks.h> -#define PLL_SYS_OFFSET 0x08000 -#define PLL_SYS_CS (PLL_SYS_OFFSET + 0x00) -#define PLL_SYS_PWR (PLL_SYS_OFFSET + 0x04) -#define PLL_SYS_FBDIV_INT (PLL_SYS_OFFSET + 0x08) -#define PLL_SYS_FBDIV_FRAC (PLL_SYS_OFFSET + 0x0c) -#define PLL_SYS_PRIM (PLL_SYS_OFFSET + 0x10) -#define PLL_SYS_SEC (PLL_SYS_OFFSET + 0x14) +#define PLL_SYS_OFFSET 0x08000 +#define PLL_SYS_CS (PLL_SYS_OFFSET + 0x00) +#define PLL_SYS_PWR (PLL_SYS_OFFSET + 0x04) +#define PLL_SYS_FBDIV_INT (PLL_SYS_OFFSET + 0x08) +#define PLL_SYS_FBDIV_FRAC (PLL_SYS_OFFSET + 0x0c) +#define PLL_SYS_PRIM (PLL_SYS_OFFSET + 0x10) +#define PLL_SYS_SEC (PLL_SYS_OFFSET + 0x14) -#define PLL_AUDIO_OFFSET 0x0c000 -#define PLL_AUDIO_CS (PLL_AUDIO_OFFSET + 0x00) -#define PLL_AUDIO_PWR (PLL_AUDIO_OFFSET + 0x04) -#define PLL_AUDIO_FBDIV_INT (PLL_AUDIO_OFFSET + 0x08) -#define PLL_AUDIO_FBDIV_FRAC (PLL_AUDIO_OFFSET + 0x0c) -#define PLL_AUDIO_PRIM (PLL_AUDIO_OFFSET + 0x10) -#define PLL_AUDIO_SEC (PLL_AUDIO_OFFSET + 0x14) -#define PLL_AUDIO_TERN (PLL_AUDIO_OFFSET + 0x18) +#define PLL_AUDIO_OFFSET 0x0c000 +#define PLL_AUDIO_CS (PLL_AUDIO_OFFSET + 0x00) +#define PLL_AUDIO_PWR (PLL_AUDIO_OFFSET + 0x04) +#define PLL_AUDIO_FBDIV_INT (PLL_AUDIO_OFFSET + 0x08) +#define PLL_AUDIO_FBDIV_FRAC (PLL_AUDIO_OFFSET + 0x0c) +#define PLL_AUDIO_PRIM (PLL_AUDIO_OFFSET + 0x10) +#define PLL_AUDIO_SEC (PLL_AUDIO_OFFSET + 0x14) +#define PLL_AUDIO_TERN (PLL_AUDIO_OFFSET + 0x18) -#define PLL_VIDEO_OFFSET 0x10000 -#define PLL_VIDEO_CS (PLL_VIDEO_OFFSET + 0x00) -#define PLL_VIDEO_PWR (PLL_VIDEO_OFFSET + 0x04) -#define PLL_VIDEO_FBDIV_INT (PLL_VIDEO_OFFSET + 0x08) -#define PLL_VIDEO_FBDIV_FRAC (PLL_VIDEO_OFFSET + 0x0c) -#define PLL_VIDEO_PRIM (PLL_VIDEO_OFFSET + 0x10) -#define PLL_VIDEO_SEC (PLL_VIDEO_OFFSET + 0x14) +#define PLL_VIDEO_OFFSET 0x10000 +#define PLL_VIDEO_CS (PLL_VIDEO_OFFSET + 0x00) +#define PLL_VIDEO_PWR (PLL_VIDEO_OFFSET + 0x04) +#define PLL_VIDEO_FBDIV_INT (PLL_VIDEO_OFFSET + 0x08) +#define PLL_VIDEO_FBDIV_FRAC (PLL_VIDEO_OFFSET + 0x0c) +#define PLL_VIDEO_PRIM (PLL_VIDEO_OFFSET + 0x10) +#define PLL_VIDEO_SEC (PLL_VIDEO_OFFSET + 0x14) -#define GPCLK_OE_CTRL 0x00000 +#define GPCLK_OE_CTRL 0x00000 -#define CLK_SYS_OFFSET 0x00014 -#define CLK_SYS_CTRL (CLK_SYS_OFFSET + 0x00) -#define CLK_SYS_DIV_INT (CLK_SYS_OFFSET + 0x04) -#define CLK_SYS_SEL (CLK_SYS_OFFSET + 0x0c) +#define CLK_SYS_OFFSET 0x00014 +#define CLK_SYS_CTRL (CLK_SYS_OFFSET + 0x00) +#define CLK_SYS_DIV_INT (CLK_SYS_OFFSET + 0x04) +#define CLK_SYS_SEL (CLK_SYS_OFFSET + 0x0c) -#define CLK_SLOW_OFFSET 0x00024 -#define CLK_SLOW_SYS_CTRL (CLK_SLOW_OFFSET + 0x00) -#define CLK_SLOW_SYS_DIV_INT (CLK_SLOW_OFFSET + 0x04) -#define CLK_SLOW_SYS_SEL (CLK_SLOW_OFFSET + 0x0c) +#define CLK_SLOW_OFFSET 0x00024 +#define CLK_SLOW_SYS_CTRL (CLK_SLOW_OFFSET + 0x00) +#define CLK_SLOW_SYS_DIV_INT (CLK_SLOW_OFFSET + 0x04) +#define CLK_SLOW_SYS_SEL (CLK_SLOW_OFFSET + 0x0c) -#define CLK_DMA_OFFSET 0x00044 -#define CLK_DMA_CTRL (CLK_DMA_OFFSET + 0x00) -#define CLK_DMA_DIV_INT (CLK_DMA_OFFSET + 0x04) -#define CLK_DMA_SEL (CLK_DMA_OFFSET + 0x0c) +#define CLK_DMA_OFFSET 0x00044 +#define CLK_DMA_CTRL (CLK_DMA_OFFSET + 0x00) +#define CLK_DMA_DIV_INT (CLK_DMA_OFFSET + 0x04) +#define CLK_DMA_SEL (CLK_DMA_OFFSET + 0x0c) -#define CLK_UART_OFFSET 0x00054 -#define CLK_UART_CTRL (CLK_UART_OFFSET + 0x00) -#define CLK_UART_DIV_INT (CLK_UART_OFFSET + 0x04) -#define CLK_UART_SEL (CLK_UART_OFFSET + 0x0c) +#define CLK_UART_OFFSET 0x00054 +#define CLK_UART_CTRL (CLK_UART_OFFSET + 0x00) +#define CLK_UART_DIV_INT (CLK_UART_OFFSET + 0x04) +#define CLK_UART_SEL (CLK_UART_OFFSET + 0x0c) -#define CLK_ETH_OFFSET 0x00064 -#define CLK_ETH_CTRL (CLK_ETH_OFFSET + 0x00) -#define CLK_ETH_DIV_INT (CLK_ETH_OFFSET + 0x04) -#define CLK_ETH_SEL (CLK_ETH_OFFSET + 0x0c) +#define CLK_ETH_OFFSET 0x00064 +#define CLK_ETH_CTRL (CLK_ETH_OFFSET + 0x00) +#define CLK_ETH_DIV_INT (CLK_ETH_OFFSET + 0x04) +#define CLK_ETH_SEL (CLK_ETH_OFFSET + 0x0c) -#define CLK_PWM0_OFFSET 0x00074 -#define CLK_PWM0_CTRL (CLK_PWM0_OFFSET + 0x00) -#define CLK_PWM0_DIV_INT (CLK_PWM0_OFFSET + 0x04) -#define CLK_PWM0_DIV_FRAC (CLK_PWM0_OFFSET + 0x08) -#define CLK_PWM0_SEL (CLK_PWM0_OFFSET + 0x0c) +#define CLK_PWM0_OFFSET 0x00074 +#define CLK_PWM0_CTRL (CLK_PWM0_OFFSET + 0x00) +#define CLK_PWM0_DIV_INT (CLK_PWM0_OFFSET + 0x04) +#define CLK_PWM0_DIV_FRAC (CLK_PWM0_OFFSET + 0x08) +#define CLK_PWM0_SEL (CLK_PWM0_OFFSET + 0x0c) -#define CLK_PWM1_OFFSET 0x00084 -#define CLK_PWM1_CTRL (CLK_PWM1_OFFSET + 0x00) -#define CLK_PWM1_DIV_INT (CLK_PWM1_OFFSET + 0x04) -#define CLK_PWM1_DIV_FRAC (CLK_PWM1_OFFSET + 0x08) -#define CLK_PWM1_SEL (CLK_PWM1_OFFSET + 0x0c) +#define CLK_PWM1_OFFSET 0x00084 +#define CLK_PWM1_CTRL (CLK_PWM1_OFFSET + 0x00) +#define CLK_PWM1_DIV_INT (CLK_PWM1_OFFSET + 0x04) +#define CLK_PWM1_DIV_FRAC (CLK_PWM1_OFFSET + 0x08) +#define CLK_PWM1_SEL (CLK_PWM1_OFFSET + 0x0c) -#define CLK_AUDIO_IN_OFFSET 0x00094 -#define CLK_AUDIO_IN_CTRL (CLK_AUDIO_IN_OFFSET + 0x00) -#define CLK_AUDIO_IN_DIV_INT (CLK_AUDIO_IN_OFFSET + 0x04) -#define CLK_AUDIO_IN_SEL (CLK_AUDIO_IN_OFFSET + 0x0c) +#define CLK_AUDIO_IN_OFFSET 0x00094 +#define CLK_AUDIO_IN_CTRL (CLK_AUDIO_IN_OFFSET + 0x00) +#define CLK_AUDIO_IN_DIV_INT (CLK_AUDIO_IN_OFFSET + 0x04) +#define CLK_AUDIO_IN_SEL (CLK_AUDIO_IN_OFFSET + 0x0c) -#define CLK_AUDIO_OUT_OFFSET 0x000a4 -#define CLK_AUDIO_OUT_CTRL (CLK_AUDIO_OUT_OFFSET + 0x00) -#define CLK_AUDIO_OUT_DIV_INT (CLK_AUDIO_OUT_OFFSET + 0x04) -#define CLK_AUDIO_OUT_SEL (CLK_AUDIO_OUT_OFFSET + 0x0c) +#define CLK_AUDIO_OUT_OFFSET 0x000a4 +#define CLK_AUDIO_OUT_CTRL (CLK_AUDIO_OUT_OFFSET + 0x00) +#define CLK_AUDIO_OUT_DIV_INT (CLK_AUDIO_OUT_OFFSET + 0x04) +#define CLK_AUDIO_OUT_SEL (CLK_AUDIO_OUT_OFFSET + 0x0c) -#define CLK_I2S_OFFSET 0x000b4 -#define CLK_I2S_CTRL (CLK_I2S_OFFSET + 0x00) -#define CLK_I2S_DIV_INT (CLK_I2S_OFFSET + 0x04) -#define CLK_I2S_SEL (CLK_I2S_OFFSET + 0x0c) +#define CLK_I2S_OFFSET 0x000b4 +#define CLK_I2S_CTRL (CLK_I2S_OFFSET + 0x00) +#define CLK_I2S_DIV_INT (CLK_I2S_OFFSET + 0x04) +#define CLK_I2S_SEL (CLK_I2S_OFFSET + 0x0c) -#define CLK_MIPI0_CFG_OFFSET 0x000c4 -#define CLK_MIPI0_CFG_CTRL (CLK_MIPI0_CFG_OFFSET + 0x00) -#define CLK_MIPI0_CFG_DIV_INT (CLK_MIPI0_CFG_OFFSET + 0x04) -#define CLK_MIPI0_CFG_SEL (CLK_MIPI0_CFG_OFFSET + 0x0c) +#define CLK_MIPI0_CFG_OFFSET 0x000c4 +#define CLK_MIPI0_CFG_CTRL (CLK_MIPI0_CFG_OFFSET + 0x00) +#define CLK_MIPI0_CFG_DIV_INT (CLK_MIPI0_CFG_OFFSET + 0x04) +#define CLK_MIPI0_CFG_SEL (CLK_MIPI0_CFG_OFFSET + 0x0c) -#define CLK_MIPI1_CFG_OFFSET 0x000d4 -#define CLK_MIPI1_CFG_CTRL (CLK_MIPI1_CFG_OFFSET + 0x00) -#define CLK_MIPI1_CFG_DIV_INT (CLK_MIPI1_CFG_OFFSET + 0x04) -#define CLK_MIPI1_CFG_SEL (CLK_MIPI1_CFG_OFFSET + 0x0c) +#define CLK_MIPI1_CFG_OFFSET 0x000d4 +#define CLK_MIPI1_CFG_CTRL (CLK_MIPI1_CFG_OFFSET + 0x00) +#define CLK_MIPI1_CFG_DIV_INT (CLK_MIPI1_CFG_OFFSET + 0x04) +#define CLK_MIPI1_CFG_SEL (CLK_MIPI1_CFG_OFFSET + 0x0c) -#define CLK_PCIE_AUX_OFFSET 0x000e4 -#define CLK_PCIE_AUX_CTRL (CLK_PCIE_AUX_OFFSET + 0x00) -#define CLK_PCIE_AUX_DIV_INT (CLK_PCIE_AUX_OFFSET + 0x04) -#define CLK_PCIE_AUX_SEL (CLK_PCIE_AUX_OFFSET + 0x0c) +#define CLK_PCIE_AUX_OFFSET 0x000e4 +#define CLK_PCIE_AUX_CTRL (CLK_PCIE_AUX_OFFSET + 0x00) +#define CLK_PCIE_AUX_DIV_INT (CLK_PCIE_AUX_OFFSET + 0x04) +#define CLK_PCIE_AUX_SEL (CLK_PCIE_AUX_OFFSET + 0x0c) -#define CLK_USBH0_MICROFRAME_OFFSET 0x000f4 -#define CLK_USBH0_MICROFRAME_CTRL (CLK_USBH0_MICROFRAME_OFFSET + 0x00) -#define CLK_USBH0_MICROFRAME_DIV_INT (CLK_USBH0_MICROFRAME_OFFSET + 0x04) -#define CLK_USBH0_MICROFRAME_SEL (CLK_USBH0_MICROFRAME_OFFSET + 0x0c) +#define CLK_USBH0_MICROFRAME_OFFSET 0x000f4 +#define CLK_USBH0_MICROFRAME_CTRL (CLK_USBH0_MICROFRAME_OFFSET + 0x00) +#define CLK_USBH0_MICROFRAME_DIV_INT (CLK_USBH0_MICROFRAME_OFFSET + 0x04) +#define CLK_USBH0_MICROFRAME_SEL (CLK_USBH0_MICROFRAME_OFFSET + 0x0c) -#define CLK_USBH1_MICROFRAME_OFFSET 0x00104 -#define CLK_USBH1_MICROFRAME_CTRL (CLK_USBH1_MICROFRAME_OFFSET + 0x00) -#define CLK_USBH1_MICROFRAME_DIV_INT (CLK_USBH1_MICROFRAME_OFFSET + 0x04) -#define CLK_USBH1_MICROFRAME_SEL (CLK_USBH1_MICROFRAME_OFFSET + 0x0c) +#define CLK_USBH1_MICROFRAME_OFFSET 0x00104 +#define CLK_USBH1_MICROFRAME_CTRL (CLK_USBH1_MICROFRAME_OFFSET + 0x00) +#define CLK_USBH1_MICROFRAME_DIV_INT (CLK_USBH1_MICROFRAME_OFFSET + 0x04) +#define CLK_USBH1_MICROFRAME_SEL (CLK_USBH1_MICROFRAME_OFFSET + 0x0c) -#define CLK_USBH0_SUSPEND_OFFSET 0x00114 -#define CLK_USBH0_SUSPEND_CTRL (CLK_USBH0_SUSPEND_OFFSET + 0x00) -#define CLK_USBH0_SUSPEND_DIV_INT (CLK_USBH0_SUSPEND_OFFSET + 0x04) -#define CLK_USBH0_SUSPEND_SEL (CLK_USBH0_SUSPEND_OFFSET + 0x0c) +#define CLK_USBH0_SUSPEND_OFFSET 0x00114 +#define CLK_USBH0_SUSPEND_CTRL (CLK_USBH0_SUSPEND_OFFSET + 0x00) +#define CLK_USBH0_SUSPEND_DIV_INT (CLK_USBH0_SUSPEND_OFFSET + 0x04) +#define CLK_USBH0_SUSPEND_SEL (CLK_USBH0_SUSPEND_OFFSET + 0x0c) -#define CLK_USBH1_SUSPEND_OFFSET 0x00124 -#define CLK_USBH1_SUSPEND_CTRL (CLK_USBH1_SUSPEND_OFFSET + 0x00) -#define CLK_USBH1_SUSPEND_DIV_INT (CLK_USBH1_SUSPEND_OFFSET + 0x04) -#define CLK_USBH1_SUSPEND_SEL (CLK_USBH1_SUSPEND_OFFSET + 0x0c) +#define CLK_USBH1_SUSPEND_OFFSET 0x00124 +#define CLK_USBH1_SUSPEND_CTRL (CLK_USBH1_SUSPEND_OFFSET + 0x00) +#define CLK_USBH1_SUSPEND_DIV_INT (CLK_USBH1_SUSPEND_OFFSET + 0x04) +#define CLK_USBH1_SUSPEND_SEL (CLK_USBH1_SUSPEND_OFFSET + 0x0c) -#define CLK_ETH_TSU_OFFSET 0x00134 -#define CLK_ETH_TSU_CTRL (CLK_ETH_TSU_OFFSET + 0x00) -#define CLK_ETH_TSU_DIV_INT (CLK_ETH_TSU_OFFSET + 0x04) -#define CLK_ETH_TSU_SEL (CLK_ETH_TSU_OFFSET + 0x0c) +#define CLK_ETH_TSU_OFFSET 0x00134 +#define CLK_ETH_TSU_CTRL (CLK_ETH_TSU_OFFSET + 0x00) +#define CLK_ETH_TSU_DIV_INT (CLK_ETH_TSU_OFFSET + 0x04) +#define CLK_ETH_TSU_SEL (CLK_ETH_TSU_OFFSET + 0x0c) -#define CLK_ADC_OFFSET 0x00144 -#define CLK_ADC_CTRL (CLK_ADC_OFFSET + 0x00) -#define CLK_ADC_DIV_INT (CLK_ADC_OFFSET + 0x04) -#define CLK_ADC_SEL (CLK_ADC_OFFSET + 0x0c) +#define CLK_ADC_OFFSET 0x00144 +#define CLK_ADC_CTRL (CLK_ADC_OFFSET + 0x00) +#define CLK_ADC_DIV_INT (CLK_ADC_OFFSET + 0x04) +#define CLK_ADC_SEL (CLK_ADC_OFFSET + 0x0c) -#define CLK_SDIO_TIMER_OFFSET 0x00154 -#define CLK_SDIO_TIMER_CTRL (CLK_SDIO_TIMER_OFFSET + 0x00) -#define CLK_SDIO_TIMER_DIV_INT (CLK_SDIO_TIMER_OFFSET + 0x04) -#define CLK_SDIO_TIMER_SEL (CLK_SDIO_TIMER_OFFSET + 0x0c) +#define CLK_SDIO_TIMER_OFFSET 0x00154 +#define CLK_SDIO_TIMER_CTRL (CLK_SDIO_TIMER_OFFSET + 0x00) +#define CLK_SDIO_TIMER_DIV_INT (CLK_SDIO_TIMER_OFFSET + 0x04) +#define CLK_SDIO_TIMER_SEL (CLK_SDIO_TIMER_OFFSET + 0x0c) -#define CLK_SDIO_ALT_SRC_OFFSET 0x00164 -#define CLK_SDIO_ALT_SRC_CTRL (CLK_SDIO_ALT_SRC_OFFSET + 0x00) -#define CLK_SDIO_ALT_SRC_DIV_INT (CLK_SDIO_ALT_SRC_OFFSET + 0x04) -#define CLK_SDIO_ALT_SRC_SEL (CLK_SDIO_ALT_SRC_OFFSET + 0x0c) +#define CLK_SDIO_ALT_SRC_OFFSET 0x00164 +#define CLK_SDIO_ALT_SRC_CTRL (CLK_SDIO_ALT_SRC_OFFSET + 0x00) +#define CLK_SDIO_ALT_SRC_DIV_INT (CLK_SDIO_ALT_SRC_OFFSET + 0x04) +#define CLK_SDIO_ALT_SRC_SEL (CLK_SDIO_ALT_SRC_OFFSET + 0x0c) -#define CLK_GP0_OFFSET 0x00174 -#define CLK_GP0_CTRL (CLK_GP0_OFFSET + 0x00) -#define CLK_GP0_DIV_INT (CLK_GP0_OFFSET + 0x04) -#define CLK_GP0_DIV_FRAC (CLK_GP0_OFFSET + 0x08) -#define CLK_GP0_SEL (CLK_GP0_OFFSET + 0x0c) +#define CLK_GP0_OFFSET 0x00174 +#define CLK_GP0_CTRL (CLK_GP0_OFFSET + 0x00) +#define CLK_GP0_DIV_INT (CLK_GP0_OFFSET + 0x04) +#define CLK_GP0_DIV_FRAC (CLK_GP0_OFFSET + 0x08) +#define CLK_GP0_SEL (CLK_GP0_OFFSET + 0x0c) -#define CLK_GP1_OFFSET 0x00184 -#define CLK_GP1_CTRL (CLK_GP1_OFFSET + 0x00) -#define CLK_GP1_DIV_INT (CLK_GP1_OFFSET + 0x04) -#define CLK_GP1_DIV_FRAC (CLK_GP1_OFFSET + 0x08) -#define CLK_GP1_SEL (CLK_GP1_OFFSET + 0x0c) +#define CLK_GP1_OFFSET 0x00184 +#define CLK_GP1_CTRL (CLK_GP1_OFFSET + 0x00) +#define CLK_GP1_DIV_INT (CLK_GP1_OFFSET + 0x04) +#define CLK_GP1_DIV_FRAC (CLK_GP1_OFFSET + 0x08) +#define CLK_GP1_SEL (CLK_GP1_OFFSET + 0x0c) -#define CLK_GP2_OFFSET 0x00194 -#define CLK_GP2_CTRL (CLK_GP2_OFFSET + 0x00) -#define CLK_GP2_DIV_INT (CLK_GP2_OFFSET + 0x04) -#define CLK_GP2_DIV_FRAC (CLK_GP2_OFFSET + 0x08) -#define CLK_GP2_SEL (CLK_GP2_OFFSET + 0x0c) +#define CLK_GP2_OFFSET 0x00194 +#define CLK_GP2_CTRL (CLK_GP2_OFFSET + 0x00) +#define CLK_GP2_DIV_INT (CLK_GP2_OFFSET + 0x04) +#define CLK_GP2_DIV_FRAC (CLK_GP2_OFFSET + 0x08) +#define CLK_GP2_SEL (CLK_GP2_OFFSET + 0x0c) -#define CLK_GP3_OFFSET 0x001a4 -#define CLK_GP3_CTRL (CLK_GP3_OFFSET + 0x00) -#define CLK_GP3_DIV_INT (CLK_GP3_OFFSET + 0x04) -#define CLK_GP3_DIV_FRAC (CLK_GP3_OFFSET + 0x08) -#define CLK_GP3_SEL (CLK_GP3_OFFSET + 0x0c) +#define CLK_GP3_OFFSET 0x001a4 +#define CLK_GP3_CTRL (CLK_GP3_OFFSET + 0x00) +#define CLK_GP3_DIV_INT (CLK_GP3_OFFSET + 0x04) +#define CLK_GP3_DIV_FRAC (CLK_GP3_OFFSET + 0x08) +#define CLK_GP3_SEL (CLK_GP3_OFFSET + 0x0c) -#define CLK_GP4_OFFSET 0x001b4 -#define CLK_GP4_CTRL (CLK_GP4_OFFSET + 0x00) -#define CLK_GP4_DIV_INT (CLK_GP4_OFFSET + 0x04) -#define CLK_GP4_DIV_FRAC (CLK_GP4_OFFSET + 0x08) -#define CLK_GP4_SEL (CLK_GP4_OFFSET + 0x0c) +#define CLK_GP4_OFFSET 0x001b4 +#define CLK_GP4_CTRL (CLK_GP4_OFFSET + 0x00) +#define CLK_GP4_DIV_INT (CLK_GP4_OFFSET + 0x04) +#define CLK_GP4_DIV_FRAC (CLK_GP4_OFFSET + 0x08) +#define CLK_GP4_SEL (CLK_GP4_OFFSET + 0x0c) -#define CLK_GP5_OFFSET 0x001c4 -#define CLK_GP5_CTRL (CLK_GP5_OFFSET + 0x00) -#define CLK_GP5_DIV_INT (CLK_GP5_OFFSET + 0x04) -#define CLK_GP5_DIV_FRAC (CLK_GP5_OFFSET + 0x08) -#define CLK_GP5_SEL (CLK_GP5_OFFSET + 0x0c) +#define CLK_GP5_OFFSET 0x001c4 +#define CLK_GP5_CTRL (CLK_GP5_OFFSET + 0x00) +#define CLK_GP5_DIV_INT (CLK_GP5_OFFSET + 0x04) +#define CLK_GP5_DIV_FRAC (CLK_GP5_OFFSET + 0x08) +#define CLK_GP5_SEL (CLK_GP5_OFFSET + 0x0c) -#define CLK_SYS_RESUS_CTRL 0x0020c +#define CLK_SYS_RESUS_CTRL 0x0020c -#define CLK_SLOW_SYS_RESUS_CTRL 0x00214 +#define CLK_SLOW_SYS_RESUS_CTRL 0x00214 -#define FC0_OFFSET 0x0021c -#define FC0_REF_KHZ (FC0_OFFSET + 0x00) -#define FC0_MIN_KHZ (FC0_OFFSET + 0x04) -#define FC0_MAX_KHZ (FC0_OFFSET + 0x08) -#define FC0_DELAY (FC0_OFFSET + 0x0c) -#define FC0_INTERVAL (FC0_OFFSET + 0x10) -#define FC0_SRC (FC0_OFFSET + 0x14) -#define FC0_STATUS (FC0_OFFSET + 0x18) -#define FC0_RESULT (FC0_OFFSET + 0x1c) -#define FC_SIZE 0x20 -#define FC_COUNT 8 -#define FC_NUM(idx, off) ((idx) * 32 + (off)) +#define FC0_OFFSET 0x0021c +#define FC0_REF_KHZ (FC0_OFFSET + 0x00) +#define FC0_MIN_KHZ (FC0_OFFSET + 0x04) +#define FC0_MAX_KHZ (FC0_OFFSET + 0x08) +#define FC0_DELAY (FC0_OFFSET + 0x0c) +#define FC0_INTERVAL (FC0_OFFSET + 0x10) +#define FC0_SRC (FC0_OFFSET + 0x14) +#define FC0_STATUS (FC0_OFFSET + 0x18) +#define FC0_RESULT (FC0_OFFSET + 0x1c) +#define FC_SIZE 0x20 +#define FC_COUNT 8 +#define FC_NUM(idx, off) ((idx) * 32 + (off)) -#define AUX_SEL 1 +#define AUX_SEL 1 -#define VIDEO_CLOCKS_OFFSET 0x4000 -#define VIDEO_CLK_VEC_CTRL (VIDEO_CLOCKS_OFFSET + 0x0000) -#define VIDEO_CLK_VEC_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0004) -#define VIDEO_CLK_VEC_SEL (VIDEO_CLOCKS_OFFSET + 0x000c) -#define VIDEO_CLK_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0010) -#define VIDEO_CLK_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0014) -#define VIDEO_CLK_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x001c) -#define VIDEO_CLK_MIPI0_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0020) -#define VIDEO_CLK_MIPI0_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0024) -#define VIDEO_CLK_MIPI0_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0028) -#define VIDEO_CLK_MIPI0_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x002c) -#define VIDEO_CLK_MIPI1_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0030) -#define VIDEO_CLK_MIPI1_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0034) -#define VIDEO_CLK_MIPI1_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0038) -#define VIDEO_CLK_MIPI1_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x003c) +#define VIDEO_CLOCKS_OFFSET 0x4000 +#define VIDEO_CLK_VEC_CTRL (VIDEO_CLOCKS_OFFSET + 0x0000) +#define VIDEO_CLK_VEC_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0004) +#define VIDEO_CLK_VEC_SEL (VIDEO_CLOCKS_OFFSET + 0x000c) +#define VIDEO_CLK_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0010) +#define VIDEO_CLK_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0014) +#define VIDEO_CLK_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x001c) +#define VIDEO_CLK_MIPI0_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0020) +#define VIDEO_CLK_MIPI0_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0024) +#define VIDEO_CLK_MIPI0_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0028) +#define VIDEO_CLK_MIPI0_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x002c) +#define VIDEO_CLK_MIPI1_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0030) +#define VIDEO_CLK_MIPI1_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0034) +#define VIDEO_CLK_MIPI1_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0038) +#define VIDEO_CLK_MIPI1_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x003c) -#define DIV_INT_8BIT_MAX GENMASK(7, 0) /* max divide for most clocks */ -#define DIV_INT_16BIT_MAX GENMASK(15, 0) /* max divide for GPx, PWM */ -#define DIV_INT_24BIT_MAX GENMASK(23, 0) /* max divide for CLK_SYS */ +#define DIV_INT_8BIT_MAX GENMASK(7, 0) /* max divide for most clocks */ +#define DIV_INT_16BIT_MAX GENMASK(15, 0) /* max divide for GPx, PWM */ +#define DIV_INT_24BIT_MAX GENMASK(23, 0) /* max divide for CLK_SYS */ -#define FC0_STATUS_DONE BIT(4) -#define FC0_STATUS_RUNNING BIT(8) -#define FC0_RESULT_FRAC_SHIFT 5 +#define FC0_STATUS_DONE BIT(4) +#define FC0_STATUS_RUNNING BIT(8) +#define FC0_RESULT_FRAC_SHIFT 5 -#define PLL_PRIM_DIV1_MASK GENMASK(18, 16) -#define PLL_PRIM_DIV2_MASK GENMASK(14, 12) +#define PLL_PRIM_DIV1_MASK GENMASK(18, 16) +#define PLL_PRIM_DIV2_MASK GENMASK(14, 12) -#define PLL_SEC_DIV_MASK GENMASK(12, 8) +#define PLL_SEC_DIV_MASK GENMASK(12, 8) -#define PLL_CS_LOCK BIT(31) -#define PLL_CS_REFDIV_MASK BIT(1) +#define PLL_CS_LOCK BIT(31) +#define PLL_CS_REFDIV_MASK BIT(1) -#define PLL_PWR_PD BIT(0) -#define PLL_PWR_DACPD BIT(1) -#define PLL_PWR_DSMPD BIT(2) -#define PLL_PWR_POSTDIVPD BIT(3) -#define PLL_PWR_4PHASEPD BIT(4) -#define PLL_PWR_VCOPD BIT(5) -#define PLL_PWR_MASK GENMASK(5, 0) +#define PLL_PWR_PD BIT(0) +#define PLL_PWR_DACPD BIT(1) +#define PLL_PWR_DSMPD BIT(2) +#define PLL_PWR_POSTDIVPD BIT(3) +#define PLL_PWR_4PHASEPD BIT(4) +#define PLL_PWR_VCOPD BIT(5) +#define PLL_PWR_MASK GENMASK(5, 0) -#define PLL_SEC_RST BIT(16) -#define PLL_SEC_IMPL BIT(31) +#define PLL_SEC_RST BIT(16) +#define PLL_SEC_IMPL BIT(31) /* PLL phase output for both PRI and SEC */ -#define PLL_PH_EN BIT(4) -#define PLL_PH_PHASE_SHIFT 0 +#define PLL_PH_EN BIT(4) +#define PLL_PH_PHASE_SHIFT 0 -#define RP1_PLL_PHASE_0 0 -#define RP1_PLL_PHASE_90 1 -#define RP1_PLL_PHASE_180 2 -#define RP1_PLL_PHASE_270 3 +#define RP1_PLL_PHASE_0 0 +#define RP1_PLL_PHASE_90 1 +#define RP1_PLL_PHASE_180 2 +#define RP1_PLL_PHASE_270 3 /* Clock fields for all clocks */ -#define CLK_CTRL_ENABLE BIT(11) -#define CLK_CTRL_AUXSRC_MASK GENMASK(9, 5) -#define CLK_CTRL_SRC_SHIFT 0 -#define CLK_DIV_FRAC_BITS 16 +#define CLK_CTRL_ENABLE BIT(11) +#define CLK_CTRL_AUXSRC_MASK GENMASK(9, 5) +#define CLK_CTRL_SRC_SHIFT 0 +#define CLK_DIV_FRAC_BITS 16 -#define LOCK_TIMEOUT_US 100000 -#define LOCK_POLL_DELAY_US 5 +#define LOCK_TIMEOUT_US 100000 +#define LOCK_POLL_DELAY_US 5 -#define MAX_CLK_PARENTS 16 +#define MAX_CLK_PARENTS 16 -#define PLL_DIV_INVALID 19 +#define PLL_DIV_INVALID 19 /* * Secondary PLL channel output divider table. * Divider values range from 8 to 19, where @@ -282,8 +282,8 @@ static const struct clk_div_table pll_sec_div_table[] = { { 0x05, PLL_DIV_INVALID }, { 0x06, PLL_DIV_INVALID }, { 0x07, PLL_DIV_INVALID }, - { 0x08, 8 }, - { 0x09, 9 }, + { 0x08, 8 }, + { 0x09, 9 }, { 0x0a, 10 }, { 0x0b, 11 }, { 0x0c, 12 }, @@ -373,8 +373,8 @@ static struct rp1_clk_desc *clk_audio; static struct rp1_clk_desc *clk_i2s; static struct clk_hw *clk_xosc; -static inline -void clockman_write(struct rp1_clockman *clockman, u32 reg, u32 val) +static inline void clockman_write(struct rp1_clockman *clockman, u32 reg, + u32 val) { regmap_write(clockman->regmap, reg, val); } @@ -390,7 +390,8 @@ static inline u32 clockman_read(struct rp1_clockman *clockman, u32 reg) static int rp1_pll_core_is_on(struct clk_hw *hw) { - struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clk_desc *pll_core = + container_of(hw, struct rp1_clk_desc, hw); struct rp1_clockman *clockman = pll_core->clockman; const struct rp1_pll_core_data *data = pll_core->data; u32 pwr = clockman_read(clockman, data->pwr_reg); @@ -400,7 +401,8 @@ static int rp1_pll_core_is_on(struct clk_hw *hw) static int rp1_pll_core_on(struct clk_hw *hw) { - struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clk_desc *pll_core = + container_of(hw, struct rp1_clk_desc, hw); struct rp1_clockman *clockman = pll_core->clockman; const struct rp1_pll_core_data *data = pll_core->data; u32 fbdiv_frac, val; @@ -423,8 +425,8 @@ static int rp1_pll_core_on(struct clk_hw *hw) /* Wait for the PLL to lock. */ ret = regmap_read_poll_timeout(clockman->regmap, data->cs_reg, val, - val & PLL_CS_LOCK, - LOCK_POLL_DELAY_US, LOCK_TIMEOUT_US); + val & PLL_CS_LOCK, LOCK_POLL_DELAY_US, + LOCK_TIMEOUT_US); if (ret) dev_err(clockman->dev, "%s: can't lock PLL\n", clk_hw_get_name(hw)); @@ -434,7 +436,8 @@ static int rp1_pll_core_on(struct clk_hw *hw) static void rp1_pll_core_off(struct clk_hw *hw) { - struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clk_desc *pll_core = + container_of(hw, struct rp1_clk_desc, hw); struct rp1_clockman *clockman = pll_core->clockman; const struct rp1_pll_core_data *data = pll_core->data; @@ -474,10 +477,11 @@ static inline unsigned long get_pll_core_divider(struct clk_hw *hw, return calc_rate; } -static int rp1_pll_core_set_rate(struct clk_hw *hw, - unsigned long rate, unsigned long parent_rate) +static int rp1_pll_core_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { - struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clk_desc *pll_core = + container_of(hw, struct rp1_clk_desc, hw); struct rp1_clockman *clockman = pll_core->clockman; const struct rp1_pll_core_data *data = pll_core->data; u32 fbdiv_int, fbdiv_frac; @@ -488,8 +492,7 @@ static int rp1_pll_core_set_rate(struct clk_hw *hw, clockman_write(clockman, data->fbdiv_frac_reg, 0); spin_unlock(&clockman->regs_lock); - get_pll_core_divider(hw, rate, parent_rate, - &fbdiv_int, &fbdiv_frac); + get_pll_core_divider(hw, rate, parent_rate, &fbdiv_int, &fbdiv_frac); spin_lock(&clockman->regs_lock); clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD); @@ -505,7 +508,7 @@ static int rp1_pll_core_set_rate(struct clk_hw *hw, /* Don't need to divide ref unless parent_rate > (output freq / 16) */ clockman_write(clockman, data->cs_reg, clockman_read(clockman, data->cs_reg) | - PLL_CS_REFDIV_MASK); + PLL_CS_REFDIV_MASK); spin_unlock(&clockman->regs_lock); return 0; @@ -514,7 +517,8 @@ static int rp1_pll_core_set_rate(struct clk_hw *hw, static unsigned long rp1_pll_core_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clk_desc *pll_core = + container_of(hw, struct rp1_clk_desc, hw); struct rp1_clockman *clockman = pll_core->clockman; const struct rp1_pll_core_data *data = pll_core->data; u32 fbdiv_int, fbdiv_frac; @@ -538,8 +542,7 @@ static int rp1_pll_core_determine_rate(struct clk_hw *hw, u32 fbdiv_int, fbdiv_frac; req->rate = get_pll_core_divider(hw, req->rate, req->best_parent_rate, - &fbdiv_int, - &fbdiv_frac); + &fbdiv_int, &fbdiv_frac); return 0; } @@ -549,8 +552,8 @@ static void get_pll_prim_dividers(unsigned long rate, unsigned long parent_rate, { unsigned int div1, div2; unsigned int best_div1 = 7, best_div2 = 7; - unsigned long best_rate_diff = - abs_diff(DIV_ROUND_CLOSEST(parent_rate, best_div1 * best_div2), rate); + unsigned long best_rate_diff = abs_diff( + DIV_ROUND_CLOSEST(parent_rate, best_div1 * best_div2), rate); unsigned long rate_diff, calc_rate; for (div1 = 1; div1 <= 7; div1++) { @@ -575,8 +578,8 @@ done: *divider2 = best_div2; } -static int rp1_pll_set_rate(struct clk_hw *hw, - unsigned long rate, unsigned long parent_rate) +static int rp1_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { struct rp1_clk_desc *pll = container_of(hw, struct rp1_clk_desc, hw); struct rp1_clockman *clockman = pll->clockman; @@ -695,7 +698,8 @@ static int rp1_pll_ph_determine_rate(struct clk_hw *hw, static int rp1_pll_divider_is_on(struct clk_hw *hw) { - struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw); + struct rp1_clk_desc *divider = + container_of(hw, struct rp1_clk_desc, div.hw); struct rp1_clockman *clockman = divider->clockman; const struct rp1_pll_data *data = divider->data; @@ -704,7 +708,8 @@ static int rp1_pll_divider_is_on(struct clk_hw *hw) static int rp1_pll_divider_on(struct clk_hw *hw) { - struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw); + struct rp1_clk_desc *divider = + container_of(hw, struct rp1_clk_desc, div.hw); struct rp1_clockman *clockman = divider->clockman; const struct rp1_pll_data *data = divider->data; @@ -720,7 +725,8 @@ static int rp1_pll_divider_on(struct clk_hw *hw) static void rp1_pll_divider_off(struct clk_hw *hw) { - struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw); + struct rp1_clk_desc *divider = + container_of(hw, struct rp1_clk_desc, div.hw); struct rp1_clockman *clockman = divider->clockman; const struct rp1_pll_data *data = divider->data; @@ -730,11 +736,11 @@ static void rp1_pll_divider_off(struct clk_hw *hw) spin_unlock(&clockman->regs_lock); } -static int rp1_pll_divider_set_rate(struct clk_hw *hw, - unsigned long rate, +static int rp1_pll_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw); + struct rp1_clk_desc *divider = + container_of(hw, struct rp1_clk_desc, div.hw); struct rp1_clockman *clockman = divider->clockman; const struct rp1_pll_data *data = divider->data; u32 div, sec; @@ -796,7 +802,8 @@ static unsigned long rp1_clock_recalc_rate(struct clk_hw *hw, div = clockman_read(clockman, data->div_int_reg); frac = (data->div_frac_reg != 0) ? - clockman_read(clockman, data->div_frac_reg) : 0; + clockman_read(clockman, data->div_frac_reg) : + 0; /* If the integer portion of the divider is 0, treat it as 2^16 */ if (!div) @@ -818,11 +825,13 @@ static int rp1_clock_on(struct clk_hw *hw) spin_lock(&clockman->regs_lock); clockman_write(clockman, data->ctrl_reg, - clockman_read(clockman, data->ctrl_reg) | CLK_CTRL_ENABLE); + clockman_read(clockman, data->ctrl_reg) | + CLK_CTRL_ENABLE); /* If this is a GPCLK, turn on the output-enable */ if (data->oe_mask) clockman_write(clockman, GPCLK_OE_CTRL, - clockman_read(clockman, GPCLK_OE_CTRL) | data->oe_mask); + clockman_read(clockman, GPCLK_OE_CTRL) | + data->oe_mask); spin_unlock(&clockman->regs_lock); return 0; @@ -836,11 +845,13 @@ static void rp1_clock_off(struct clk_hw *hw) spin_lock(&clockman->regs_lock); clockman_write(clockman, data->ctrl_reg, - clockman_read(clockman, data->ctrl_reg) & ~CLK_CTRL_ENABLE); + clockman_read(clockman, data->ctrl_reg) & + ~CLK_CTRL_ENABLE); /* If this is a GPCLK, turn off the output-enable */ if (data->oe_mask) clockman_write(clockman, GPCLK_OE_CTRL, - clockman_read(clockman, GPCLK_OE_CTRL) & ~data->oe_mask); + clockman_read(clockman, GPCLK_OE_CTRL) & + ~data->oe_mask); spin_unlock(&clockman->regs_lock); } @@ -868,8 +879,7 @@ static u32 rp1_clock_choose_div(unsigned long rate, unsigned long parent_rate, div <<= CLK_DIV_FRAC_BITS; } - div = clamp(div, - 1ull << CLK_DIV_FRAC_BITS, + div = clamp(div, 1ull << CLK_DIV_FRAC_BITS, (u64)data->div_int_max << CLK_DIV_FRAC_BITS); return div; @@ -929,7 +939,8 @@ static int rp1_clock_set_parent(struct clk_hw *hw, u8 index) /* Select parent from aux list */ ctrl &= ~CLK_CTRL_AUXSRC_MASK; - ctrl |= FIELD_PREP(CLK_CTRL_AUXSRC_MASK, index - data->num_std_parents); + ctrl |= FIELD_PREP(CLK_CTRL_AUXSRC_MASK, + index - data->num_std_parents); /* Set src to aux list */ ctrl &= ~data->clk_src_mask; ctrl |= (AUX_SEL << CLK_CTRL_SRC_SHIFT) & data->clk_src_mask; @@ -948,10 +959,8 @@ static int rp1_clock_set_parent(struct clk_hw *hw, u8 index) return 0; } -static int rp1_clock_set_rate_and_parent(struct clk_hw *hw, - unsigned long rate, - unsigned long parent_rate, - u8 parent) +static int rp1_clock_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate, u8 parent) { struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); struct rp1_clockman *clockman = clock->clockman; @@ -962,7 +971,8 @@ static int rp1_clock_set_rate_and_parent(struct clk_hw *hw, clockman_write(clockman, data->div_int_reg, div >> CLK_DIV_FRAC_BITS); if (data->div_frac_reg) - clockman_write(clockman, data->div_frac_reg, div << (32 - CLK_DIV_FRAC_BITS)); + clockman_write(clockman, data->div_frac_reg, + div << (32 - CLK_DIV_FRAC_BITS)); spin_unlock(&clockman->regs_lock); @@ -983,8 +993,8 @@ static unsigned long calc_core_pll_rate(struct clk_hw *pll_hw, int *pdiv_prim, int *pdiv_clk) { static const int prim_divs[] = { - 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 15, 16, - 18, 20, 21, 24, 25, 28, 30, 35, 36, 42, 49, + 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 15, + 16, 18, 20, 21, 24, 25, 28, 30, 35, 36, 42, 49, }; const unsigned long xosc_rate = clk_hw_get_rate(clk_xosc); const unsigned long core_min = xosc_rate * 16; @@ -1018,7 +1028,9 @@ static unsigned long calc_core_pll_rate(struct clk_hw *pll_hw, div = ((best_rate << 24) + xosc_rate / 2) / xosc_rate; div_int = div >> 24; div_frac = div % (1 << 24); - core_rate = (xosc_rate * ((div_int << 24) + div_frac) + (1 << 23)) >> 24; + core_rate = (xosc_rate * ((div_int << 24) + div_frac) + + (1 << 23)) >> + 24; } else { core_rate = 0; } @@ -1031,8 +1043,7 @@ static unsigned long calc_core_pll_rate(struct clk_hw *pll_hw, return core_rate; } -static void rp1_clock_choose_div_and_prate(struct clk_hw *hw, - int parent_idx, +static void rp1_clock_choose_div_and_prate(struct clk_hw *hw, int parent_idx, unsigned long rate, unsigned long *prate, unsigned long *calc_rate) @@ -1047,7 +1058,8 @@ static void rp1_clock_choose_div_and_prate(struct clk_hw *hw, parent = clk_hw_get_parent_by_index(hw, parent_idx); - if (hw == clk_i2s_hw && clk_i2s->cached_rate == rate && parent == clk_audio_hw) { + if (hw == clk_i2s_hw && clk_i2s->cached_rate == rate && + parent == clk_audio_hw) { *prate = clk_audio->cached_rate; *calc_rate = rate; return; @@ -1057,7 +1069,8 @@ static void rp1_clock_choose_div_and_prate(struct clk_hw *hw, unsigned long core_rate, audio_rate, i2s_rate; int div_prim, div_clk; - core_rate = calc_core_pll_rate(parent, rate, &div_prim, &div_clk); + core_rate = + calc_core_pll_rate(parent, rate, &div_prim, &div_clk); audio_rate = DIV_ROUND_CLOSEST(core_rate, div_prim); i2s_rate = DIV_ROUND_CLOSEST(audio_rate, div_clk); clk_audio_core->cached_rate = core_rate; @@ -1152,8 +1165,8 @@ static int rp1_clock_determine_rate(struct clk_hw *hw, return 0; } -static int rp1_varsrc_set_rate(struct clk_hw *hw, - unsigned long rate, unsigned long parent_rate) +static int rp1_varsrc_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); @@ -1273,8 +1286,8 @@ static struct clk_hw *rp1_register_clock(struct rp1_clockman *clockman, const struct rp1_clock_data *clock_data = desc->data; int ret; - if (WARN_ON_ONCE(MAX_CLK_PARENTS < - clock_data->num_std_parents + clock_data->num_aux_parents)) + if (WARN_ON_ONCE(MAX_CLK_PARENTS < clock_data->num_std_parents + + clock_data->num_aux_parents)) return ERR_PTR(-EINVAL); /* There must be a gap for the AUX selector */ @@ -1292,168 +1305,114 @@ static struct clk_hw *rp1_register_clock(struct rp1_clockman *clockman, } /* Assignment helper macros for different clock types. */ -#define _REGISTER(f, ...) { .clk_register = f, __VA_ARGS__ } +#define _REGISTER(f, ...) { .clk_register = f, __VA_ARGS__ } -#define CLK_DATA(type, ...) .data = &(struct type) { __VA_ARGS__ } +#define CLK_DATA(type, ...) \ + .data = &(struct type) \ + { \ + __VA_ARGS__ \ + } -#define REGISTER_PLL(...) _REGISTER(&rp1_register_pll, \ - __VA_ARGS__) +#define REGISTER_PLL(...) _REGISTER(&rp1_register_pll, __VA_ARGS__) -#define REGISTER_PLL_DIV(...) _REGISTER(&rp1_register_pll_divider, \ - __VA_ARGS__) +#define REGISTER_PLL_DIV(...) _REGISTER(&rp1_register_pll_divider, __VA_ARGS__) -#define REGISTER_CLK(...) _REGISTER(&rp1_register_clock, \ - __VA_ARGS__) +#define REGISTER_CLK(...) _REGISTER(&rp1_register_clock, __VA_ARGS__) -static struct rp1_clk_desc pll_sys_core_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_sys_core", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_pll_core_ops, - CLK_IS_CRITICAL - ), - CLK_DATA(rp1_pll_core_data, - .cs_reg = PLL_SYS_CS, - .pwr_reg = PLL_SYS_PWR, - .fbdiv_int_reg = PLL_SYS_FBDIV_INT, - .fbdiv_frac_reg = PLL_SYS_FBDIV_FRAC, - ) -); +static struct rp1_clk_desc pll_sys_core_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_sys_core", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_pll_core_ops, CLK_IS_CRITICAL), + CLK_DATA(rp1_pll_core_data, .cs_reg = PLL_SYS_CS, + .pwr_reg = PLL_SYS_PWR, + .fbdiv_int_reg = PLL_SYS_FBDIV_INT, + .fbdiv_frac_reg = PLL_SYS_FBDIV_FRAC, )); -static struct rp1_clk_desc pll_audio_core_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_audio_core", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_pll_core_ops, - CLK_IS_CRITICAL - ), - CLK_DATA(rp1_pll_core_data, - .cs_reg = PLL_AUDIO_CS, - .pwr_reg = PLL_AUDIO_PWR, - .fbdiv_int_reg = PLL_AUDIO_FBDIV_INT, - .fbdiv_frac_reg = PLL_AUDIO_FBDIV_FRAC, - ) -); +static struct rp1_clk_desc pll_audio_core_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_audio_core", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_pll_core_ops, CLK_IS_CRITICAL), + CLK_DATA(rp1_pll_core_data, .cs_reg = PLL_AUDIO_CS, + .pwr_reg = PLL_AUDIO_PWR, + .fbdiv_int_reg = PLL_AUDIO_FBDIV_INT, + .fbdiv_frac_reg = PLL_AUDIO_FBDIV_FRAC, )); -static struct rp1_clk_desc pll_video_core_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_video_core", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_pll_core_ops, - CLK_IS_CRITICAL - ), - CLK_DATA(rp1_pll_core_data, - .cs_reg = PLL_VIDEO_CS, - .pwr_reg = PLL_VIDEO_PWR, - .fbdiv_int_reg = PLL_VIDEO_FBDIV_INT, - .fbdiv_frac_reg = PLL_VIDEO_FBDIV_FRAC, - ) -); +static struct rp1_clk_desc pll_video_core_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_video_core", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_pll_core_ops, CLK_IS_CRITICAL), + CLK_DATA(rp1_pll_core_data, .cs_reg = PLL_VIDEO_CS, + .pwr_reg = PLL_VIDEO_PWR, + .fbdiv_int_reg = PLL_VIDEO_FBDIV_INT, + .fbdiv_frac_reg = PLL_VIDEO_FBDIV_FRAC, )); -static struct rp1_clk_desc pll_sys_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_sys", - (const struct clk_parent_data[]) { - { .hw = &pll_sys_core_desc.hw } - }, - &rp1_pll_ops, - 0 - ), - CLK_DATA(rp1_pll_data, - .ctrl_reg = PLL_SYS_PRIM, - .fc0_src = FC_NUM(0, 2), - ) -); +static struct rp1_clk_desc pll_sys_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_sys", + (const struct clk_parent_data[]){ + { .hw = &pll_sys_core_desc.hw } }, + &rp1_pll_ops, 0), + CLK_DATA(rp1_pll_data, .ctrl_reg = PLL_SYS_PRIM, + .fc0_src = FC_NUM(0, 2), )); -static struct rp1_clk_desc pll_audio_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_audio", - (const struct clk_parent_data[]) { - { .hw = &pll_audio_core_desc.hw } - }, - &rp1_pll_ops, - CLK_SET_RATE_PARENT - ), - CLK_DATA(rp1_pll_data, - .ctrl_reg = PLL_AUDIO_PRIM, - .fc0_src = FC_NUM(4, 2), - ) -); +static struct rp1_clk_desc pll_audio_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_audio", + (const struct clk_parent_data[]){ + { .hw = &pll_audio_core_desc.hw } }, + &rp1_pll_ops, CLK_SET_RATE_PARENT), + CLK_DATA(rp1_pll_data, .ctrl_reg = PLL_AUDIO_PRIM, + .fc0_src = FC_NUM(4, 2), )); -static struct rp1_clk_desc pll_video_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_video", - (const struct clk_parent_data[]) { - { .hw = &pll_video_core_desc.hw } - }, - &rp1_pll_ops, - 0 - ), - CLK_DATA(rp1_pll_data, - .ctrl_reg = PLL_VIDEO_PRIM, - .fc0_src = FC_NUM(3, 2), - ) -); +static struct rp1_clk_desc pll_video_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_video", + (const struct clk_parent_data[]){ + { .hw = &pll_video_core_desc.hw } }, + &rp1_pll_ops, 0), + CLK_DATA(rp1_pll_data, .ctrl_reg = PLL_VIDEO_PRIM, + .fc0_src = FC_NUM(3, 2), )); -static struct rp1_clk_desc pll_sys_sec_desc = REGISTER_PLL_DIV( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_sys_sec", - (const struct clk_parent_data[]) { - { .hw = &pll_sys_core_desc.hw } - }, - &rp1_pll_divider_ops, - 0 - ), - CLK_DATA(rp1_pll_data, - .ctrl_reg = PLL_SYS_SEC, - .fc0_src = FC_NUM(2, 2), - ) -); +static struct rp1_clk_desc pll_sys_sec_desc = + REGISTER_PLL_DIV(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_sys_sec", + (const struct clk_parent_data[]){ + { .hw = &pll_sys_core_desc.hw } }, + &rp1_pll_divider_ops, 0), + CLK_DATA(rp1_pll_data, .ctrl_reg = PLL_SYS_SEC, + .fc0_src = FC_NUM(2, 2), )); -static struct rp1_clk_desc pll_video_sec_desc = REGISTER_PLL_DIV( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_video_sec", - (const struct clk_parent_data[]) { - { .hw = &pll_video_core_desc.hw } - }, - &rp1_pll_divider_ops, - 0 - ), - CLK_DATA(rp1_pll_data, - .ctrl_reg = PLL_VIDEO_SEC, - .fc0_src = FC_NUM(5, 3), - ) -); +static struct rp1_clk_desc pll_video_sec_desc = + REGISTER_PLL_DIV(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_video_sec", + (const struct clk_parent_data[]){ + { .hw = &pll_video_core_desc.hw } }, + &rp1_pll_divider_ops, 0), + CLK_DATA(rp1_pll_data, .ctrl_reg = PLL_VIDEO_SEC, + .fc0_src = FC_NUM(5, 3), )); static const struct clk_parent_data clk_eth_tsu_parents[] = { - { .index = 0 }, - { .hw = &pll_video_sec_desc.hw }, - { .index = -1 }, - { .index = -1 }, - { .index = -1 }, - { .index = -1 }, - { .index = -1 }, - { .index = -1 }, + { .index = 0 }, { .hw = &pll_video_sec_desc.hw }, + { .index = -1 }, { .index = -1 }, + { .index = -1 }, { .index = -1 }, + { .index = -1 }, { .index = -1 }, }; -static struct rp1_clk_desc clk_eth_tsu_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_eth_tsu", - clk_eth_tsu_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 8, - .ctrl_reg = CLK_ETH_TSU_CTRL, - .div_int_reg = CLK_ETH_TSU_DIV_INT, - .sel_reg = CLK_ETH_TSU_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 50 * HZ_PER_MHZ, - .fc0_src = FC_NUM(5, 7), - ) -); +static struct rp1_clk_desc clk_eth_tsu_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA("clk_eth_tsu", + clk_eth_tsu_parents, + &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 8, + .ctrl_reg = CLK_ETH_TSU_CTRL, + .div_int_reg = CLK_ETH_TSU_DIV_INT, + .sel_reg = CLK_ETH_TSU_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(5, 7), )); static const struct clk_parent_data clk_eth_parents[] = { { .hw = &pll_sys_sec_desc.div.hw }, @@ -1461,24 +1420,16 @@ static const struct clk_parent_data clk_eth_parents[] = { { .hw = &pll_video_sec_desc.hw }, }; -static struct rp1_clk_desc clk_eth_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_eth", - clk_eth_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 3, - .ctrl_reg = CLK_ETH_CTRL, - .div_int_reg = CLK_ETH_DIV_INT, - .sel_reg = CLK_ETH_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 125 * HZ_PER_MHZ, - .fc0_src = FC_NUM(4, 6), - ) -); +static struct rp1_clk_desc clk_eth_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_eth", clk_eth_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 3, .ctrl_reg = CLK_ETH_CTRL, + .div_int_reg = CLK_ETH_DIV_INT, + .sel_reg = CLK_ETH_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 125 * HZ_PER_MHZ, + .fc0_src = FC_NUM(4, 6), )); static const struct clk_parent_data clk_sys_parents[] = { { .index = 0 }, @@ -1486,126 +1437,79 @@ static const struct clk_parent_data clk_sys_parents[] = { { .hw = &pll_sys_desc.hw }, }; -static struct rp1_clk_desc clk_sys_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_sys", - clk_sys_parents, - &rp1_clk_ops, - CLK_IS_CRITICAL - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 3, - .num_aux_parents = 0, - .ctrl_reg = CLK_SYS_CTRL, - .div_int_reg = CLK_SYS_DIV_INT, - .sel_reg = CLK_SYS_SEL, - .div_int_max = DIV_INT_24BIT_MAX, - .max_freq = 200 * HZ_PER_MHZ, - .fc0_src = FC_NUM(0, 4), - .clk_src_mask = 0x3, - ) -); +static struct rp1_clk_desc clk_sys_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_sys", clk_sys_parents, &rp1_clk_ops, + CLK_IS_CRITICAL), + CLK_DATA(rp1_clock_data, .num_std_parents = 3, + .num_aux_parents = 0, .ctrl_reg = CLK_SYS_CTRL, + .div_int_reg = CLK_SYS_DIV_INT, + .sel_reg = CLK_SYS_SEL, + .div_int_max = DIV_INT_24BIT_MAX, + .max_freq = 200 * HZ_PER_MHZ, + .fc0_src = FC_NUM(0, 4), .clk_src_mask = 0x3, )); -static struct rp1_clk_desc pll_sys_pri_ph_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_sys_pri_ph", - (const struct clk_parent_data[]) { - { .hw = &pll_sys_desc.hw } - }, - &rp1_pll_ph_ops, - 0 - ), - CLK_DATA(rp1_pll_ph_data, - .ph_reg = PLL_SYS_PRIM, - .fixed_divider = 2, - .phase = RP1_PLL_PHASE_0, - .fc0_src = FC_NUM(1, 2), - ) -); +static struct rp1_clk_desc pll_sys_pri_ph_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_sys_pri_ph", + (const struct clk_parent_data[]){ + { .hw = &pll_sys_desc.hw } }, + &rp1_pll_ph_ops, 0), + CLK_DATA(rp1_pll_ph_data, .ph_reg = PLL_SYS_PRIM, + .fixed_divider = 2, .phase = RP1_PLL_PHASE_0, + .fc0_src = FC_NUM(1, 2), )); -static struct rp1_clk_desc pll_audio_pri_ph_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_audio_pri_ph", - (const struct clk_parent_data[]) { - { .hw = &pll_audio_desc.hw } - }, - &rp1_pll_ph_ops, - 0 - ), - CLK_DATA(rp1_pll_ph_data, - .ph_reg = PLL_AUDIO_PRIM, - .fixed_divider = 2, - .phase = RP1_PLL_PHASE_0, - .fc0_src = FC_NUM(5, 1), - ) -); +static struct rp1_clk_desc pll_audio_pri_ph_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_audio_pri_ph", + (const struct clk_parent_data[]){ + { .hw = &pll_audio_desc.hw } }, + &rp1_pll_ph_ops, 0), + CLK_DATA(rp1_pll_ph_data, .ph_reg = PLL_AUDIO_PRIM, + .fixed_divider = 2, .phase = RP1_PLL_PHASE_0, + .fc0_src = FC_NUM(5, 1), )); -static struct rp1_clk_desc pll_video_pri_ph_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_video_pri_ph", - (const struct clk_parent_data[]) { - { .hw = &pll_video_desc.hw } - }, - &rp1_pll_ph_ops, - 0 - ), - CLK_DATA(rp1_pll_ph_data, - .ph_reg = PLL_VIDEO_PRIM, - .fixed_divider = 2, - .phase = RP1_PLL_PHASE_0, - .fc0_src = FC_NUM(4, 3), - ) -); +static struct rp1_clk_desc pll_video_pri_ph_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_video_pri_ph", + (const struct clk_parent_data[]){ + { .hw = &pll_video_desc.hw } }, + &rp1_pll_ph_ops, 0), + CLK_DATA(rp1_pll_ph_data, .ph_reg = PLL_VIDEO_PRIM, + .fixed_divider = 2, .phase = RP1_PLL_PHASE_0, + .fc0_src = FC_NUM(4, 3), )); -static struct rp1_clk_desc pll_audio_sec_desc = REGISTER_PLL_DIV( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_audio_sec", - (const struct clk_parent_data[]) { - { .hw = &pll_audio_core_desc.hw } - }, - &rp1_pll_divider_ops, - 0 - ), - CLK_DATA(rp1_pll_data, - .ctrl_reg = PLL_AUDIO_SEC, - .fc0_src = FC_NUM(6, 2), - ) -); +static struct rp1_clk_desc pll_audio_sec_desc = + REGISTER_PLL_DIV(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_audio_sec", + (const struct clk_parent_data[]){ + { .hw = &pll_audio_core_desc.hw } }, + &rp1_pll_divider_ops, 0), + CLK_DATA(rp1_pll_data, .ctrl_reg = PLL_AUDIO_SEC, + .fc0_src = FC_NUM(6, 2), )); -static struct rp1_clk_desc pll_audio_tern_desc = REGISTER_PLL_DIV( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_audio_tern", - (const struct clk_parent_data[]) { - { .hw = &pll_audio_core_desc.hw } - }, - &rp1_pll_divider_ops, - 0 - ), - CLK_DATA(rp1_pll_data, - .ctrl_reg = PLL_AUDIO_TERN, - .fc0_src = FC_NUM(6, 2), - ) -); +static struct rp1_clk_desc pll_audio_tern_desc = + REGISTER_PLL_DIV(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_audio_tern", + (const struct clk_parent_data[]){ + { .hw = &pll_audio_core_desc.hw } }, + &rp1_pll_divider_ops, 0), + CLK_DATA(rp1_pll_data, .ctrl_reg = PLL_AUDIO_TERN, + .fc0_src = FC_NUM(6, 2), )); -static struct rp1_clk_desc clk_slow_sys_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_slow_sys", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_clk_ops, - CLK_IS_CRITICAL - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 1, - .num_aux_parents = 0, - .ctrl_reg = CLK_SLOW_SYS_CTRL, - .div_int_reg = CLK_SLOW_SYS_DIV_INT, - .sel_reg = CLK_SLOW_SYS_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 50 * HZ_PER_MHZ, - .fc0_src = FC_NUM(1, 4), - .clk_src_mask = 0x1, - ) -); +static struct rp1_clk_desc clk_slow_sys_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_slow_sys", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_clk_ops, CLK_IS_CRITICAL), + CLK_DATA(rp1_clock_data, .num_std_parents = 1, + .num_aux_parents = 0, + .ctrl_reg = CLK_SLOW_SYS_CTRL, + .div_int_reg = CLK_SLOW_SYS_DIV_INT, + .sel_reg = CLK_SLOW_SYS_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(1, 4), .clk_src_mask = 0x1, )); static const struct clk_parent_data clk_dma_parents[] = { { .hw = &pll_sys_pri_ph_desc.hw }, @@ -1613,24 +1517,16 @@ static const struct clk_parent_data clk_dma_parents[] = { { .index = 0 }, }; -static struct rp1_clk_desc clk_dma_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_dma", - clk_dma_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 3, - .ctrl_reg = CLK_DMA_CTRL, - .div_int_reg = CLK_DMA_DIV_INT, - .sel_reg = CLK_DMA_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 100 * HZ_PER_MHZ, - .fc0_src = FC_NUM(2, 2), - ) -); +static struct rp1_clk_desc clk_dma_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_dma", clk_dma_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 3, .ctrl_reg = CLK_DMA_CTRL, + .div_int_reg = CLK_DMA_DIV_INT, + .sel_reg = CLK_DMA_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(2, 2), )); static const struct clk_parent_data clk_uart_parents[] = { { .hw = &pll_sys_pri_ph_desc.hw }, @@ -1638,24 +1534,16 @@ static const struct clk_parent_data clk_uart_parents[] = { { .index = 0 }, }; -static struct rp1_clk_desc clk_uart_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_uart", - clk_uart_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 3, - .ctrl_reg = CLK_UART_CTRL, - .div_int_reg = CLK_UART_DIV_INT, - .sel_reg = CLK_UART_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 100 * HZ_PER_MHZ, - .fc0_src = FC_NUM(6, 7), - ) -); +static struct rp1_clk_desc clk_uart_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_uart", clk_uart_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 3, .ctrl_reg = CLK_UART_CTRL, + .div_int_reg = CLK_UART_DIV_INT, + .sel_reg = CLK_UART_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(6, 7), )); static const struct clk_parent_data clk_pwm0_parents[] = { { .index = -1 }, @@ -1663,25 +1551,17 @@ static const struct clk_parent_data clk_pwm0_parents[] = { { .index = 0 }, }; -static struct rp1_clk_desc clk_pwm0_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_pwm0", - clk_pwm0_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 3, - .ctrl_reg = CLK_PWM0_CTRL, - .div_int_reg = CLK_PWM0_DIV_INT, - .div_frac_reg = CLK_PWM0_DIV_FRAC, - .sel_reg = CLK_PWM0_SEL, - .div_int_max = DIV_INT_16BIT_MAX, - .max_freq = 76800 * HZ_PER_KHZ, - .fc0_src = FC_NUM(0, 5), - ) -); +static struct rp1_clk_desc clk_pwm0_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_pwm0", clk_pwm0_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 3, .ctrl_reg = CLK_PWM0_CTRL, + .div_int_reg = CLK_PWM0_DIV_INT, + .div_frac_reg = CLK_PWM0_DIV_FRAC, + .sel_reg = CLK_PWM0_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 76800 * HZ_PER_KHZ, + .fc0_src = FC_NUM(0, 5), )); static const struct clk_parent_data clk_pwm1_parents[] = { { .index = -1 }, @@ -1689,52 +1569,36 @@ static const struct clk_parent_data clk_pwm1_parents[] = { { .index = 0 }, }; -static struct rp1_clk_desc clk_pwm1_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_pwm1", - clk_pwm1_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 3, - .ctrl_reg = CLK_PWM1_CTRL, - .div_int_reg = CLK_PWM1_DIV_INT, - .div_frac_reg = CLK_PWM1_DIV_FRAC, - .sel_reg = CLK_PWM1_SEL, - .div_int_max = DIV_INT_16BIT_MAX, - .max_freq = 76800 * HZ_PER_KHZ, - .fc0_src = FC_NUM(1, 5), - ) -); +static struct rp1_clk_desc clk_pwm1_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_pwm1", clk_pwm1_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 3, .ctrl_reg = CLK_PWM1_CTRL, + .div_int_reg = CLK_PWM1_DIV_INT, + .div_frac_reg = CLK_PWM1_DIV_FRAC, + .sel_reg = CLK_PWM1_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 76800 * HZ_PER_KHZ, + .fc0_src = FC_NUM(1, 5), )); static const struct clk_parent_data clk_audio_in_parents[] = { - { .index = -1 }, - { .index = -1 }, - { .index = -1 }, - { .hw = &pll_video_sec_desc.hw }, + { .index = -1 }, { .index = -1 }, + { .index = -1 }, { .hw = &pll_video_sec_desc.hw }, { .index = 0 }, }; -static struct rp1_clk_desc clk_audio_in_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_audio_in", - clk_audio_in_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 5, - .ctrl_reg = CLK_AUDIO_IN_CTRL, - .div_int_reg = CLK_AUDIO_IN_DIV_INT, - .sel_reg = CLK_AUDIO_IN_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 76800 * HZ_PER_KHZ, - .fc0_src = FC_NUM(2, 5), - ) -); +static struct rp1_clk_desc clk_audio_in_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA("clk_audio_in", + clk_audio_in_parents, + &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 5, + .ctrl_reg = CLK_AUDIO_IN_CTRL, + .div_int_reg = CLK_AUDIO_IN_DIV_INT, + .sel_reg = CLK_AUDIO_IN_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 76800 * HZ_PER_KHZ, + .fc0_src = FC_NUM(2, 5), )); static const struct clk_parent_data clk_audio_out_parents[] = { { .index = -1 }, @@ -1743,24 +1607,18 @@ static const struct clk_parent_data clk_audio_out_parents[] = { { .index = 0 }, }; -static struct rp1_clk_desc clk_audio_out_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_audio_out", - clk_audio_out_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 4, - .ctrl_reg = CLK_AUDIO_OUT_CTRL, - .div_int_reg = CLK_AUDIO_OUT_DIV_INT, - .sel_reg = CLK_AUDIO_OUT_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 153600 * HZ_PER_KHZ, - .fc0_src = FC_NUM(3, 5), - ) -); +static struct rp1_clk_desc clk_audio_out_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA("clk_audio_out", + clk_audio_out_parents, + &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 4, + .ctrl_reg = CLK_AUDIO_OUT_CTRL, + .div_int_reg = CLK_AUDIO_OUT_DIV_INT, + .sel_reg = CLK_AUDIO_OUT_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 153600 * HZ_PER_KHZ, + .fc0_src = FC_NUM(3, 5), )); static const struct clk_parent_data clk_i2s_parents[] = { { .index = 0 }, @@ -1768,122 +1626,87 @@ static const struct clk_parent_data clk_i2s_parents[] = { { .hw = &pll_audio_sec_desc.hw }, }; -static struct rp1_clk_desc clk_i2s_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_i2s", - clk_i2s_parents, - &rp1_clk_ops, - CLK_SET_RATE_PARENT - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 3, - .ctrl_reg = CLK_I2S_CTRL, - .div_int_reg = CLK_I2S_DIV_INT, - .sel_reg = CLK_I2S_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 50 * HZ_PER_MHZ, - .fc0_src = FC_NUM(4, 4), - ) -); +static struct rp1_clk_desc clk_i2s_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_i2s", clk_i2s_parents, &rp1_clk_ops, + CLK_SET_RATE_PARENT), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 3, .ctrl_reg = CLK_I2S_CTRL, + .div_int_reg = CLK_I2S_DIV_INT, + .sel_reg = CLK_I2S_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(4, 4), )); -static struct rp1_clk_desc clk_mipi0_cfg_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_mipi0_cfg", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 1, - .ctrl_reg = CLK_MIPI0_CFG_CTRL, - .div_int_reg = CLK_MIPI0_CFG_DIV_INT, - .sel_reg = CLK_MIPI0_CFG_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 50 * HZ_PER_MHZ, - .fc0_src = FC_NUM(4, 5), - ) -); +static struct rp1_clk_desc clk_mipi0_cfg_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_mipi0_cfg", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_MIPI0_CFG_CTRL, + .div_int_reg = CLK_MIPI0_CFG_DIV_INT, + .sel_reg = CLK_MIPI0_CFG_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(4, 5), )); -static struct rp1_clk_desc clk_mipi1_cfg_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_mipi1_cfg", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 1, - .ctrl_reg = CLK_MIPI1_CFG_CTRL, - .div_int_reg = CLK_MIPI1_CFG_DIV_INT, - .sel_reg = CLK_MIPI1_CFG_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 50 * HZ_PER_MHZ, - .fc0_src = FC_NUM(5, 6), - .clk_src_mask = 0x1, - ) -); +static struct rp1_clk_desc clk_mipi1_cfg_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_mipi1_cfg", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_MIPI1_CFG_CTRL, + .div_int_reg = CLK_MIPI1_CFG_DIV_INT, + .sel_reg = CLK_MIPI1_CFG_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(5, 6), .clk_src_mask = 0x1, )); -static struct rp1_clk_desc clk_adc_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_adc", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 1, - .ctrl_reg = CLK_ADC_CTRL, - .div_int_reg = CLK_ADC_DIV_INT, - .sel_reg = CLK_ADC_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 50 * HZ_PER_MHZ, - .fc0_src = FC_NUM(5, 5), - ) -); +static struct rp1_clk_desc clk_adc_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_adc", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 1, .ctrl_reg = CLK_ADC_CTRL, + .div_int_reg = CLK_ADC_DIV_INT, + .sel_reg = CLK_ADC_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(5, 5), )); -static struct rp1_clk_desc clk_sdio_timer_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_sdio_timer", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 1, - .ctrl_reg = CLK_SDIO_TIMER_CTRL, - .div_int_reg = CLK_SDIO_TIMER_DIV_INT, - .sel_reg = CLK_SDIO_TIMER_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 50 * HZ_PER_MHZ, - .fc0_src = FC_NUM(3, 4), - ) -); +static struct rp1_clk_desc clk_sdio_timer_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_sdio_timer", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_SDIO_TIMER_CTRL, + .div_int_reg = CLK_SDIO_TIMER_DIV_INT, + .sel_reg = CLK_SDIO_TIMER_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(3, 4), )); -static struct rp1_clk_desc clk_sdio_alt_src_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_sdio_alt_src", - (const struct clk_parent_data[]) { - { .hw = &pll_sys_desc.hw } - }, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 1, - .ctrl_reg = CLK_SDIO_ALT_SRC_CTRL, - .div_int_reg = CLK_SDIO_ALT_SRC_DIV_INT, - .sel_reg = CLK_SDIO_ALT_SRC_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 200 * HZ_PER_MHZ, - .fc0_src = FC_NUM(5, 4), - ) -); +static struct rp1_clk_desc clk_sdio_alt_src_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_sdio_alt_src", + (const struct clk_parent_data[]){ + { .hw = &pll_sys_desc.hw } }, + &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_SDIO_ALT_SRC_CTRL, + .div_int_reg = CLK_SDIO_ALT_SRC_DIV_INT, + .sel_reg = CLK_SDIO_ALT_SRC_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 200 * HZ_PER_MHZ, + .fc0_src = FC_NUM(5, 4), )); static const struct clk_parent_data clk_dpi_parents[] = { { .hw = &pll_sys_desc.hw }, @@ -1897,23 +1720,17 @@ static const struct clk_parent_data clk_dpi_parents[] = { }; static struct rp1_clk_desc clk_dpi_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_dpi", - clk_dpi_parents, - &rp1_clk_ops, - CLK_SET_RATE_NO_REPARENT /* Let DPI driver set parent */ - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 8, - .ctrl_reg = VIDEO_CLK_DPI_CTRL, - .div_int_reg = VIDEO_CLK_DPI_DIV_INT, - .sel_reg = VIDEO_CLK_DPI_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 200 * HZ_PER_MHZ, - .fc0_src = FC_NUM(1, 6), - ) -); + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_dpi", clk_dpi_parents, &rp1_clk_ops, + CLK_SET_RATE_NO_REPARENT /* Let DPI driver set parent */ + ), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 8, .ctrl_reg = VIDEO_CLK_DPI_CTRL, + .div_int_reg = VIDEO_CLK_DPI_DIV_INT, + .sel_reg = VIDEO_CLK_DPI_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 200 * HZ_PER_MHZ, + .fc0_src = FC_NUM(1, 6), )); static const struct clk_parent_data clk_gp0_parents[] = { { .index = 0 }, @@ -1934,26 +1751,18 @@ static const struct clk_parent_data clk_gp0_parents[] = { { .hw = &clk_sys_desc.hw }, }; -static struct rp1_clk_desc clk_gp0_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_gp0", - clk_gp0_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 16, - .oe_mask = BIT(0), - .ctrl_reg = CLK_GP0_CTRL, - .div_int_reg = CLK_GP0_DIV_INT, - .div_frac_reg = CLK_GP0_DIV_FRAC, - .sel_reg = CLK_GP0_SEL, - .div_int_max = DIV_INT_16BIT_MAX, - .max_freq = 100 * HZ_PER_MHZ, - .fc0_src = FC_NUM(0, 1), - ) -); +static struct rp1_clk_desc clk_gp0_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp0", clk_gp0_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 16, .oe_mask = BIT(0), + .ctrl_reg = CLK_GP0_CTRL, + .div_int_reg = CLK_GP0_DIV_INT, + .div_frac_reg = CLK_GP0_DIV_FRAC, + .sel_reg = CLK_GP0_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(0, 1), )); static const struct clk_parent_data clk_gp1_parents[] = { { .hw = &clk_sdio_timer_desc.hw }, @@ -1974,52 +1783,34 @@ static const struct clk_parent_data clk_gp1_parents[] = { { .index = -1 }, }; -static struct rp1_clk_desc clk_gp1_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_gp1", - clk_gp1_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 16, - .oe_mask = BIT(1), - .ctrl_reg = CLK_GP1_CTRL, - .div_int_reg = CLK_GP1_DIV_INT, - .div_frac_reg = CLK_GP1_DIV_FRAC, - .sel_reg = CLK_GP1_SEL, - .div_int_max = DIV_INT_16BIT_MAX, - .max_freq = 100 * HZ_PER_MHZ, - .fc0_src = FC_NUM(1, 1), - ) -); +static struct rp1_clk_desc clk_gp1_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp1", clk_gp1_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 16, .oe_mask = BIT(1), + .ctrl_reg = CLK_GP1_CTRL, + .div_int_reg = CLK_GP1_DIV_INT, + .div_frac_reg = CLK_GP1_DIV_FRAC, + .sel_reg = CLK_GP1_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(1, 1), )); -static struct rp1_clk_desc clksrc_mipi0_dsi_byteclk_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clksrc_mipi0_dsi_byteclk", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_varsrc_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 1, - .num_aux_parents = 0, - ) -); +static struct rp1_clk_desc clksrc_mipi0_dsi_byteclk_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clksrc_mipi0_dsi_byteclk", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_varsrc_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 1, + .num_aux_parents = 0, )); -static struct rp1_clk_desc clksrc_mipi1_dsi_byteclk_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clksrc_mipi1_dsi_byteclk", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_varsrc_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 1, - .num_aux_parents = 0, - ) -); +static struct rp1_clk_desc clksrc_mipi1_dsi_byteclk_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clksrc_mipi1_dsi_byteclk", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_varsrc_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 1, + .num_aux_parents = 0, )); static const struct clk_parent_data clk_mipi0_dpi_parents[] = { { .hw = &pll_sys_desc.hw }, @@ -2033,24 +1824,19 @@ static const struct clk_parent_data clk_mipi0_dpi_parents[] = { }; static struct rp1_clk_desc clk_mipi0_dpi_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_mipi0_dpi", - clk_mipi0_dpi_parents, - &rp1_clk_ops, - CLK_SET_RATE_NO_REPARENT /* Let DSI driver set parent */ - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 8, - .ctrl_reg = VIDEO_CLK_MIPI0_DPI_CTRL, - .div_int_reg = VIDEO_CLK_MIPI0_DPI_DIV_INT, - .div_frac_reg = VIDEO_CLK_MIPI0_DPI_DIV_FRAC, - .sel_reg = VIDEO_CLK_MIPI0_DPI_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 200 * HZ_PER_MHZ, - .fc0_src = FC_NUM(2, 6), - ) -); + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_mipi0_dpi", clk_mipi0_dpi_parents, &rp1_clk_ops, + CLK_SET_RATE_NO_REPARENT /* Let DSI driver set parent */ + ), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 8, + .ctrl_reg = VIDEO_CLK_MIPI0_DPI_CTRL, + .div_int_reg = VIDEO_CLK_MIPI0_DPI_DIV_INT, + .div_frac_reg = VIDEO_CLK_MIPI0_DPI_DIV_FRAC, + .sel_reg = VIDEO_CLK_MIPI0_DPI_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 200 * HZ_PER_MHZ, + .fc0_src = FC_NUM(2, 6), )); static const struct clk_parent_data clk_mipi1_dpi_parents[] = { { .hw = &pll_sys_desc.hw }, @@ -2064,24 +1850,19 @@ static const struct clk_parent_data clk_mipi1_dpi_parents[] = { }; static struct rp1_clk_desc clk_mipi1_dpi_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_mipi1_dpi", - clk_mipi1_dpi_parents, - &rp1_clk_ops, - CLK_SET_RATE_NO_REPARENT /* Let DSI driver set parent */ - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 8, - .ctrl_reg = VIDEO_CLK_MIPI1_DPI_CTRL, - .div_int_reg = VIDEO_CLK_MIPI1_DPI_DIV_INT, - .div_frac_reg = VIDEO_CLK_MIPI1_DPI_DIV_FRAC, - .sel_reg = VIDEO_CLK_MIPI1_DPI_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 200 * HZ_PER_MHZ, - .fc0_src = FC_NUM(3, 6), - ) -); + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_mipi1_dpi", clk_mipi1_dpi_parents, &rp1_clk_ops, + CLK_SET_RATE_NO_REPARENT /* Let DSI driver set parent */ + ), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 8, + .ctrl_reg = VIDEO_CLK_MIPI1_DPI_CTRL, + .div_int_reg = VIDEO_CLK_MIPI1_DPI_DIV_INT, + .div_frac_reg = VIDEO_CLK_MIPI1_DPI_DIV_FRAC, + .sel_reg = VIDEO_CLK_MIPI1_DPI_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 200 * HZ_PER_MHZ, + .fc0_src = FC_NUM(3, 6), )); static const struct clk_parent_data clk_gp2_parents[] = { { .hw = &clk_sdio_alt_src_desc.hw }, @@ -2102,26 +1883,18 @@ static const struct clk_parent_data clk_gp2_parents[] = { { .hw = &clk_sys_desc.hw }, }; -static struct rp1_clk_desc clk_gp2_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_gp2", - clk_gp2_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 16, - .oe_mask = BIT(2), - .ctrl_reg = CLK_GP2_CTRL, - .div_int_reg = CLK_GP2_DIV_INT, - .div_frac_reg = CLK_GP2_DIV_FRAC, - .sel_reg = CLK_GP2_SEL, - .div_int_max = DIV_INT_16BIT_MAX, - .max_freq = 100 * HZ_PER_MHZ, - .fc0_src = FC_NUM(2, 1), - ) -); +static struct rp1_clk_desc clk_gp2_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp2", clk_gp2_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 16, .oe_mask = BIT(2), + .ctrl_reg = CLK_GP2_CTRL, + .div_int_reg = CLK_GP2_DIV_INT, + .div_frac_reg = CLK_GP2_DIV_FRAC, + .sel_reg = CLK_GP2_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(2, 1), )); static const struct clk_parent_data clk_gp3_parents[] = { { .index = 0 }, @@ -2142,26 +1915,18 @@ static const struct clk_parent_data clk_gp3_parents[] = { { .index = -1 }, }; -static struct rp1_clk_desc clk_gp3_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_gp3", - clk_gp3_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 16, - .oe_mask = BIT(3), - .ctrl_reg = CLK_GP3_CTRL, - .div_int_reg = CLK_GP3_DIV_INT, - .div_frac_reg = CLK_GP3_DIV_FRAC, - .sel_reg = CLK_GP3_SEL, - .div_int_max = DIV_INT_16BIT_MAX, - .max_freq = 100 * HZ_PER_MHZ, - .fc0_src = FC_NUM(3, 1), - ) -); +static struct rp1_clk_desc clk_gp3_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp3", clk_gp3_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 16, .oe_mask = BIT(3), + .ctrl_reg = CLK_GP3_CTRL, + .div_int_reg = CLK_GP3_DIV_INT, + .div_frac_reg = CLK_GP3_DIV_FRAC, + .sel_reg = CLK_GP3_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(3, 1), )); static const struct clk_parent_data clk_gp4_parents[] = { { .index = 0 }, @@ -2182,26 +1947,18 @@ static const struct clk_parent_data clk_gp4_parents[] = { { .hw = &clk_sys_desc.hw }, }; -static struct rp1_clk_desc clk_gp4_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_gp4", - clk_gp4_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 16, - .oe_mask = BIT(4), - .ctrl_reg = CLK_GP4_CTRL, - .div_int_reg = CLK_GP4_DIV_INT, - .div_frac_reg = CLK_GP4_DIV_FRAC, - .sel_reg = CLK_GP4_SEL, - .div_int_max = DIV_INT_16BIT_MAX, - .max_freq = 100 * HZ_PER_MHZ, - .fc0_src = FC_NUM(4, 1), - ) -); +static struct rp1_clk_desc clk_gp4_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp4", clk_gp4_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 16, .oe_mask = BIT(4), + .ctrl_reg = CLK_GP4_CTRL, + .div_int_reg = CLK_GP4_DIV_INT, + .div_frac_reg = CLK_GP4_DIV_FRAC, + .sel_reg = CLK_GP4_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(4, 1), )); static const struct clk_parent_data clk_vec_parents[] = { { .hw = &pll_sys_pri_ph_desc.hw }, @@ -2215,23 +1972,17 @@ static const struct clk_parent_data clk_vec_parents[] = { }; static struct rp1_clk_desc clk_vec_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_vec", - clk_vec_parents, - &rp1_clk_ops, - CLK_SET_RATE_NO_REPARENT /* Let VEC driver set parent */ - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 8, - .ctrl_reg = VIDEO_CLK_VEC_CTRL, - .div_int_reg = VIDEO_CLK_VEC_DIV_INT, - .sel_reg = VIDEO_CLK_VEC_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 108 * HZ_PER_MHZ, - .fc0_src = FC_NUM(0, 6), - ) -); + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_vec", clk_vec_parents, &rp1_clk_ops, + CLK_SET_RATE_NO_REPARENT /* Let VEC driver set parent */ + ), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 8, .ctrl_reg = VIDEO_CLK_VEC_CTRL, + .div_int_reg = VIDEO_CLK_VEC_DIV_INT, + .sel_reg = VIDEO_CLK_VEC_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 108 * HZ_PER_MHZ, + .fc0_src = FC_NUM(0, 6), )); static const struct clk_parent_data clk_gp5_parents[] = { { .index = 0 }, @@ -2252,26 +2003,18 @@ static const struct clk_parent_data clk_gp5_parents[] = { { .index = -1 }, }; -static struct rp1_clk_desc clk_gp5_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_gp5", - clk_gp5_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 16, - .oe_mask = BIT(5), - .ctrl_reg = CLK_GP5_CTRL, - .div_int_reg = CLK_GP5_DIV_INT, - .div_frac_reg = CLK_GP5_DIV_FRAC, - .sel_reg = CLK_GP5_SEL, - .div_int_max = DIV_INT_16BIT_MAX, - .max_freq = 100 * HZ_PER_MHZ, - .fc0_src = FC_NUM(5, 1), - ) -); +static struct rp1_clk_desc clk_gp5_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp5", clk_gp5_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 16, .oe_mask = BIT(5), + .ctrl_reg = CLK_GP5_CTRL, + .div_int_reg = CLK_GP5_DIV_INT, + .div_frac_reg = CLK_GP5_DIV_FRAC, + .sel_reg = CLK_GP5_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(5, 1), )); static struct rp1_clk_desc *const clk_desc_array[] = { [RP1_PLL_SYS_CORE] = &pll_sys_core_desc, @@ -2346,9 +2089,11 @@ static const struct regmap_range rp1_reg_ranges[] = { regmap_reg_range(CLK_MIPI1_CFG_SEL, CLK_MIPI1_CFG_SEL), regmap_reg_range(CLK_PCIE_AUX_CTRL, CLK_PCIE_AUX_DIV_INT), regmap_reg_range(CLK_PCIE_AUX_SEL, CLK_PCIE_AUX_SEL), - regmap_reg_range(CLK_USBH0_MICROFRAME_CTRL, CLK_USBH0_MICROFRAME_DIV_INT), + regmap_reg_range(CLK_USBH0_MICROFRAME_CTRL, + CLK_USBH0_MICROFRAME_DIV_INT), regmap_reg_range(CLK_USBH0_MICROFRAME_SEL, CLK_USBH0_MICROFRAME_SEL), - regmap_reg_range(CLK_USBH1_MICROFRAME_CTRL, CLK_USBH1_MICROFRAME_DIV_INT), + regmap_reg_range(CLK_USBH1_MICROFRAME_CTRL, + CLK_USBH1_MICROFRAME_DIV_INT), regmap_reg_range(CLK_USBH1_MICROFRAME_SEL, CLK_USBH1_MICROFRAME_SEL), regmap_reg_range(CLK_USBH0_SUSPEND_CTRL, CLK_USBH0_SUSPEND_DIV_INT), regmap_reg_range(CLK_USBH0_SUSPEND_SEL, CLK_USBH0_SUSPEND_SEL), @@ -2412,8 +2157,8 @@ static int rp1_clk_probe(struct platform_device *pdev) if (IS_ERR(clockman->regs)) return PTR_ERR(clockman->regs); - clockman->regmap = devm_regmap_init_mmio(dev, clockman->regs, - &rp1_clk_regmap_cfg); + clockman->regmap = + devm_regmap_init_mmio(dev, clockman->regs, &rp1_clk_regmap_cfg); if (IS_ERR(clockman->regmap)) { dev_err_probe(dev, PTR_ERR(clockman->regmap), "could not init clock regmap\n"); |