diff options
Diffstat (limited to 'drivers/clk/clk-rp1.c')
| -rw-r--r-- | drivers/clk/clk-rp1.c | 1697 |
1 files changed, 721 insertions, 976 deletions
diff --git a/drivers/clk/clk-rp1.c b/drivers/clk/clk-rp1.c index fd144755b879..ab74f20d4e5b 100644 --- a/drivers/clk/clk-rp1.c +++ b/drivers/clk/clk-rp1.c @@ -15,259 +15,259 @@ #include <dt-bindings/clock/raspberrypi,rp1-clocks.h> -#define PLL_SYS_OFFSET 0x08000 -#define PLL_SYS_CS (PLL_SYS_OFFSET + 0x00) -#define PLL_SYS_PWR (PLL_SYS_OFFSET + 0x04) -#define PLL_SYS_FBDIV_INT (PLL_SYS_OFFSET + 0x08) -#define PLL_SYS_FBDIV_FRAC (PLL_SYS_OFFSET + 0x0c) -#define PLL_SYS_PRIM (PLL_SYS_OFFSET + 0x10) -#define PLL_SYS_SEC (PLL_SYS_OFFSET + 0x14) +#define PLL_SYS_OFFSET 0x08000 +#define PLL_SYS_CS (PLL_SYS_OFFSET + 0x00) +#define PLL_SYS_PWR (PLL_SYS_OFFSET + 0x04) +#define PLL_SYS_FBDIV_INT (PLL_SYS_OFFSET + 0x08) +#define PLL_SYS_FBDIV_FRAC (PLL_SYS_OFFSET + 0x0c) +#define PLL_SYS_PRIM (PLL_SYS_OFFSET + 0x10) +#define PLL_SYS_SEC (PLL_SYS_OFFSET + 0x14) -#define PLL_AUDIO_OFFSET 0x0c000 -#define PLL_AUDIO_CS (PLL_AUDIO_OFFSET + 0x00) -#define PLL_AUDIO_PWR (PLL_AUDIO_OFFSET + 0x04) -#define PLL_AUDIO_FBDIV_INT (PLL_AUDIO_OFFSET + 0x08) -#define PLL_AUDIO_FBDIV_FRAC (PLL_AUDIO_OFFSET + 0x0c) -#define PLL_AUDIO_PRIM (PLL_AUDIO_OFFSET + 0x10) -#define PLL_AUDIO_SEC (PLL_AUDIO_OFFSET + 0x14) -#define PLL_AUDIO_TERN (PLL_AUDIO_OFFSET + 0x18) +#define PLL_AUDIO_OFFSET 0x0c000 +#define PLL_AUDIO_CS (PLL_AUDIO_OFFSET + 0x00) +#define PLL_AUDIO_PWR (PLL_AUDIO_OFFSET + 0x04) +#define PLL_AUDIO_FBDIV_INT (PLL_AUDIO_OFFSET + 0x08) +#define PLL_AUDIO_FBDIV_FRAC (PLL_AUDIO_OFFSET + 0x0c) +#define PLL_AUDIO_PRIM (PLL_AUDIO_OFFSET + 0x10) +#define PLL_AUDIO_SEC (PLL_AUDIO_OFFSET + 0x14) +#define PLL_AUDIO_TERN (PLL_AUDIO_OFFSET + 0x18) -#define PLL_VIDEO_OFFSET 0x10000 -#define PLL_VIDEO_CS (PLL_VIDEO_OFFSET + 0x00) -#define PLL_VIDEO_PWR (PLL_VIDEO_OFFSET + 0x04) -#define PLL_VIDEO_FBDIV_INT (PLL_VIDEO_OFFSET + 0x08) -#define PLL_VIDEO_FBDIV_FRAC (PLL_VIDEO_OFFSET + 0x0c) -#define PLL_VIDEO_PRIM (PLL_VIDEO_OFFSET + 0x10) -#define PLL_VIDEO_SEC (PLL_VIDEO_OFFSET + 0x14) +#define PLL_VIDEO_OFFSET 0x10000 +#define PLL_VIDEO_CS (PLL_VIDEO_OFFSET + 0x00) +#define PLL_VIDEO_PWR (PLL_VIDEO_OFFSET + 0x04) +#define PLL_VIDEO_FBDIV_INT (PLL_VIDEO_OFFSET + 0x08) +#define PLL_VIDEO_FBDIV_FRAC (PLL_VIDEO_OFFSET + 0x0c) +#define PLL_VIDEO_PRIM (PLL_VIDEO_OFFSET + 0x10) +#define PLL_VIDEO_SEC (PLL_VIDEO_OFFSET + 0x14) -#define GPCLK_OE_CTRL 0x00000 +#define GPCLK_OE_CTRL 0x00000 -#define CLK_SYS_OFFSET 0x00014 -#define CLK_SYS_CTRL (CLK_SYS_OFFSET + 0x00) -#define CLK_SYS_DIV_INT (CLK_SYS_OFFSET + 0x04) -#define CLK_SYS_SEL (CLK_SYS_OFFSET + 0x0c) +#define CLK_SYS_OFFSET 0x00014 +#define CLK_SYS_CTRL (CLK_SYS_OFFSET + 0x00) +#define CLK_SYS_DIV_INT (CLK_SYS_OFFSET + 0x04) +#define CLK_SYS_SEL (CLK_SYS_OFFSET + 0x0c) -#define CLK_SLOW_OFFSET 0x00024 -#define CLK_SLOW_SYS_CTRL (CLK_SLOW_OFFSET + 0x00) -#define CLK_SLOW_SYS_DIV_INT (CLK_SLOW_OFFSET + 0x04) -#define CLK_SLOW_SYS_SEL (CLK_SLOW_OFFSET + 0x0c) +#define CLK_SLOW_OFFSET 0x00024 +#define CLK_SLOW_SYS_CTRL (CLK_SLOW_OFFSET + 0x00) +#define CLK_SLOW_SYS_DIV_INT (CLK_SLOW_OFFSET + 0x04) +#define CLK_SLOW_SYS_SEL (CLK_SLOW_OFFSET + 0x0c) -#define CLK_DMA_OFFSET 0x00044 -#define CLK_DMA_CTRL (CLK_DMA_OFFSET + 0x00) -#define CLK_DMA_DIV_INT (CLK_DMA_OFFSET + 0x04) -#define CLK_DMA_SEL (CLK_DMA_OFFSET + 0x0c) +#define CLK_DMA_OFFSET 0x00044 +#define CLK_DMA_CTRL (CLK_DMA_OFFSET + 0x00) +#define CLK_DMA_DIV_INT (CLK_DMA_OFFSET + 0x04) +#define CLK_DMA_SEL (CLK_DMA_OFFSET + 0x0c) -#define CLK_UART_OFFSET 0x00054 -#define CLK_UART_CTRL (CLK_UART_OFFSET + 0x00) -#define CLK_UART_DIV_INT (CLK_UART_OFFSET + 0x04) -#define CLK_UART_SEL (CLK_UART_OFFSET + 0x0c) +#define CLK_UART_OFFSET 0x00054 +#define CLK_UART_CTRL (CLK_UART_OFFSET + 0x00) +#define CLK_UART_DIV_INT (CLK_UART_OFFSET + 0x04) +#define CLK_UART_SEL (CLK_UART_OFFSET + 0x0c) -#define CLK_ETH_OFFSET 0x00064 -#define CLK_ETH_CTRL (CLK_ETH_OFFSET + 0x00) -#define CLK_ETH_DIV_INT (CLK_ETH_OFFSET + 0x04) -#define CLK_ETH_SEL (CLK_ETH_OFFSET + 0x0c) +#define CLK_ETH_OFFSET 0x00064 +#define CLK_ETH_CTRL (CLK_ETH_OFFSET + 0x00) +#define CLK_ETH_DIV_INT (CLK_ETH_OFFSET + 0x04) +#define CLK_ETH_SEL (CLK_ETH_OFFSET + 0x0c) -#define CLK_PWM0_OFFSET 0x00074 -#define CLK_PWM0_CTRL (CLK_PWM0_OFFSET + 0x00) -#define CLK_PWM0_DIV_INT (CLK_PWM0_OFFSET + 0x04) -#define CLK_PWM0_DIV_FRAC (CLK_PWM0_OFFSET + 0x08) -#define CLK_PWM0_SEL (CLK_PWM0_OFFSET + 0x0c) +#define CLK_PWM0_OFFSET 0x00074 +#define CLK_PWM0_CTRL (CLK_PWM0_OFFSET + 0x00) +#define CLK_PWM0_DIV_INT (CLK_PWM0_OFFSET + 0x04) +#define CLK_PWM0_DIV_FRAC (CLK_PWM0_OFFSET + 0x08) +#define CLK_PWM0_SEL (CLK_PWM0_OFFSET + 0x0c) -#define CLK_PWM1_OFFSET 0x00084 -#define CLK_PWM1_CTRL (CLK_PWM1_OFFSET + 0x00) -#define CLK_PWM1_DIV_INT (CLK_PWM1_OFFSET + 0x04) -#define CLK_PWM1_DIV_FRAC (CLK_PWM1_OFFSET + 0x08) -#define CLK_PWM1_SEL (CLK_PWM1_OFFSET + 0x0c) +#define CLK_PWM1_OFFSET 0x00084 +#define CLK_PWM1_CTRL (CLK_PWM1_OFFSET + 0x00) +#define CLK_PWM1_DIV_INT (CLK_PWM1_OFFSET + 0x04) +#define CLK_PWM1_DIV_FRAC (CLK_PWM1_OFFSET + 0x08) +#define CLK_PWM1_SEL (CLK_PWM1_OFFSET + 0x0c) -#define CLK_AUDIO_IN_OFFSET 0x00094 -#define CLK_AUDIO_IN_CTRL (CLK_AUDIO_IN_OFFSET + 0x00) -#define CLK_AUDIO_IN_DIV_INT (CLK_AUDIO_IN_OFFSET + 0x04) -#define CLK_AUDIO_IN_SEL (CLK_AUDIO_IN_OFFSET + 0x0c) +#define CLK_AUDIO_IN_OFFSET 0x00094 +#define CLK_AUDIO_IN_CTRL (CLK_AUDIO_IN_OFFSET + 0x00) +#define CLK_AUDIO_IN_DIV_INT (CLK_AUDIO_IN_OFFSET + 0x04) +#define CLK_AUDIO_IN_SEL (CLK_AUDIO_IN_OFFSET + 0x0c) -#define CLK_AUDIO_OUT_OFFSET 0x000a4 -#define CLK_AUDIO_OUT_CTRL (CLK_AUDIO_OUT_OFFSET + 0x00) -#define CLK_AUDIO_OUT_DIV_INT (CLK_AUDIO_OUT_OFFSET + 0x04) -#define CLK_AUDIO_OUT_SEL (CLK_AUDIO_OUT_OFFSET + 0x0c) +#define CLK_AUDIO_OUT_OFFSET 0x000a4 +#define CLK_AUDIO_OUT_CTRL (CLK_AUDIO_OUT_OFFSET + 0x00) +#define CLK_AUDIO_OUT_DIV_INT (CLK_AUDIO_OUT_OFFSET + 0x04) +#define CLK_AUDIO_OUT_SEL (CLK_AUDIO_OUT_OFFSET + 0x0c) -#define CLK_I2S_OFFSET 0x000b4 -#define CLK_I2S_CTRL (CLK_I2S_OFFSET + 0x00) -#define CLK_I2S_DIV_INT (CLK_I2S_OFFSET + 0x04) -#define CLK_I2S_SEL (CLK_I2S_OFFSET + 0x0c) +#define CLK_I2S_OFFSET 0x000b4 +#define CLK_I2S_CTRL (CLK_I2S_OFFSET + 0x00) +#define CLK_I2S_DIV_INT (CLK_I2S_OFFSET + 0x04) +#define CLK_I2S_SEL (CLK_I2S_OFFSET + 0x0c) -#define CLK_MIPI0_CFG_OFFSET 0x000c4 -#define CLK_MIPI0_CFG_CTRL (CLK_MIPI0_CFG_OFFSET + 0x00) -#define CLK_MIPI0_CFG_DIV_INT (CLK_MIPI0_CFG_OFFSET + 0x04) -#define CLK_MIPI0_CFG_SEL (CLK_MIPI0_CFG_OFFSET + 0x0c) +#define CLK_MIPI0_CFG_OFFSET 0x000c4 +#define CLK_MIPI0_CFG_CTRL (CLK_MIPI0_CFG_OFFSET + 0x00) +#define CLK_MIPI0_CFG_DIV_INT (CLK_MIPI0_CFG_OFFSET + 0x04) +#define CLK_MIPI0_CFG_SEL (CLK_MIPI0_CFG_OFFSET + 0x0c) -#define CLK_MIPI1_CFG_OFFSET 0x000d4 -#define CLK_MIPI1_CFG_CTRL (CLK_MIPI1_CFG_OFFSET + 0x00) -#define CLK_MIPI1_CFG_DIV_INT (CLK_MIPI1_CFG_OFFSET + 0x04) -#define CLK_MIPI1_CFG_SEL (CLK_MIPI1_CFG_OFFSET + 0x0c) +#define CLK_MIPI1_CFG_OFFSET 0x000d4 +#define CLK_MIPI1_CFG_CTRL (CLK_MIPI1_CFG_OFFSET + 0x00) +#define CLK_MIPI1_CFG_DIV_INT (CLK_MIPI1_CFG_OFFSET + 0x04) +#define CLK_MIPI1_CFG_SEL (CLK_MIPI1_CFG_OFFSET + 0x0c) -#define CLK_PCIE_AUX_OFFSET 0x000e4 -#define CLK_PCIE_AUX_CTRL (CLK_PCIE_AUX_OFFSET + 0x00) -#define CLK_PCIE_AUX_DIV_INT (CLK_PCIE_AUX_OFFSET + 0x04) -#define CLK_PCIE_AUX_SEL (CLK_PCIE_AUX_OFFSET + 0x0c) +#define CLK_PCIE_AUX_OFFSET 0x000e4 +#define CLK_PCIE_AUX_CTRL (CLK_PCIE_AUX_OFFSET + 0x00) +#define CLK_PCIE_AUX_DIV_INT (CLK_PCIE_AUX_OFFSET + 0x04) +#define CLK_PCIE_AUX_SEL (CLK_PCIE_AUX_OFFSET + 0x0c) -#define CLK_USBH0_MICROFRAME_OFFSET 0x000f4 -#define CLK_USBH0_MICROFRAME_CTRL (CLK_USBH0_MICROFRAME_OFFSET + 0x00) -#define CLK_USBH0_MICROFRAME_DIV_INT (CLK_USBH0_MICROFRAME_OFFSET + 0x04) -#define CLK_USBH0_MICROFRAME_SEL (CLK_USBH0_MICROFRAME_OFFSET + 0x0c) +#define CLK_USBH0_MICROFRAME_OFFSET 0x000f4 +#define CLK_USBH0_MICROFRAME_CTRL (CLK_USBH0_MICROFRAME_OFFSET + 0x00) +#define CLK_USBH0_MICROFRAME_DIV_INT (CLK_USBH0_MICROFRAME_OFFSET + 0x04) +#define CLK_USBH0_MICROFRAME_SEL (CLK_USBH0_MICROFRAME_OFFSET + 0x0c) -#define CLK_USBH1_MICROFRAME_OFFSET 0x00104 -#define CLK_USBH1_MICROFRAME_CTRL (CLK_USBH1_MICROFRAME_OFFSET + 0x00) -#define CLK_USBH1_MICROFRAME_DIV_INT (CLK_USBH1_MICROFRAME_OFFSET + 0x04) -#define CLK_USBH1_MICROFRAME_SEL (CLK_USBH1_MICROFRAME_OFFSET + 0x0c) +#define CLK_USBH1_MICROFRAME_OFFSET 0x00104 +#define CLK_USBH1_MICROFRAME_CTRL (CLK_USBH1_MICROFRAME_OFFSET + 0x00) +#define CLK_USBH1_MICROFRAME_DIV_INT (CLK_USBH1_MICROFRAME_OFFSET + 0x04) +#define CLK_USBH1_MICROFRAME_SEL (CLK_USBH1_MICROFRAME_OFFSET + 0x0c) -#define CLK_USBH0_SUSPEND_OFFSET 0x00114 -#define CLK_USBH0_SUSPEND_CTRL (CLK_USBH0_SUSPEND_OFFSET + 0x00) -#define CLK_USBH0_SUSPEND_DIV_INT (CLK_USBH0_SUSPEND_OFFSET + 0x04) -#define CLK_USBH0_SUSPEND_SEL (CLK_USBH0_SUSPEND_OFFSET + 0x0c) +#define CLK_USBH0_SUSPEND_OFFSET 0x00114 +#define CLK_USBH0_SUSPEND_CTRL (CLK_USBH0_SUSPEND_OFFSET + 0x00) +#define CLK_USBH0_SUSPEND_DIV_INT (CLK_USBH0_SUSPEND_OFFSET + 0x04) +#define CLK_USBH0_SUSPEND_SEL (CLK_USBH0_SUSPEND_OFFSET + 0x0c) -#define CLK_USBH1_SUSPEND_OFFSET 0x00124 -#define CLK_USBH1_SUSPEND_CTRL (CLK_USBH1_SUSPEND_OFFSET + 0x00) -#define CLK_USBH1_SUSPEND_DIV_INT (CLK_USBH1_SUSPEND_OFFSET + 0x04) -#define CLK_USBH1_SUSPEND_SEL (CLK_USBH1_SUSPEND_OFFSET + 0x0c) +#define CLK_USBH1_SUSPEND_OFFSET 0x00124 +#define CLK_USBH1_SUSPEND_CTRL (CLK_USBH1_SUSPEND_OFFSET + 0x00) +#define CLK_USBH1_SUSPEND_DIV_INT (CLK_USBH1_SUSPEND_OFFSET + 0x04) +#define CLK_USBH1_SUSPEND_SEL (CLK_USBH1_SUSPEND_OFFSET + 0x0c) -#define CLK_ETH_TSU_OFFSET 0x00134 -#define CLK_ETH_TSU_CTRL (CLK_ETH_TSU_OFFSET + 0x00) -#define CLK_ETH_TSU_DIV_INT (CLK_ETH_TSU_OFFSET + 0x04) -#define CLK_ETH_TSU_SEL (CLK_ETH_TSU_OFFSET + 0x0c) +#define CLK_ETH_TSU_OFFSET 0x00134 +#define CLK_ETH_TSU_CTRL (CLK_ETH_TSU_OFFSET + 0x00) +#define CLK_ETH_TSU_DIV_INT (CLK_ETH_TSU_OFFSET + 0x04) +#define CLK_ETH_TSU_SEL (CLK_ETH_TSU_OFFSET + 0x0c) -#define CLK_ADC_OFFSET 0x00144 -#define CLK_ADC_CTRL (CLK_ADC_OFFSET + 0x00) -#define CLK_ADC_DIV_INT (CLK_ADC_OFFSET + 0x04) -#define CLK_ADC_SEL (CLK_ADC_OFFSET + 0x0c) +#define CLK_ADC_OFFSET 0x00144 +#define CLK_ADC_CTRL (CLK_ADC_OFFSET + 0x00) +#define CLK_ADC_DIV_INT (CLK_ADC_OFFSET + 0x04) +#define CLK_ADC_SEL (CLK_ADC_OFFSET + 0x0c) -#define CLK_SDIO_TIMER_OFFSET 0x00154 -#define CLK_SDIO_TIMER_CTRL (CLK_SDIO_TIMER_OFFSET + 0x00) -#define CLK_SDIO_TIMER_DIV_INT (CLK_SDIO_TIMER_OFFSET + 0x04) -#define CLK_SDIO_TIMER_SEL (CLK_SDIO_TIMER_OFFSET + 0x0c) +#define CLK_SDIO_TIMER_OFFSET 0x00154 +#define CLK_SDIO_TIMER_CTRL (CLK_SDIO_TIMER_OFFSET + 0x00) +#define CLK_SDIO_TIMER_DIV_INT (CLK_SDIO_TIMER_OFFSET + 0x04) +#define CLK_SDIO_TIMER_SEL (CLK_SDIO_TIMER_OFFSET + 0x0c) -#define CLK_SDIO_ALT_SRC_OFFSET 0x00164 -#define CLK_SDIO_ALT_SRC_CTRL (CLK_SDIO_ALT_SRC_OFFSET + 0x00) -#define CLK_SDIO_ALT_SRC_DIV_INT (CLK_SDIO_ALT_SRC_OFFSET + 0x04) -#define CLK_SDIO_ALT_SRC_SEL (CLK_SDIO_ALT_SRC_OFFSET + 0x0c) +#define CLK_SDIO_ALT_SRC_OFFSET 0x00164 +#define CLK_SDIO_ALT_SRC_CTRL (CLK_SDIO_ALT_SRC_OFFSET + 0x00) +#define CLK_SDIO_ALT_SRC_DIV_INT (CLK_SDIO_ALT_SRC_OFFSET + 0x04) +#define CLK_SDIO_ALT_SRC_SEL (CLK_SDIO_ALT_SRC_OFFSET + 0x0c) -#define CLK_GP0_OFFSET 0x00174 -#define CLK_GP0_CTRL (CLK_GP0_OFFSET + 0x00) -#define CLK_GP0_DIV_INT (CLK_GP0_OFFSET + 0x04) -#define CLK_GP0_DIV_FRAC (CLK_GP0_OFFSET + 0x08) -#define CLK_GP0_SEL (CLK_GP0_OFFSET + 0x0c) +#define CLK_GP0_OFFSET 0x00174 +#define CLK_GP0_CTRL (CLK_GP0_OFFSET + 0x00) +#define CLK_GP0_DIV_INT (CLK_GP0_OFFSET + 0x04) +#define CLK_GP0_DIV_FRAC (CLK_GP0_OFFSET + 0x08) +#define CLK_GP0_SEL (CLK_GP0_OFFSET + 0x0c) -#define CLK_GP1_OFFSET 0x00184 -#define CLK_GP1_CTRL (CLK_GP1_OFFSET + 0x00) -#define CLK_GP1_DIV_INT (CLK_GP1_OFFSET + 0x04) -#define CLK_GP1_DIV_FRAC (CLK_GP1_OFFSET + 0x08) -#define CLK_GP1_SEL (CLK_GP1_OFFSET + 0x0c) +#define CLK_GP1_OFFSET 0x00184 +#define CLK_GP1_CTRL (CLK_GP1_OFFSET + 0x00) +#define CLK_GP1_DIV_INT (CLK_GP1_OFFSET + 0x04) +#define CLK_GP1_DIV_FRAC (CLK_GP1_OFFSET + 0x08) +#define CLK_GP1_SEL (CLK_GP1_OFFSET + 0x0c) -#define CLK_GP2_OFFSET 0x00194 -#define CLK_GP2_CTRL (CLK_GP2_OFFSET + 0x00) -#define CLK_GP2_DIV_INT (CLK_GP2_OFFSET + 0x04) -#define CLK_GP2_DIV_FRAC (CLK_GP2_OFFSET + 0x08) -#define CLK_GP2_SEL (CLK_GP2_OFFSET + 0x0c) +#define CLK_GP2_OFFSET 0x00194 +#define CLK_GP2_CTRL (CLK_GP2_OFFSET + 0x00) +#define CLK_GP2_DIV_INT (CLK_GP2_OFFSET + 0x04) +#define CLK_GP2_DIV_FRAC (CLK_GP2_OFFSET + 0x08) +#define CLK_GP2_SEL (CLK_GP2_OFFSET + 0x0c) -#define CLK_GP3_OFFSET 0x001a4 -#define CLK_GP3_CTRL (CLK_GP3_OFFSET + 0x00) -#define CLK_GP3_DIV_INT (CLK_GP3_OFFSET + 0x04) -#define CLK_GP3_DIV_FRAC (CLK_GP3_OFFSET + 0x08) -#define CLK_GP3_SEL (CLK_GP3_OFFSET + 0x0c) +#define CLK_GP3_OFFSET 0x001a4 +#define CLK_GP3_CTRL (CLK_GP3_OFFSET + 0x00) +#define CLK_GP3_DIV_INT (CLK_GP3_OFFSET + 0x04) +#define CLK_GP3_DIV_FRAC (CLK_GP3_OFFSET + 0x08) +#define CLK_GP3_SEL (CLK_GP3_OFFSET + 0x0c) -#define CLK_GP4_OFFSET 0x001b4 -#define CLK_GP4_CTRL (CLK_GP4_OFFSET + 0x00) -#define CLK_GP4_DIV_INT (CLK_GP4_OFFSET + 0x04) -#define CLK_GP4_DIV_FRAC (CLK_GP4_OFFSET + 0x08) -#define CLK_GP4_SEL (CLK_GP4_OFFSET + 0x0c) +#define CLK_GP4_OFFSET 0x001b4 +#define CLK_GP4_CTRL (CLK_GP4_OFFSET + 0x00) +#define CLK_GP4_DIV_INT (CLK_GP4_OFFSET + 0x04) +#define CLK_GP4_DIV_FRAC (CLK_GP4_OFFSET + 0x08) +#define CLK_GP4_SEL (CLK_GP4_OFFSET + 0x0c) -#define CLK_GP5_OFFSET 0x001c4 -#define CLK_GP5_CTRL (CLK_GP5_OFFSET + 0x00) -#define CLK_GP5_DIV_INT (CLK_GP5_OFFSET + 0x04) -#define CLK_GP5_DIV_FRAC (CLK_GP5_OFFSET + 0x08) -#define CLK_GP5_SEL (CLK_GP5_OFFSET + 0x0c) +#define CLK_GP5_OFFSET 0x001c4 +#define CLK_GP5_CTRL (CLK_GP5_OFFSET + 0x00) +#define CLK_GP5_DIV_INT (CLK_GP5_OFFSET + 0x04) +#define CLK_GP5_DIV_FRAC (CLK_GP5_OFFSET + 0x08) +#define CLK_GP5_SEL (CLK_GP5_OFFSET + 0x0c) -#define CLK_SYS_RESUS_CTRL 0x0020c +#define CLK_SYS_RESUS_CTRL 0x0020c -#define CLK_SLOW_SYS_RESUS_CTRL 0x00214 +#define CLK_SLOW_SYS_RESUS_CTRL 0x00214 -#define FC0_OFFSET 0x0021c -#define FC0_REF_KHZ (FC0_OFFSET + 0x00) -#define FC0_MIN_KHZ (FC0_OFFSET + 0x04) -#define FC0_MAX_KHZ (FC0_OFFSET + 0x08) -#define FC0_DELAY (FC0_OFFSET + 0x0c) -#define FC0_INTERVAL (FC0_OFFSET + 0x10) -#define FC0_SRC (FC0_OFFSET + 0x14) -#define FC0_STATUS (FC0_OFFSET + 0x18) -#define FC0_RESULT (FC0_OFFSET + 0x1c) -#define FC_SIZE 0x20 -#define FC_COUNT 8 -#define FC_NUM(idx, off) ((idx) * 32 + (off)) +#define FC0_OFFSET 0x0021c +#define FC0_REF_KHZ (FC0_OFFSET + 0x00) +#define FC0_MIN_KHZ (FC0_OFFSET + 0x04) +#define FC0_MAX_KHZ (FC0_OFFSET + 0x08) +#define FC0_DELAY (FC0_OFFSET + 0x0c) +#define FC0_INTERVAL (FC0_OFFSET + 0x10) +#define FC0_SRC (FC0_OFFSET + 0x14) +#define FC0_STATUS (FC0_OFFSET + 0x18) +#define FC0_RESULT (FC0_OFFSET + 0x1c) +#define FC_SIZE 0x20 +#define FC_COUNT 8 +#define FC_NUM(idx, off) ((idx) * 32 + (off)) -#define AUX_SEL 1 +#define AUX_SEL 1 -#define VIDEO_CLOCKS_OFFSET 0x4000 -#define VIDEO_CLK_VEC_CTRL (VIDEO_CLOCKS_OFFSET + 0x0000) -#define VIDEO_CLK_VEC_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0004) -#define VIDEO_CLK_VEC_SEL (VIDEO_CLOCKS_OFFSET + 0x000c) -#define VIDEO_CLK_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0010) -#define VIDEO_CLK_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0014) -#define VIDEO_CLK_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x001c) -#define VIDEO_CLK_MIPI0_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0020) -#define VIDEO_CLK_MIPI0_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0024) -#define VIDEO_CLK_MIPI0_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0028) -#define VIDEO_CLK_MIPI0_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x002c) -#define VIDEO_CLK_MIPI1_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0030) -#define VIDEO_CLK_MIPI1_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0034) -#define VIDEO_CLK_MIPI1_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0038) -#define VIDEO_CLK_MIPI1_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x003c) +#define VIDEO_CLOCKS_OFFSET 0x4000 +#define VIDEO_CLK_VEC_CTRL (VIDEO_CLOCKS_OFFSET + 0x0000) +#define VIDEO_CLK_VEC_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0004) +#define VIDEO_CLK_VEC_SEL (VIDEO_CLOCKS_OFFSET + 0x000c) +#define VIDEO_CLK_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0010) +#define VIDEO_CLK_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0014) +#define VIDEO_CLK_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x001c) +#define VIDEO_CLK_MIPI0_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0020) +#define VIDEO_CLK_MIPI0_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0024) +#define VIDEO_CLK_MIPI0_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0028) +#define VIDEO_CLK_MIPI0_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x002c) +#define VIDEO_CLK_MIPI1_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0030) +#define VIDEO_CLK_MIPI1_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0034) +#define VIDEO_CLK_MIPI1_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0038) +#define VIDEO_CLK_MIPI1_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x003c) -#define DIV_INT_8BIT_MAX GENMASK(7, 0) /* max divide for most clocks */ -#define DIV_INT_16BIT_MAX GENMASK(15, 0) /* max divide for GPx, PWM */ -#define DIV_INT_24BIT_MAX GENMASK(23, 0) /* max divide for CLK_SYS */ +#define DIV_INT_8BIT_MAX GENMASK(7, 0) /* max divide for most clocks */ +#define DIV_INT_16BIT_MAX GENMASK(15, 0) /* max divide for GPx, PWM */ +#define DIV_INT_24BIT_MAX GENMASK(23, 0) /* max divide for CLK_SYS */ -#define FC0_STATUS_DONE BIT(4) -#define FC0_STATUS_RUNNING BIT(8) -#define FC0_RESULT_FRAC_SHIFT 5 +#define FC0_STATUS_DONE BIT(4) +#define FC0_STATUS_RUNNING BIT(8) +#define FC0_RESULT_FRAC_SHIFT 5 -#define PLL_PRIM_DIV1_MASK GENMASK(18, 16) -#define PLL_PRIM_DIV2_MASK GENMASK(14, 12) +#define PLL_PRIM_DIV1_MASK GENMASK(18, 16) +#define PLL_PRIM_DIV2_MASK GENMASK(14, 12) -#define PLL_SEC_DIV_MASK GENMASK(12, 8) +#define PLL_SEC_DIV_MASK GENMASK(12, 8) -#define PLL_CS_LOCK BIT(31) -#define PLL_CS_REFDIV_MASK BIT(1) +#define PLL_CS_LOCK BIT(31) +#define PLL_CS_REFDIV_MASK BIT(1) -#define PLL_PWR_PD BIT(0) -#define PLL_PWR_DACPD BIT(1) -#define PLL_PWR_DSMPD BIT(2) -#define PLL_PWR_POSTDIVPD BIT(3) -#define PLL_PWR_4PHASEPD BIT(4) -#define PLL_PWR_VCOPD BIT(5) -#define PLL_PWR_MASK GENMASK(5, 0) +#define PLL_PWR_PD BIT(0) +#define PLL_PWR_DACPD BIT(1) +#define PLL_PWR_DSMPD BIT(2) +#define PLL_PWR_POSTDIVPD BIT(3) +#define PLL_PWR_4PHASEPD BIT(4) +#define PLL_PWR_VCOPD BIT(5) +#define PLL_PWR_MASK GENMASK(5, 0) -#define PLL_SEC_RST BIT(16) -#define PLL_SEC_IMPL BIT(31) +#define PLL_SEC_RST BIT(16) +#define PLL_SEC_IMPL BIT(31) /* PLL phase output for both PRI and SEC */ -#define PLL_PH_EN BIT(4) -#define PLL_PH_PHASE_SHIFT 0 +#define PLL_PH_EN BIT(4) +#define PLL_PH_PHASE_SHIFT 0 -#define RP1_PLL_PHASE_0 0 -#define RP1_PLL_PHASE_90 1 -#define RP1_PLL_PHASE_180 2 -#define RP1_PLL_PHASE_270 3 +#define RP1_PLL_PHASE_0 0 +#define RP1_PLL_PHASE_90 1 +#define RP1_PLL_PHASE_180 2 +#define RP1_PLL_PHASE_270 3 /* Clock fields for all clocks */ -#define CLK_CTRL_ENABLE BIT(11) -#define CLK_CTRL_AUXSRC_MASK GENMASK(9, 5) -#define CLK_CTRL_SRC_SHIFT 0 -#define CLK_DIV_FRAC_BITS 16 +#define CLK_CTRL_ENABLE BIT(11) +#define CLK_CTRL_AUXSRC_MASK GENMASK(9, 5) +#define CLK_CTRL_SRC_SHIFT 0 +#define CLK_DIV_FRAC_BITS 16 -#define LOCK_TIMEOUT_US 100000 -#define LOCK_POLL_DELAY_US 5 +#define LOCK_TIMEOUT_US 100000 +#define LOCK_POLL_DELAY_US 5 -#define MAX_CLK_PARENTS 16 +#define MAX_CLK_PARENTS 16 -#define PLL_DIV_INVALID 19 +#define PLL_DIV_INVALID 19 /* * Secondary PLL channel output divider table. * Divider values range from 8 to 19, where @@ -282,8 +282,8 @@ static const struct clk_div_table pll_sec_div_table[] = { { 0x05, PLL_DIV_INVALID }, { 0x06, PLL_DIV_INVALID }, { 0x07, PLL_DIV_INVALID }, - { 0x08, 8 }, - { 0x09, 9 }, + { 0x08, 8 }, + { 0x09, 9 }, { 0x0a, 10 }, { 0x0b, 11 }, { 0x0c, 12 }, @@ -373,8 +373,8 @@ static struct rp1_clk_desc *clk_audio; static struct rp1_clk_desc *clk_i2s; static struct clk_hw *clk_xosc; -static inline -void clockman_write(struct rp1_clockman *clockman, u32 reg, u32 val) +static inline void clockman_write(struct rp1_clockman *clockman, u32 reg, + u32 val) { regmap_write(clockman->regmap, reg, val); } @@ -390,7 +390,8 @@ static inline u32 clockman_read(struct rp1_clockman *clockman, u32 reg) static int rp1_pll_core_is_on(struct clk_hw *hw) { - struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clk_desc *pll_core = + container_of(hw, struct rp1_clk_desc, hw); struct rp1_clockman *clockman = pll_core->clockman; const struct rp1_pll_core_data *data = pll_core->data; u32 pwr = clockman_read(clockman, data->pwr_reg); @@ -400,7 +401,8 @@ static int rp1_pll_core_is_on(struct clk_hw *hw) static int rp1_pll_core_on(struct clk_hw *hw) { - struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clk_desc *pll_core = + container_of(hw, struct rp1_clk_desc, hw); struct rp1_clockman *clockman = pll_core->clockman; const struct rp1_pll_core_data *data = pll_core->data; u32 fbdiv_frac, val; @@ -423,8 +425,8 @@ static int rp1_pll_core_on(struct clk_hw *hw) /* Wait for the PLL to lock. */ ret = regmap_read_poll_timeout(clockman->regmap, data->cs_reg, val, - val & PLL_CS_LOCK, - LOCK_POLL_DELAY_US, LOCK_TIMEOUT_US); + val & PLL_CS_LOCK, LOCK_POLL_DELAY_US, + LOCK_TIMEOUT_US); if (ret) dev_err(clockman->dev, "%s: can't lock PLL\n", clk_hw_get_name(hw)); @@ -434,7 +436,8 @@ static int rp1_pll_core_on(struct clk_hw *hw) static void rp1_pll_core_off(struct clk_hw *hw) { - struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clk_desc *pll_core = + container_of(hw, struct rp1_clk_desc, hw); struct rp1_clockman *clockman = pll_core->clockman; const struct rp1_pll_core_data *data = pll_core->data; @@ -474,10 +477,11 @@ static inline unsigned long get_pll_core_divider(struct clk_hw *hw, return calc_rate; } -static int rp1_pll_core_set_rate(struct clk_hw *hw, - unsigned long rate, unsigned long parent_rate) +static int rp1_pll_core_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { - struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clk_desc *pll_core = + container_of(hw, struct rp1_clk_desc, hw); struct rp1_clockman *clockman = pll_core->clockman; const struct rp1_pll_core_data *data = pll_core->data; u32 fbdiv_int, fbdiv_frac; @@ -488,8 +492,7 @@ static int rp1_pll_core_set_rate(struct clk_hw *hw, clockman_write(clockman, data->fbdiv_frac_reg, 0); spin_unlock(&clockman->regs_lock); - get_pll_core_divider(hw, rate, parent_rate, - &fbdiv_int, &fbdiv_frac); + get_pll_core_divider(hw, rate, parent_rate, &fbdiv_int, &fbdiv_frac); spin_lock(&clockman->regs_lock); clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD); @@ -505,7 +508,7 @@ static int rp1_pll_core_set_rate(struct clk_hw *hw, /* Don't need to divide ref unless parent_rate > (output freq / 16) */ clockman_write(clockman, data->cs_reg, clockman_read(clockman, data->cs_reg) | - PLL_CS_REFDIV_MASK); + PLL_CS_REFDIV_MASK); spin_unlock(&clockman->regs_lock); return 0; @@ -514,7 +517,8 @@ static int rp1_pll_core_set_rate(struct clk_hw *hw, static unsigned long rp1_pll_core_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct rp1_clk_desc *pll_core = container_of(hw, struct rp1_clk_desc, hw); + struct rp1_clk_desc *pll_core = + container_of(hw, struct rp1_clk_desc, hw); struct rp1_clockman *clockman = pll_core->clockman; const struct rp1_pll_core_data *data = pll_core->data; u32 fbdiv_int, fbdiv_frac; @@ -538,8 +542,7 @@ static int rp1_pll_core_determine_rate(struct clk_hw *hw, u32 fbdiv_int, fbdiv_frac; req->rate = get_pll_core_divider(hw, req->rate, req->best_parent_rate, - &fbdiv_int, - &fbdiv_frac); + &fbdiv_int, &fbdiv_frac); return 0; } @@ -549,8 +552,8 @@ static void get_pll_prim_dividers(unsigned long rate, unsigned long parent_rate, { unsigned int div1, div2; unsigned int best_div1 = 7, best_div2 = 7; - unsigned long best_rate_diff = - abs_diff(DIV_ROUND_CLOSEST(parent_rate, best_div1 * best_div2), rate); + unsigned long best_rate_diff = abs_diff( + DIV_ROUND_CLOSEST(parent_rate, best_div1 * best_div2), rate); unsigned long rate_diff, calc_rate; for (div1 = 1; div1 <= 7; div1++) { @@ -575,8 +578,8 @@ done: *divider2 = best_div2; } -static int rp1_pll_set_rate(struct clk_hw *hw, - unsigned long rate, unsigned long parent_rate) +static int rp1_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { struct rp1_clk_desc *pll = container_of(hw, struct rp1_clk_desc, hw); struct rp1_clockman *clockman = pll->clockman; @@ -695,7 +698,8 @@ static int rp1_pll_ph_determine_rate(struct clk_hw *hw, static int rp1_pll_divider_is_on(struct clk_hw *hw) { - struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw); + struct rp1_clk_desc *divider = + container_of(hw, struct rp1_clk_desc, div.hw); struct rp1_clockman *clockman = divider->clockman; const struct rp1_pll_data *data = divider->data; @@ -704,7 +708,8 @@ static int rp1_pll_divider_is_on(struct clk_hw *hw) static int rp1_pll_divider_on(struct clk_hw *hw) { - struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw); + struct rp1_clk_desc *divider = + container_of(hw, struct rp1_clk_desc, div.hw); struct rp1_clockman *clockman = divider->clockman; const struct rp1_pll_data *data = divider->data; @@ -720,7 +725,8 @@ static int rp1_pll_divider_on(struct clk_hw *hw) static void rp1_pll_divider_off(struct clk_hw *hw) { - struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw); + struct rp1_clk_desc *divider = + container_of(hw, struct rp1_clk_desc, div.hw); struct rp1_clockman *clockman = divider->clockman; const struct rp1_pll_data *data = divider->data; @@ -730,11 +736,11 @@ static void rp1_pll_divider_off(struct clk_hw *hw) spin_unlock(&clockman->regs_lock); } -static int rp1_pll_divider_set_rate(struct clk_hw *hw, - unsigned long rate, +static int rp1_pll_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct rp1_clk_desc *divider = container_of(hw, struct rp1_clk_desc, div.hw); + struct rp1_clk_desc *divider = + container_of(hw, struct rp1_clk_desc, div.hw); struct rp1_clockman *clockman = divider->clockman; const struct rp1_pll_data *data = divider->data; u32 div, sec; @@ -796,7 +802,8 @@ static unsigned long rp1_clock_recalc_rate(struct clk_hw *hw, div = clockman_read(clockman, data->div_int_reg); frac = (data->div_frac_reg != 0) ? - clockman_read(clockman, data->div_frac_reg) : 0; + clockman_read(clockman, data->div_frac_reg) : + 0; /* If the integer portion of the divider is 0, treat it as 2^16 */ if (!div) @@ -818,11 +825,13 @@ static int rp1_clock_on(struct clk_hw *hw) spin_lock(&clockman->regs_lock); clockman_write(clockman, data->ctrl_reg, - clockman_read(clockman, data->ctrl_reg) | CLK_CTRL_ENABLE); + clockman_read(clockman, data->ctrl_reg) | + CLK_CTRL_ENABLE); /* If this is a GPCLK, turn on the output-enable */ if (data->oe_mask) clockman_write(clockman, GPCLK_OE_CTRL, - clockman_read(clockman, GPCLK_OE_CTRL) | data->oe_mask); + clockman_read(clockman, GPCLK_OE_CTRL) | + data->oe_mask); spin_unlock(&clockman->regs_lock); return 0; @@ -836,11 +845,13 @@ static void rp1_clock_off(struct clk_hw *hw) spin_lock(&clockman->regs_lock); clockman_write(clockman, data->ctrl_reg, - clockman_read(clockman, data->ctrl_reg) & ~CLK_CTRL_ENABLE); + clockman_read(clockman, data->ctrl_reg) & + ~CLK_CTRL_ENABLE); /* If this is a GPCLK, turn off the output-enable */ if (data->oe_mask) clockman_write(clockman, GPCLK_OE_CTRL, - clockman_read(clockman, GPCLK_OE_CTRL) & ~data->oe_mask); + clockman_read(clockman, GPCLK_OE_CTRL) & + ~data->oe_mask); spin_unlock(&clockman->regs_lock); } @@ -868,8 +879,7 @@ static u32 rp1_clock_choose_div(unsigned long rate, unsigned long parent_rate, div <<= CLK_DIV_FRAC_BITS; } - div = clamp(div, - 1ull << CLK_DIV_FRAC_BITS, + div = clamp(div, 1ull << CLK_DIV_FRAC_BITS, (u64)data->div_int_max << CLK_DIV_FRAC_BITS); return div; @@ -929,7 +939,8 @@ static int rp1_clock_set_parent(struct clk_hw *hw, u8 index) /* Select parent from aux list */ ctrl &= ~CLK_CTRL_AUXSRC_MASK; - ctrl |= FIELD_PREP(CLK_CTRL_AUXSRC_MASK, index - data->num_std_parents); + ctrl |= FIELD_PREP(CLK_CTRL_AUXSRC_MASK, + index - data->num_std_parents); /* Set src to aux list */ ctrl &= ~data->clk_src_mask; ctrl |= (AUX_SEL << CLK_CTRL_SRC_SHIFT) & data->clk_src_mask; @@ -948,10 +959,8 @@ static int rp1_clock_set_parent(struct clk_hw *hw, u8 index) return 0; } -static int rp1_clock_set_rate_and_parent(struct clk_hw *hw, - unsigned long rate, - unsigned long parent_rate, - u8 parent) +static int rp1_clock_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate, u8 parent) { struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); struct rp1_clockman *clockman = clock->clockman; @@ -962,7 +971,8 @@ static int rp1_clock_set_rate_and_parent(struct clk_hw *hw, clockman_write(clockman, data->div_int_reg, div >> CLK_DIV_FRAC_BITS); if (data->div_frac_reg) - clockman_write(clockman, data->div_frac_reg, div << (32 - CLK_DIV_FRAC_BITS)); + clockman_write(clockman, data->div_frac_reg, + div << (32 - CLK_DIV_FRAC_BITS)); spin_unlock(&clockman->regs_lock); @@ -983,8 +993,8 @@ static unsigned long calc_core_pll_rate(struct clk_hw *pll_hw, int *pdiv_prim, int *pdiv_clk) { static const int prim_divs[] = { - 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 15, 16, - 18, 20, 21, 24, 25, 28, 30, 35, 36, 42, 49, + 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 15, + 16, 18, 20, 21, 24, 25, 28, 30, 35, 36, 42, 49, }; const unsigned long xosc_rate = clk_hw_get_rate(clk_xosc); const unsigned long core_min = xosc_rate * 16; @@ -1018,7 +1028,9 @@ static unsigned long calc_core_pll_rate(struct clk_hw *pll_hw, div = ((best_rate << 24) + xosc_rate / 2) / xosc_rate; div_int = div >> 24; div_frac = div % (1 << 24); - core_rate = (xosc_rate * ((div_int << 24) + div_frac) + (1 << 23)) >> 24; + core_rate = (xosc_rate * ((div_int << 24) + div_frac) + + (1 << 23)) >> + 24; } else { core_rate = 0; } @@ -1031,8 +1043,7 @@ static unsigned long calc_core_pll_rate(struct clk_hw *pll_hw, return core_rate; } -static void rp1_clock_choose_div_and_prate(struct clk_hw *hw, - int parent_idx, +static void rp1_clock_choose_div_and_prate(struct clk_hw *hw, int parent_idx, unsigned long rate, unsigned long *prate, unsigned long *calc_rate) @@ -1047,7 +1058,8 @@ static void rp1_clock_choose_div_and_prate(struct clk_hw *hw, parent = clk_hw_get_parent_by_index(hw, parent_idx); - if (hw == clk_i2s_hw && clk_i2s->cached_rate == rate && parent == clk_audio_hw) { + if (hw == clk_i2s_hw && clk_i2s->cached_rate == rate && + parent == clk_audio_hw) { *prate = clk_audio->cached_rate; *calc_rate = rate; return; @@ -1057,7 +1069,8 @@ static void rp1_clock_choose_div_and_prate(struct clk_hw *hw, unsigned long core_rate, audio_rate, i2s_rate; int div_prim, div_clk; - core_rate = calc_core_pll_rate(parent, rate, &div_prim, &div_clk); + core_rate = + calc_core_pll_rate(parent, rate, &div_prim, &div_clk); audio_rate = DIV_ROUND_CLOSEST(core_rate, div_prim); i2s_rate = DIV_ROUND_CLOSEST(audio_rate, div_clk); clk_audio_core->cached_rate = core_rate; @@ -1152,8 +1165,8 @@ static int rp1_clock_determine_rate(struct clk_hw *hw, return 0; } -static int rp1_varsrc_set_rate(struct clk_hw *hw, - unsigned long rate, unsigned long parent_rate) +static int rp1_varsrc_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) { struct rp1_clk_desc *clock = container_of(hw, struct rp1_clk_desc, hw); @@ -1273,8 +1286,8 @@ static struct clk_hw *rp1_register_clock(struct rp1_clockman *clockman, const struct rp1_clock_data *clock_data = desc->data; int ret; - if (WARN_ON_ONCE(MAX_CLK_PARENTS < - clock_data->num_std_parents + clock_data->num_aux_parents)) + if (WARN_ON_ONCE(MAX_CLK_PARENTS < clock_data->num_std_parents + + clock_data->num_aux_parents)) return ERR_PTR(-EINVAL); /* There must be a gap for the AUX selector */ @@ -1292,168 +1305,114 @@ static struct clk_hw *rp1_register_clock(struct rp1_clockman *clockman, } /* Assignment helper macros for different clock types. */ -#define _REGISTER(f, ...) { .clk_register = f, __VA_ARGS__ } +#define _REGISTER(f, ...) { .clk_register = f, __VA_ARGS__ } -#define CLK_DATA(type, ...) .data = &(struct type) { __VA_ARGS__ } +#define CLK_DATA(type, ...) \ + .data = &(struct type) \ + { \ + __VA_ARGS__ \ + } -#define REGISTER_PLL(...) _REGISTER(&rp1_register_pll, \ - __VA_ARGS__) +#define REGISTER_PLL(...) _REGISTER(&rp1_register_pll, __VA_ARGS__) -#define REGISTER_PLL_DIV(...) _REGISTER(&rp1_register_pll_divider, \ - __VA_ARGS__) +#define REGISTER_PLL_DIV(...) _REGISTER(&rp1_register_pll_divider, __VA_ARGS__) -#define REGISTER_CLK(...) _REGISTER(&rp1_register_clock, \ - __VA_ARGS__) +#define REGISTER_CLK(...) _REGISTER(&rp1_register_clock, __VA_ARGS__) -static struct rp1_clk_desc pll_sys_core_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_sys_core", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_pll_core_ops, - CLK_IS_CRITICAL - ), - CLK_DATA(rp1_pll_core_data, - .cs_reg = PLL_SYS_CS, - .pwr_reg = PLL_SYS_PWR, - .fbdiv_int_reg = PLL_SYS_FBDIV_INT, - .fbdiv_frac_reg = PLL_SYS_FBDIV_FRAC, - ) -); +static struct rp1_clk_desc pll_sys_core_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_sys_core", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_pll_core_ops, CLK_IS_CRITICAL), + CLK_DATA(rp1_pll_core_data, .cs_reg = PLL_SYS_CS, + .pwr_reg = PLL_SYS_PWR, + .fbdiv_int_reg = PLL_SYS_FBDIV_INT, + .fbdiv_frac_reg = PLL_SYS_FBDIV_FRAC, )); -static struct rp1_clk_desc pll_audio_core_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_audio_core", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_pll_core_ops, - CLK_IS_CRITICAL - ), - CLK_DATA(rp1_pll_core_data, - .cs_reg = PLL_AUDIO_CS, - .pwr_reg = PLL_AUDIO_PWR, - .fbdiv_int_reg = PLL_AUDIO_FBDIV_INT, - .fbdiv_frac_reg = PLL_AUDIO_FBDIV_FRAC, - ) -); +static struct rp1_clk_desc pll_audio_core_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_audio_core", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_pll_core_ops, CLK_IS_CRITICAL), + CLK_DATA(rp1_pll_core_data, .cs_reg = PLL_AUDIO_CS, + .pwr_reg = PLL_AUDIO_PWR, + .fbdiv_int_reg = PLL_AUDIO_FBDIV_INT, + .fbdiv_frac_reg = PLL_AUDIO_FBDIV_FRAC, )); -static struct rp1_clk_desc pll_video_core_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_video_core", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_pll_core_ops, - CLK_IS_CRITICAL - ), - CLK_DATA(rp1_pll_core_data, - .cs_reg = PLL_VIDEO_CS, - .pwr_reg = PLL_VIDEO_PWR, - .fbdiv_int_reg = PLL_VIDEO_FBDIV_INT, - .fbdiv_frac_reg = PLL_VIDEO_FBDIV_FRAC, - ) -); +static struct rp1_clk_desc pll_video_core_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_video_core", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_pll_core_ops, CLK_IS_CRITICAL), + CLK_DATA(rp1_pll_core_data, .cs_reg = PLL_VIDEO_CS, + .pwr_reg = PLL_VIDEO_PWR, + .fbdiv_int_reg = PLL_VIDEO_FBDIV_INT, + .fbdiv_frac_reg = PLL_VIDEO_FBDIV_FRAC, )); -static struct rp1_clk_desc pll_sys_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_sys", - (const struct clk_parent_data[]) { - { .hw = &pll_sys_core_desc.hw } - }, - &rp1_pll_ops, - 0 - ), - CLK_DATA(rp1_pll_data, - .ctrl_reg = PLL_SYS_PRIM, - .fc0_src = FC_NUM(0, 2), - ) -); +static struct rp1_clk_desc pll_sys_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_sys", + (const struct clk_parent_data[]){ + { .hw = &pll_sys_core_desc.hw } }, + &rp1_pll_ops, 0), + CLK_DATA(rp1_pll_data, .ctrl_reg = PLL_SYS_PRIM, + .fc0_src = FC_NUM(0, 2), )); -static struct rp1_clk_desc pll_audio_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_audio", - (const struct clk_parent_data[]) { - { .hw = &pll_audio_core_desc.hw } - }, - &rp1_pll_ops, - CLK_SET_RATE_PARENT - ), - CLK_DATA(rp1_pll_data, - .ctrl_reg = PLL_AUDIO_PRIM, - .fc0_src = FC_NUM(4, 2), - ) -); +static struct rp1_clk_desc pll_audio_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_audio", + (const struct clk_parent_data[]){ + { .hw = &pll_audio_core_desc.hw } }, + &rp1_pll_ops, CLK_SET_RATE_PARENT), + CLK_DATA(rp1_pll_data, .ctrl_reg = PLL_AUDIO_PRIM, + .fc0_src = FC_NUM(4, 2), )); -static struct rp1_clk_desc pll_video_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_video", - (const struct clk_parent_data[]) { - { .hw = &pll_video_core_desc.hw } - }, - &rp1_pll_ops, - 0 - ), - CLK_DATA(rp1_pll_data, - .ctrl_reg = PLL_VIDEO_PRIM, - .fc0_src = FC_NUM(3, 2), - ) -); +static struct rp1_clk_desc pll_video_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_video", + (const struct clk_parent_data[]){ + { .hw = &pll_video_core_desc.hw } }, + &rp1_pll_ops, 0), + CLK_DATA(rp1_pll_data, .ctrl_reg = PLL_VIDEO_PRIM, + .fc0_src = FC_NUM(3, 2), )); -static struct rp1_clk_desc pll_sys_sec_desc = REGISTER_PLL_DIV( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_sys_sec", - (const struct clk_parent_data[]) { - { .hw = &pll_sys_core_desc.hw } - }, - &rp1_pll_divider_ops, - 0 - ), - CLK_DATA(rp1_pll_data, - .ctrl_reg = PLL_SYS_SEC, - .fc0_src = FC_NUM(2, 2), - ) -); +static struct rp1_clk_desc pll_sys_sec_desc = + REGISTER_PLL_DIV(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_sys_sec", + (const struct clk_parent_data[]){ + { .hw = &pll_sys_core_desc.hw } }, + &rp1_pll_divider_ops, 0), + CLK_DATA(rp1_pll_data, .ctrl_reg = PLL_SYS_SEC, + .fc0_src = FC_NUM(2, 2), )); -static struct rp1_clk_desc pll_video_sec_desc = REGISTER_PLL_DIV( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_video_sec", - (const struct clk_parent_data[]) { - { .hw = &pll_video_core_desc.hw } - }, - &rp1_pll_divider_ops, - 0 - ), - CLK_DATA(rp1_pll_data, - .ctrl_reg = PLL_VIDEO_SEC, - .fc0_src = FC_NUM(5, 3), - ) -); +static struct rp1_clk_desc pll_video_sec_desc = + REGISTER_PLL_DIV(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_video_sec", + (const struct clk_parent_data[]){ + { .hw = &pll_video_core_desc.hw } }, + &rp1_pll_divider_ops, 0), + CLK_DATA(rp1_pll_data, .ctrl_reg = PLL_VIDEO_SEC, + .fc0_src = FC_NUM(5, 3), )); static const struct clk_parent_data clk_eth_tsu_parents[] = { - { .index = 0 }, - { .hw = &pll_video_sec_desc.hw }, - { .index = -1 }, - { .index = -1 }, - { .index = -1 }, - { .index = -1 }, - { .index = -1 }, - { .index = -1 }, + { .index = 0 }, { .hw = &pll_video_sec_desc.hw }, + { .index = -1 }, { .index = -1 }, + { .index = -1 }, { .index = -1 }, + { .index = -1 }, { .index = -1 }, }; -static struct rp1_clk_desc clk_eth_tsu_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_eth_tsu", - clk_eth_tsu_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 8, - .ctrl_reg = CLK_ETH_TSU_CTRL, - .div_int_reg = CLK_ETH_TSU_DIV_INT, - .sel_reg = CLK_ETH_TSU_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 50 * HZ_PER_MHZ, - .fc0_src = FC_NUM(5, 7), - ) -); +static struct rp1_clk_desc clk_eth_tsu_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA("clk_eth_tsu", + clk_eth_tsu_parents, + &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 8, + .ctrl_reg = CLK_ETH_TSU_CTRL, + .div_int_reg = CLK_ETH_TSU_DIV_INT, + .sel_reg = CLK_ETH_TSU_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(5, 7), )); static const struct clk_parent_data clk_eth_parents[] = { { .hw = &pll_sys_sec_desc.div.hw }, @@ -1461,24 +1420,16 @@ static const struct clk_parent_data clk_eth_parents[] = { { .hw = &pll_video_sec_desc.hw }, }; -static struct rp1_clk_desc clk_eth_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_eth", - clk_eth_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 3, - .ctrl_reg = CLK_ETH_CTRL, - .div_int_reg = CLK_ETH_DIV_INT, - .sel_reg = CLK_ETH_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 125 * HZ_PER_MHZ, - .fc0_src = FC_NUM(4, 6), - ) -); +static struct rp1_clk_desc clk_eth_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_eth", clk_eth_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 3, .ctrl_reg = CLK_ETH_CTRL, + .div_int_reg = CLK_ETH_DIV_INT, + .sel_reg = CLK_ETH_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 125 * HZ_PER_MHZ, + .fc0_src = FC_NUM(4, 6), )); static const struct clk_parent_data clk_sys_parents[] = { { .index = 0 }, @@ -1486,126 +1437,79 @@ static const struct clk_parent_data clk_sys_parents[] = { { .hw = &pll_sys_desc.hw }, }; -static struct rp1_clk_desc clk_sys_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_sys", - clk_sys_parents, - &rp1_clk_ops, - CLK_IS_CRITICAL - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 3, - .num_aux_parents = 0, - .ctrl_reg = CLK_SYS_CTRL, - .div_int_reg = CLK_SYS_DIV_INT, - .sel_reg = CLK_SYS_SEL, - .div_int_max = DIV_INT_24BIT_MAX, - .max_freq = 200 * HZ_PER_MHZ, - .fc0_src = FC_NUM(0, 4), - .clk_src_mask = 0x3, - ) -); +static struct rp1_clk_desc clk_sys_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_sys", clk_sys_parents, &rp1_clk_ops, + CLK_IS_CRITICAL), + CLK_DATA(rp1_clock_data, .num_std_parents = 3, + .num_aux_parents = 0, .ctrl_reg = CLK_SYS_CTRL, + .div_int_reg = CLK_SYS_DIV_INT, + .sel_reg = CLK_SYS_SEL, + .div_int_max = DIV_INT_24BIT_MAX, + .max_freq = 200 * HZ_PER_MHZ, + .fc0_src = FC_NUM(0, 4), .clk_src_mask = 0x3, )); -static struct rp1_clk_desc pll_sys_pri_ph_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_sys_pri_ph", - (const struct clk_parent_data[]) { - { .hw = &pll_sys_desc.hw } - }, - &rp1_pll_ph_ops, - 0 - ), - CLK_DATA(rp1_pll_ph_data, - .ph_reg = PLL_SYS_PRIM, - .fixed_divider = 2, - .phase = RP1_PLL_PHASE_0, - .fc0_src = FC_NUM(1, 2), - ) -); +static struct rp1_clk_desc pll_sys_pri_ph_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_sys_pri_ph", + (const struct clk_parent_data[]){ + { .hw = &pll_sys_desc.hw } }, + &rp1_pll_ph_ops, 0), + CLK_DATA(rp1_pll_ph_data, .ph_reg = PLL_SYS_PRIM, + .fixed_divider = 2, .phase = RP1_PLL_PHASE_0, + .fc0_src = FC_NUM(1, 2), )); -static struct rp1_clk_desc pll_audio_pri_ph_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_audio_pri_ph", - (const struct clk_parent_data[]) { - { .hw = &pll_audio_desc.hw } - }, - &rp1_pll_ph_ops, - 0 - ), - CLK_DATA(rp1_pll_ph_data, - .ph_reg = PLL_AUDIO_PRIM, - .fixed_divider = 2, - .phase = RP1_PLL_PHASE_0, - .fc0_src = FC_NUM(5, 1), - ) -); +static struct rp1_clk_desc pll_audio_pri_ph_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_audio_pri_ph", + (const struct clk_parent_data[]){ + { .hw = &pll_audio_desc.hw } }, + &rp1_pll_ph_ops, 0), + CLK_DATA(rp1_pll_ph_data, .ph_reg = PLL_AUDIO_PRIM, + .fixed_divider = 2, .phase = RP1_PLL_PHASE_0, + .fc0_src = FC_NUM(5, 1), )); -static struct rp1_clk_desc pll_video_pri_ph_desc = REGISTER_PLL( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_video_pri_ph", - (const struct clk_parent_data[]) { - { .hw = &pll_video_desc.hw } - }, - &rp1_pll_ph_ops, - 0 - ), - CLK_DATA(rp1_pll_ph_data, - .ph_reg = PLL_VIDEO_PRIM, - .fixed_divider = 2, - .phase = RP1_PLL_PHASE_0, - .fc0_src = FC_NUM(4, 3), - ) -); +static struct rp1_clk_desc pll_video_pri_ph_desc = + REGISTER_PLL(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_video_pri_ph", + (const struct clk_parent_data[]){ + { .hw = &pll_video_desc.hw } }, + &rp1_pll_ph_ops, 0), + CLK_DATA(rp1_pll_ph_data, .ph_reg = PLL_VIDEO_PRIM, + .fixed_divider = 2, .phase = RP1_PLL_PHASE_0, + .fc0_src = FC_NUM(4, 3), )); -static struct rp1_clk_desc pll_audio_sec_desc = REGISTER_PLL_DIV( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_audio_sec", - (const struct clk_parent_data[]) { - { .hw = &pll_audio_core_desc.hw } - }, - &rp1_pll_divider_ops, - 0 - ), - CLK_DATA(rp1_pll_data, - .ctrl_reg = PLL_AUDIO_SEC, - .fc0_src = FC_NUM(6, 2), - ) -); +static struct rp1_clk_desc pll_audio_sec_desc = + REGISTER_PLL_DIV(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_audio_sec", + (const struct clk_parent_data[]){ + { .hw = &pll_audio_core_desc.hw } }, + &rp1_pll_divider_ops, 0), + CLK_DATA(rp1_pll_data, .ctrl_reg = PLL_AUDIO_SEC, + .fc0_src = FC_NUM(6, 2), )); -static struct rp1_clk_desc pll_audio_tern_desc = REGISTER_PLL_DIV( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "pll_audio_tern", - (const struct clk_parent_data[]) { - { .hw = &pll_audio_core_desc.hw } - }, - &rp1_pll_divider_ops, - 0 - ), - CLK_DATA(rp1_pll_data, - .ctrl_reg = PLL_AUDIO_TERN, - .fc0_src = FC_NUM(6, 2), - ) -); +static struct rp1_clk_desc pll_audio_tern_desc = + REGISTER_PLL_DIV(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "pll_audio_tern", + (const struct clk_parent_data[]){ + { .hw = &pll_audio_core_desc.hw } }, + &rp1_pll_divider_ops, 0), + CLK_DATA(rp1_pll_data, .ctrl_reg = PLL_AUDIO_TERN, + .fc0_src = FC_NUM(6, 2), )); -static struct rp1_clk_desc clk_slow_sys_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_slow_sys", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_clk_ops, - CLK_IS_CRITICAL - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 1, - .num_aux_parents = 0, - .ctrl_reg = CLK_SLOW_SYS_CTRL, - .div_int_reg = CLK_SLOW_SYS_DIV_INT, - .sel_reg = CLK_SLOW_SYS_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 50 * HZ_PER_MHZ, - .fc0_src = FC_NUM(1, 4), - .clk_src_mask = 0x1, - ) -); +static struct rp1_clk_desc clk_slow_sys_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_slow_sys", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_clk_ops, CLK_IS_CRITICAL), + CLK_DATA(rp1_clock_data, .num_std_parents = 1, + .num_aux_parents = 0, + .ctrl_reg = CLK_SLOW_SYS_CTRL, + .div_int_reg = CLK_SLOW_SYS_DIV_INT, + .sel_reg = CLK_SLOW_SYS_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(1, 4), .clk_src_mask = 0x1, )); static const struct clk_parent_data clk_dma_parents[] = { { .hw = &pll_sys_pri_ph_desc.hw }, @@ -1613,24 +1517,16 @@ static const struct clk_parent_data clk_dma_parents[] = { { .index = 0 }, }; -static struct rp1_clk_desc clk_dma_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_dma", - clk_dma_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 3, - .ctrl_reg = CLK_DMA_CTRL, - .div_int_reg = CLK_DMA_DIV_INT, - .sel_reg = CLK_DMA_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 100 * HZ_PER_MHZ, - .fc0_src = FC_NUM(2, 2), - ) -); +static struct rp1_clk_desc clk_dma_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_dma", clk_dma_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 3, .ctrl_reg = CLK_DMA_CTRL, + .div_int_reg = CLK_DMA_DIV_INT, + .sel_reg = CLK_DMA_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(2, 2), )); static const struct clk_parent_data clk_uart_parents[] = { { .hw = &pll_sys_pri_ph_desc.hw }, @@ -1638,24 +1534,16 @@ static const struct clk_parent_data clk_uart_parents[] = { { .index = 0 }, }; -static struct rp1_clk_desc clk_uart_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_uart", - clk_uart_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 3, - .ctrl_reg = CLK_UART_CTRL, - .div_int_reg = CLK_UART_DIV_INT, - .sel_reg = CLK_UART_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 100 * HZ_PER_MHZ, - .fc0_src = FC_NUM(6, 7), - ) -); +static struct rp1_clk_desc clk_uart_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_uart", clk_uart_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 3, .ctrl_reg = CLK_UART_CTRL, + .div_int_reg = CLK_UART_DIV_INT, + .sel_reg = CLK_UART_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(6, 7), )); static const struct clk_parent_data clk_pwm0_parents[] = { { .index = -1 }, @@ -1663,25 +1551,17 @@ static const struct clk_parent_data clk_pwm0_parents[] = { { .index = 0 }, }; -static struct rp1_clk_desc clk_pwm0_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_pwm0", - clk_pwm0_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 3, - .ctrl_reg = CLK_PWM0_CTRL, - .div_int_reg = CLK_PWM0_DIV_INT, - .div_frac_reg = CLK_PWM0_DIV_FRAC, - .sel_reg = CLK_PWM0_SEL, - .div_int_max = DIV_INT_16BIT_MAX, - .max_freq = 76800 * HZ_PER_KHZ, - .fc0_src = FC_NUM(0, 5), - ) -); +static struct rp1_clk_desc clk_pwm0_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_pwm0", clk_pwm0_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 3, .ctrl_reg = CLK_PWM0_CTRL, + .div_int_reg = CLK_PWM0_DIV_INT, + .div_frac_reg = CLK_PWM0_DIV_FRAC, + .sel_reg = CLK_PWM0_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 76800 * HZ_PER_KHZ, + .fc0_src = FC_NUM(0, 5), )); static const struct clk_parent_data clk_pwm1_parents[] = { { .index = -1 }, @@ -1689,52 +1569,36 @@ static const struct clk_parent_data clk_pwm1_parents[] = { { .index = 0 }, }; -static struct rp1_clk_desc clk_pwm1_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_pwm1", - clk_pwm1_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 3, - .ctrl_reg = CLK_PWM1_CTRL, - .div_int_reg = CLK_PWM1_DIV_INT, - .div_frac_reg = CLK_PWM1_DIV_FRAC, - .sel_reg = CLK_PWM1_SEL, - .div_int_max = DIV_INT_16BIT_MAX, - .max_freq = 76800 * HZ_PER_KHZ, - .fc0_src = FC_NUM(1, 5), - ) -); +static struct rp1_clk_desc clk_pwm1_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_pwm1", clk_pwm1_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 3, .ctrl_reg = CLK_PWM1_CTRL, + .div_int_reg = CLK_PWM1_DIV_INT, + .div_frac_reg = CLK_PWM1_DIV_FRAC, + .sel_reg = CLK_PWM1_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 76800 * HZ_PER_KHZ, + .fc0_src = FC_NUM(1, 5), )); static const struct clk_parent_data clk_audio_in_parents[] = { - { .index = -1 }, - { .index = -1 }, - { .index = -1 }, - { .hw = &pll_video_sec_desc.hw }, + { .index = -1 }, { .index = -1 }, + { .index = -1 }, { .hw = &pll_video_sec_desc.hw }, { .index = 0 }, }; -static struct rp1_clk_desc clk_audio_in_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_audio_in", - clk_audio_in_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 5, - .ctrl_reg = CLK_AUDIO_IN_CTRL, - .div_int_reg = CLK_AUDIO_IN_DIV_INT, - .sel_reg = CLK_AUDIO_IN_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 76800 * HZ_PER_KHZ, - .fc0_src = FC_NUM(2, 5), - ) -); +static struct rp1_clk_desc clk_audio_in_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA("clk_audio_in", + clk_audio_in_parents, + &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 5, + .ctrl_reg = CLK_AUDIO_IN_CTRL, + .div_int_reg = CLK_AUDIO_IN_DIV_INT, + .sel_reg = CLK_AUDIO_IN_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 76800 * HZ_PER_KHZ, + .fc0_src = FC_NUM(2, 5), )); static const struct clk_parent_data clk_audio_out_parents[] = { { .index = -1 }, @@ -1743,24 +1607,18 @@ static const struct clk_parent_data clk_audio_out_parents[] = { { .index = 0 }, }; -static struct rp1_clk_desc clk_audio_out_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_audio_out", - clk_audio_out_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 4, - .ctrl_reg = CLK_AUDIO_OUT_CTRL, - .div_int_reg = CLK_AUDIO_OUT_DIV_INT, - .sel_reg = CLK_AUDIO_OUT_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 153600 * HZ_PER_KHZ, - .fc0_src = FC_NUM(3, 5), - ) -); +static struct rp1_clk_desc clk_audio_out_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA("clk_audio_out", + clk_audio_out_parents, + &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 4, + .ctrl_reg = CLK_AUDIO_OUT_CTRL, + .div_int_reg = CLK_AUDIO_OUT_DIV_INT, + .sel_reg = CLK_AUDIO_OUT_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 153600 * HZ_PER_KHZ, + .fc0_src = FC_NUM(3, 5), )); static const struct clk_parent_data clk_i2s_parents[] = { { .index = 0 }, @@ -1768,122 +1626,87 @@ static const struct clk_parent_data clk_i2s_parents[] = { { .hw = &pll_audio_sec_desc.hw }, }; -static struct rp1_clk_desc clk_i2s_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_i2s", - clk_i2s_parents, - &rp1_clk_ops, - CLK_SET_RATE_PARENT - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 3, - .ctrl_reg = CLK_I2S_CTRL, - .div_int_reg = CLK_I2S_DIV_INT, - .sel_reg = CLK_I2S_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 50 * HZ_PER_MHZ, - .fc0_src = FC_NUM(4, 4), - ) -); +static struct rp1_clk_desc clk_i2s_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_i2s", clk_i2s_parents, &rp1_clk_ops, + CLK_SET_RATE_PARENT), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 3, .ctrl_reg = CLK_I2S_CTRL, + .div_int_reg = CLK_I2S_DIV_INT, + .sel_reg = CLK_I2S_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(4, 4), )); -static struct rp1_clk_desc clk_mipi0_cfg_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_mipi0_cfg", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 1, - .ctrl_reg = CLK_MIPI0_CFG_CTRL, - .div_int_reg = CLK_MIPI0_CFG_DIV_INT, - .sel_reg = CLK_MIPI0_CFG_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 50 * HZ_PER_MHZ, - .fc0_src = FC_NUM(4, 5), - ) -); +static struct rp1_clk_desc clk_mipi0_cfg_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_mipi0_cfg", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_MIPI0_CFG_CTRL, + .div_int_reg = CLK_MIPI0_CFG_DIV_INT, + .sel_reg = CLK_MIPI0_CFG_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(4, 5), )); -static struct rp1_clk_desc clk_mipi1_cfg_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_mipi1_cfg", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 1, - .ctrl_reg = CLK_MIPI1_CFG_CTRL, - .div_int_reg = CLK_MIPI1_CFG_DIV_INT, - .sel_reg = CLK_MIPI1_CFG_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 50 * HZ_PER_MHZ, - .fc0_src = FC_NUM(5, 6), - .clk_src_mask = 0x1, - ) -); +static struct rp1_clk_desc clk_mipi1_cfg_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_mipi1_cfg", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_MIPI1_CFG_CTRL, + .div_int_reg = CLK_MIPI1_CFG_DIV_INT, + .sel_reg = CLK_MIPI1_CFG_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(5, 6), .clk_src_mask = 0x1, )); -static struct rp1_clk_desc clk_adc_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_adc", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 1, - .ctrl_reg = CLK_ADC_CTRL, - .div_int_reg = CLK_ADC_DIV_INT, - .sel_reg = CLK_ADC_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 50 * HZ_PER_MHZ, - .fc0_src = FC_NUM(5, 5), - ) -); +static struct rp1_clk_desc clk_adc_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_adc", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 1, .ctrl_reg = CLK_ADC_CTRL, + .div_int_reg = CLK_ADC_DIV_INT, + .sel_reg = CLK_ADC_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(5, 5), )); -static struct rp1_clk_desc clk_sdio_timer_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_sdio_timer", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 1, - .ctrl_reg = CLK_SDIO_TIMER_CTRL, - .div_int_reg = CLK_SDIO_TIMER_DIV_INT, - .sel_reg = CLK_SDIO_TIMER_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 50 * HZ_PER_MHZ, - .fc0_src = FC_NUM(3, 4), - ) -); +static struct rp1_clk_desc clk_sdio_timer_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_sdio_timer", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_SDIO_TIMER_CTRL, + .div_int_reg = CLK_SDIO_TIMER_DIV_INT, + .sel_reg = CLK_SDIO_TIMER_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 50 * HZ_PER_MHZ, + .fc0_src = FC_NUM(3, 4), )); -static struct rp1_clk_desc clk_sdio_alt_src_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_sdio_alt_src", - (const struct clk_parent_data[]) { - { .hw = &pll_sys_desc.hw } - }, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 1, - .ctrl_reg = CLK_SDIO_ALT_SRC_CTRL, - .div_int_reg = CLK_SDIO_ALT_SRC_DIV_INT, - .sel_reg = CLK_SDIO_ALT_SRC_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 200 * HZ_PER_MHZ, - .fc0_src = FC_NUM(5, 4), - ) -); +static struct rp1_clk_desc clk_sdio_alt_src_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_sdio_alt_src", + (const struct clk_parent_data[]){ + { .hw = &pll_sys_desc.hw } }, + &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 1, + .ctrl_reg = CLK_SDIO_ALT_SRC_CTRL, + .div_int_reg = CLK_SDIO_ALT_SRC_DIV_INT, + .sel_reg = CLK_SDIO_ALT_SRC_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 200 * HZ_PER_MHZ, + .fc0_src = FC_NUM(5, 4), )); static const struct clk_parent_data clk_dpi_parents[] = { { .hw = &pll_sys_desc.hw }, @@ -1897,23 +1720,17 @@ static const struct clk_parent_data clk_dpi_parents[] = { }; static struct rp1_clk_desc clk_dpi_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_dpi", - clk_dpi_parents, - &rp1_clk_ops, - CLK_SET_RATE_NO_REPARENT /* Let DPI driver set parent */ - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 8, - .ctrl_reg = VIDEO_CLK_DPI_CTRL, - .div_int_reg = VIDEO_CLK_DPI_DIV_INT, - .sel_reg = VIDEO_CLK_DPI_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 200 * HZ_PER_MHZ, - .fc0_src = FC_NUM(1, 6), - ) -); + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_dpi", clk_dpi_parents, &rp1_clk_ops, + CLK_SET_RATE_NO_REPARENT /* Let DPI driver set parent */ + ), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 8, .ctrl_reg = VIDEO_CLK_DPI_CTRL, + .div_int_reg = VIDEO_CLK_DPI_DIV_INT, + .sel_reg = VIDEO_CLK_DPI_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 200 * HZ_PER_MHZ, + .fc0_src = FC_NUM(1, 6), )); static const struct clk_parent_data clk_gp0_parents[] = { { .index = 0 }, @@ -1934,26 +1751,18 @@ static const struct clk_parent_data clk_gp0_parents[] = { { .hw = &clk_sys_desc.hw }, }; -static struct rp1_clk_desc clk_gp0_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_gp0", - clk_gp0_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 16, - .oe_mask = BIT(0), - .ctrl_reg = CLK_GP0_CTRL, - .div_int_reg = CLK_GP0_DIV_INT, - .div_frac_reg = CLK_GP0_DIV_FRAC, - .sel_reg = CLK_GP0_SEL, - .div_int_max = DIV_INT_16BIT_MAX, - .max_freq = 100 * HZ_PER_MHZ, - .fc0_src = FC_NUM(0, 1), - ) -); +static struct rp1_clk_desc clk_gp0_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp0", clk_gp0_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 16, .oe_mask = BIT(0), + .ctrl_reg = CLK_GP0_CTRL, + .div_int_reg = CLK_GP0_DIV_INT, + .div_frac_reg = CLK_GP0_DIV_FRAC, + .sel_reg = CLK_GP0_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(0, 1), )); static const struct clk_parent_data clk_gp1_parents[] = { { .hw = &clk_sdio_timer_desc.hw }, @@ -1974,52 +1783,34 @@ static const struct clk_parent_data clk_gp1_parents[] = { { .index = -1 }, }; -static struct rp1_clk_desc clk_gp1_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_gp1", - clk_gp1_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 16, - .oe_mask = BIT(1), - .ctrl_reg = CLK_GP1_CTRL, - .div_int_reg = CLK_GP1_DIV_INT, - .div_frac_reg = CLK_GP1_DIV_FRAC, - .sel_reg = CLK_GP1_SEL, - .div_int_max = DIV_INT_16BIT_MAX, - .max_freq = 100 * HZ_PER_MHZ, - .fc0_src = FC_NUM(1, 1), - ) -); +static struct rp1_clk_desc clk_gp1_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp1", clk_gp1_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 16, .oe_mask = BIT(1), + .ctrl_reg = CLK_GP1_CTRL, + .div_int_reg = CLK_GP1_DIV_INT, + .div_frac_reg = CLK_GP1_DIV_FRAC, + .sel_reg = CLK_GP1_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(1, 1), )); -static struct rp1_clk_desc clksrc_mipi0_dsi_byteclk_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clksrc_mipi0_dsi_byteclk", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_varsrc_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 1, - .num_aux_parents = 0, - ) -); +static struct rp1_clk_desc clksrc_mipi0_dsi_byteclk_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clksrc_mipi0_dsi_byteclk", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_varsrc_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 1, + .num_aux_parents = 0, )); -static struct rp1_clk_desc clksrc_mipi1_dsi_byteclk_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clksrc_mipi1_dsi_byteclk", - (const struct clk_parent_data[]) { { .index = 0 } }, - &rp1_varsrc_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 1, - .num_aux_parents = 0, - ) -); +static struct rp1_clk_desc clksrc_mipi1_dsi_byteclk_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clksrc_mipi1_dsi_byteclk", + (const struct clk_parent_data[]){ { .index = 0 } }, + &rp1_varsrc_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 1, + .num_aux_parents = 0, )); static const struct clk_parent_data clk_mipi0_dpi_parents[] = { { .hw = &pll_sys_desc.hw }, @@ -2033,24 +1824,19 @@ static const struct clk_parent_data clk_mipi0_dpi_parents[] = { }; static struct rp1_clk_desc clk_mipi0_dpi_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_mipi0_dpi", - clk_mipi0_dpi_parents, - &rp1_clk_ops, - CLK_SET_RATE_NO_REPARENT /* Let DSI driver set parent */ - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 8, - .ctrl_reg = VIDEO_CLK_MIPI0_DPI_CTRL, - .div_int_reg = VIDEO_CLK_MIPI0_DPI_DIV_INT, - .div_frac_reg = VIDEO_CLK_MIPI0_DPI_DIV_FRAC, - .sel_reg = VIDEO_CLK_MIPI0_DPI_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 200 * HZ_PER_MHZ, - .fc0_src = FC_NUM(2, 6), - ) -); + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_mipi0_dpi", clk_mipi0_dpi_parents, &rp1_clk_ops, + CLK_SET_RATE_NO_REPARENT /* Let DSI driver set parent */ + ), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 8, + .ctrl_reg = VIDEO_CLK_MIPI0_DPI_CTRL, + .div_int_reg = VIDEO_CLK_MIPI0_DPI_DIV_INT, + .div_frac_reg = VIDEO_CLK_MIPI0_DPI_DIV_FRAC, + .sel_reg = VIDEO_CLK_MIPI0_DPI_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 200 * HZ_PER_MHZ, + .fc0_src = FC_NUM(2, 6), )); static const struct clk_parent_data clk_mipi1_dpi_parents[] = { { .hw = &pll_sys_desc.hw }, @@ -2064,24 +1850,19 @@ static const struct clk_parent_data clk_mipi1_dpi_parents[] = { }; static struct rp1_clk_desc clk_mipi1_dpi_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_mipi1_dpi", - clk_mipi1_dpi_parents, - &rp1_clk_ops, - CLK_SET_RATE_NO_REPARENT /* Let DSI driver set parent */ - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 8, - .ctrl_reg = VIDEO_CLK_MIPI1_DPI_CTRL, - .div_int_reg = VIDEO_CLK_MIPI1_DPI_DIV_INT, - .div_frac_reg = VIDEO_CLK_MIPI1_DPI_DIV_FRAC, - .sel_reg = VIDEO_CLK_MIPI1_DPI_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 200 * HZ_PER_MHZ, - .fc0_src = FC_NUM(3, 6), - ) -); + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_mipi1_dpi", clk_mipi1_dpi_parents, &rp1_clk_ops, + CLK_SET_RATE_NO_REPARENT /* Let DSI driver set parent */ + ), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 8, + .ctrl_reg = VIDEO_CLK_MIPI1_DPI_CTRL, + .div_int_reg = VIDEO_CLK_MIPI1_DPI_DIV_INT, + .div_frac_reg = VIDEO_CLK_MIPI1_DPI_DIV_FRAC, + .sel_reg = VIDEO_CLK_MIPI1_DPI_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 200 * HZ_PER_MHZ, + .fc0_src = FC_NUM(3, 6), )); static const struct clk_parent_data clk_gp2_parents[] = { { .hw = &clk_sdio_alt_src_desc.hw }, @@ -2102,26 +1883,18 @@ static const struct clk_parent_data clk_gp2_parents[] = { { .hw = &clk_sys_desc.hw }, }; -static struct rp1_clk_desc clk_gp2_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_gp2", - clk_gp2_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 16, - .oe_mask = BIT(2), - .ctrl_reg = CLK_GP2_CTRL, - .div_int_reg = CLK_GP2_DIV_INT, - .div_frac_reg = CLK_GP2_DIV_FRAC, - .sel_reg = CLK_GP2_SEL, - .div_int_max = DIV_INT_16BIT_MAX, - .max_freq = 100 * HZ_PER_MHZ, - .fc0_src = FC_NUM(2, 1), - ) -); +static struct rp1_clk_desc clk_gp2_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp2", clk_gp2_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 16, .oe_mask = BIT(2), + .ctrl_reg = CLK_GP2_CTRL, + .div_int_reg = CLK_GP2_DIV_INT, + .div_frac_reg = CLK_GP2_DIV_FRAC, + .sel_reg = CLK_GP2_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(2, 1), )); static const struct clk_parent_data clk_gp3_parents[] = { { .index = 0 }, @@ -2142,26 +1915,18 @@ static const struct clk_parent_data clk_gp3_parents[] = { { .index = -1 }, }; -static struct rp1_clk_desc clk_gp3_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_gp3", - clk_gp3_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 16, - .oe_mask = BIT(3), - .ctrl_reg = CLK_GP3_CTRL, - .div_int_reg = CLK_GP3_DIV_INT, - .div_frac_reg = CLK_GP3_DIV_FRAC, - .sel_reg = CLK_GP3_SEL, - .div_int_max = DIV_INT_16BIT_MAX, - .max_freq = 100 * HZ_PER_MHZ, - .fc0_src = FC_NUM(3, 1), - ) -); +static struct rp1_clk_desc clk_gp3_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp3", clk_gp3_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 16, .oe_mask = BIT(3), + .ctrl_reg = CLK_GP3_CTRL, + .div_int_reg = CLK_GP3_DIV_INT, + .div_frac_reg = CLK_GP3_DIV_FRAC, + .sel_reg = CLK_GP3_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(3, 1), )); static const struct clk_parent_data clk_gp4_parents[] = { { .index = 0 }, @@ -2182,26 +1947,18 @@ static const struct clk_parent_data clk_gp4_parents[] = { { .hw = &clk_sys_desc.hw }, }; -static struct rp1_clk_desc clk_gp4_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_gp4", - clk_gp4_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 16, - .oe_mask = BIT(4), - .ctrl_reg = CLK_GP4_CTRL, - .div_int_reg = CLK_GP4_DIV_INT, - .div_frac_reg = CLK_GP4_DIV_FRAC, - .sel_reg = CLK_GP4_SEL, - .div_int_max = DIV_INT_16BIT_MAX, - .max_freq = 100 * HZ_PER_MHZ, - .fc0_src = FC_NUM(4, 1), - ) -); +static struct rp1_clk_desc clk_gp4_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp4", clk_gp4_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 16, .oe_mask = BIT(4), + .ctrl_reg = CLK_GP4_CTRL, + .div_int_reg = CLK_GP4_DIV_INT, + .div_frac_reg = CLK_GP4_DIV_FRAC, + .sel_reg = CLK_GP4_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(4, 1), )); static const struct clk_parent_data clk_vec_parents[] = { { .hw = &pll_sys_pri_ph_desc.hw }, @@ -2215,23 +1972,17 @@ static const struct clk_parent_data clk_vec_parents[] = { }; static struct rp1_clk_desc clk_vec_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_vec", - clk_vec_parents, - &rp1_clk_ops, - CLK_SET_RATE_NO_REPARENT /* Let VEC driver set parent */ - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 8, - .ctrl_reg = VIDEO_CLK_VEC_CTRL, - .div_int_reg = VIDEO_CLK_VEC_DIV_INT, - .sel_reg = VIDEO_CLK_VEC_SEL, - .div_int_max = DIV_INT_8BIT_MAX, - .max_freq = 108 * HZ_PER_MHZ, - .fc0_src = FC_NUM(0, 6), - ) -); + .hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_vec", clk_vec_parents, &rp1_clk_ops, + CLK_SET_RATE_NO_REPARENT /* Let VEC driver set parent */ + ), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 8, .ctrl_reg = VIDEO_CLK_VEC_CTRL, + .div_int_reg = VIDEO_CLK_VEC_DIV_INT, + .sel_reg = VIDEO_CLK_VEC_SEL, + .div_int_max = DIV_INT_8BIT_MAX, + .max_freq = 108 * HZ_PER_MHZ, + .fc0_src = FC_NUM(0, 6), )); static const struct clk_parent_data clk_gp5_parents[] = { { .index = 0 }, @@ -2252,26 +2003,18 @@ static const struct clk_parent_data clk_gp5_parents[] = { { .index = -1 }, }; -static struct rp1_clk_desc clk_gp5_desc = REGISTER_CLK( - .hw.init = CLK_HW_INIT_PARENTS_DATA( - "clk_gp5", - clk_gp5_parents, - &rp1_clk_ops, - 0 - ), - CLK_DATA(rp1_clock_data, - .num_std_parents = 0, - .num_aux_parents = 16, - .oe_mask = BIT(5), - .ctrl_reg = CLK_GP5_CTRL, - .div_int_reg = CLK_GP5_DIV_INT, - .div_frac_reg = CLK_GP5_DIV_FRAC, - .sel_reg = CLK_GP5_SEL, - .div_int_max = DIV_INT_16BIT_MAX, - .max_freq = 100 * HZ_PER_MHZ, - .fc0_src = FC_NUM(5, 1), - ) -); +static struct rp1_clk_desc clk_gp5_desc = + REGISTER_CLK(.hw.init = CLK_HW_INIT_PARENTS_DATA( + "clk_gp5", clk_gp5_parents, &rp1_clk_ops, 0), + CLK_DATA(rp1_clock_data, .num_std_parents = 0, + .num_aux_parents = 16, .oe_mask = BIT(5), + .ctrl_reg = CLK_GP5_CTRL, + .div_int_reg = CLK_GP5_DIV_INT, + .div_frac_reg = CLK_GP5_DIV_FRAC, + .sel_reg = CLK_GP5_SEL, + .div_int_max = DIV_INT_16BIT_MAX, + .max_freq = 100 * HZ_PER_MHZ, + .fc0_src = FC_NUM(5, 1), )); static struct rp1_clk_desc *const clk_desc_array[] = { [RP1_PLL_SYS_CORE] = &pll_sys_core_desc, @@ -2346,9 +2089,11 @@ static const struct regmap_range rp1_reg_ranges[] = { regmap_reg_range(CLK_MIPI1_CFG_SEL, CLK_MIPI1_CFG_SEL), regmap_reg_range(CLK_PCIE_AUX_CTRL, CLK_PCIE_AUX_DIV_INT), regmap_reg_range(CLK_PCIE_AUX_SEL, CLK_PCIE_AUX_SEL), - regmap_reg_range(CLK_USBH0_MICROFRAME_CTRL, CLK_USBH0_MICROFRAME_DIV_INT), + regmap_reg_range(CLK_USBH0_MICROFRAME_CTRL, + CLK_USBH0_MICROFRAME_DIV_INT), regmap_reg_range(CLK_USBH0_MICROFRAME_SEL, CLK_USBH0_MICROFRAME_SEL), - regmap_reg_range(CLK_USBH1_MICROFRAME_CTRL, CLK_USBH1_MICROFRAME_DIV_INT), + regmap_reg_range(CLK_USBH1_MICROFRAME_CTRL, + CLK_USBH1_MICROFRAME_DIV_INT), regmap_reg_range(CLK_USBH1_MICROFRAME_SEL, CLK_USBH1_MICROFRAME_SEL), regmap_reg_range(CLK_USBH0_SUSPEND_CTRL, CLK_USBH0_SUSPEND_DIV_INT), regmap_reg_range(CLK_USBH0_SUSPEND_SEL, CLK_USBH0_SUSPEND_SEL), @@ -2412,8 +2157,8 @@ static int rp1_clk_probe(struct platform_device *pdev) if (IS_ERR(clockman->regs)) return PTR_ERR(clockman->regs); - clockman->regmap = devm_regmap_init_mmio(dev, clockman->regs, - &rp1_clk_regmap_cfg); + clockman->regmap = + devm_regmap_init_mmio(dev, clockman->regs, &rp1_clk_regmap_cfg); if (IS_ERR(clockman->regmap)) { dev_err_probe(dev, PTR_ERR(clockman->regmap), "could not init clock regmap\n"); |