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| author | Eric Lin <[email protected]> | 2025-02-13 01:21:39 +0000 |
|---|---|---|
| committer | Namhyung Kim <[email protected]> | 2025-03-10 21:15:38 +0000 |
| commit | 2e3a13d6b74ee0ca59b2243878b7b6e0dddbcf6b (patch) | |
| tree | 3e5d3e5068a0eee787d63f274a5d9ed4bf875497 /tools/perf/util/python.c | |
| parent | perf vendor events riscv: Add SiFive Bullet version 0x0d events (diff) | |
| download | kernel-2e3a13d6b74ee0ca59b2243878b7b6e0dddbcf6b.tar.gz kernel-2e3a13d6b74ee0ca59b2243878b7b6e0dddbcf6b.zip | |
perf vendor events riscv: Add SiFive P550 events
The SiFive Performance P550 core features an out-of-order
microarchitecture which exposes the same PMU events as Bullet,
plus events for UTLB hits and PTE cache misses/hits.
Add support for specifying these events using symbolic names.
Signed-off-by: Eric Lin <[email protected]>
Co-developed-by: Samuel Holland <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Ian Rogers <[email protected]>
Tested-by: Ian Rogers <[email protected]>
Tested-by: Atish Patra <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Namhyung Kim <[email protected]>
Diffstat (limited to 'tools/perf/util/python.c')
0 files changed, 0 insertions, 0 deletions