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| author | Eric Lin <[email protected]> | 2025-02-13 01:21:38 +0000 |
|---|---|---|
| committer | Namhyung Kim <[email protected]> | 2025-03-10 21:15:38 +0000 |
| commit | 8866a33815507485f8129b395511b8b2a0f6411d (patch) | |
| tree | 7fc8c0c4825113fa80874c94b2eca4c10dc846b5 /tools/perf/util/python.c | |
| parent | perf vendor events riscv: Add SiFive Bullet version 0x07 events (diff) | |
| download | kernel-8866a33815507485f8129b395511b8b2a0f6411d.tar.gz kernel-8866a33815507485f8129b395511b8b2a0f6411d.zip | |
perf vendor events riscv: Add SiFive Bullet version 0x0d events
SiFive Bullet microarchitecture cores with mimpid values starting with
0x0d or greater add new PMU events to count TLB miss stall cycles.
All other PMU events are unchanged from earlier Bullet cores.
Signed-off-by: Eric Lin <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Ian Rogers <[email protected]>
Tested-by: Ian Rogers <[email protected]>
Tested-by: Atish Patra <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Namhyung Kim <[email protected]>
Diffstat (limited to 'tools/perf/util/python.c')
0 files changed, 0 insertions, 0 deletions