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| author | Niravkumar L Rabara <[email protected]> | 2023-08-02 02:58:42 +0000 |
|---|---|---|
| committer | Dinh Nguyen <[email protected]> | 2023-08-08 11:32:34 +0000 |
| commit | d5f0942b5066e28138476259d076e4d6c871da7d (patch) | |
| tree | 68593ece6a1c23a4fa710dec235a37f93f0b50ef /tools/perf/scripts/python/syscall-counts.py | |
| parent | dt-bindings: reset: add reset IDs for Agilex5 (diff) | |
| download | kernel-d5f0942b5066e28138476259d076e4d6c871da7d.tar.gz kernel-d5f0942b5066e28138476259d076e4d6c871da7d.zip | |
dt-bindings: clock: add Intel Agilex5 clock manager
Add clock ID definitions for Intel Agilex5 SoCFPGA.
The registers in Agilex5 handling the clock is named as clock manager.
Signed-off-by: Teh Wen Ping <[email protected]>
Reviewed-by: Dinh Nguyen <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Niravkumar L Rabara <[email protected]>
Signed-off-by: Dinh Nguyen <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions