diff options
| author | Lad Prabhakar <[email protected]> | 2023-08-18 13:57:21 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <[email protected]> | 2023-09-01 16:08:58 +0000 |
| commit | 3e7bf4685e42786dc10a57512c8a767947f25c10 (patch) | |
| tree | 2ed56085ed67fa7ef429e4177ae807bfee6815f9 /tools/perf/builtin-script.c | |
| parent | riscv: mm: dma-noncoherent: nonstandard cache operations support (diff) | |
| download | kernel-3e7bf4685e42786dc10a57512c8a767947f25c10.tar.gz kernel-3e7bf4685e42786dc10a57512c8a767947f25c10.zip | |
dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller
Add DT binding documentation for L2 cache controller found on RZ/Five SoC.
The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
Single) from Andes. The AX45MP core has an L2 cache controller, this patch
describes the L2 cache block.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Tested-by: Conor Dooley <[email protected]> # tyre-kicking on a d1
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
Diffstat (limited to 'tools/perf/builtin-script.c')
0 files changed, 0 insertions, 0 deletions