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| author | Konrad Rzeszutek Wilk <[email protected]> | 2018-04-26 02:04:24 +0000 |
|---|---|---|
| committer | Thomas Gleixner <[email protected]> | 2018-05-03 11:55:49 +0000 |
| commit | 764f3c21588a059cd783c6ba0734d4db2d72822d (patch) | |
| tree | ce5a4674c1c99218da979ade936f043f8ca3c45e /fs/proc/array.c | |
| parent | x86/bugs: Whitelist allowed SPEC_CTRL MSR values (diff) | |
| download | kernel-764f3c21588a059cd783c6ba0734d4db2d72822d.tar.gz kernel-764f3c21588a059cd783c6ba0734d4db2d72822d.zip | |
x86/bugs/AMD: Add support to disable RDS on Fam[15,16,17]h if requested
AMD does not need the Speculative Store Bypass mitigation to be enabled.
The parameters for this are already available and can be done via MSR
C001_1020. Each family uses a different bit in that MSR for this.
[ tglx: Expose the bit mask via a variable and move the actual MSR fiddling
into the bugs code as that's the right thing to do and also required
to prepare for dynamic enable/disable ]
Suggested-by: Borislav Petkov <[email protected]>
Signed-off-by: Konrad Rzeszutek Wilk <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Ingo Molnar <[email protected]>
Diffstat (limited to 'fs/proc/array.c')
0 files changed, 0 insertions, 0 deletions