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authorDmitry Baryshkov <[email protected]>2021-03-31 10:57:19 +0000
committerRob Clark <[email protected]>2021-04-07 18:05:45 +0000
commit076437c9e360737c85d443bbf81d5ea02b3d182d (patch)
tree20a0c62b459a63d149a41fb5b98b243fbfd24cfb /drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
parentdrm/msm/dsi: drop global msm_dsi_phy_type enumaration (diff)
downloadkernel-076437c9e360737c85d443bbf81d5ea02b3d182d.tar.gz
kernel-076437c9e360737c85d443bbf81d5ea02b3d182d.zip
drm/msm/dsi: move min/max PLL rate to phy config
Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Tested-by: Stephen Boyd <[email protected]> # on sc7180 lazor Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/phy/dsi_phy.h')
-rw-r--r--drivers/gpu/drm/msm/dsi/phy/dsi_phy.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 39abb86446f9..000e4207dabc 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -38,6 +38,9 @@ struct msm_dsi_phy_cfg {
struct msm_dsi_phy_ops ops;
const struct msm_dsi_pll_ops pll_ops;
+ unsigned long min_pll_rate;
+ unsigned long max_pll_rate;
+
/*
* Each cell {phy_id, pll_id} of the truth table indicates
* if the source PLL selection bit should be set for each PHY.