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authorDmitry Baryshkov <[email protected]>2021-03-31 10:57:18 +0000
committerRob Clark <[email protected]>2021-04-07 18:05:45 +0000
commit80d2229bf0e7b169a1ab3adcaed9c4ce336f50b2 (patch)
tree793ccadd2370a7a81c0f29c1b54d2427b3e72a0c /drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
parentdrm/msm/dsi: move all PLL callbacks into PHY config struct (diff)
downloadkernel-80d2229bf0e7b169a1ab3adcaed9c4ce336f50b2.tar.gz
kernel-80d2229bf0e7b169a1ab3adcaed9c4ce336f50b2.zip
drm/msm/dsi: drop global msm_dsi_phy_type enumaration
With the current upstream driver the msm_dsi_phy_type enum does not make much sense: all DSI PHYs are probed using the dt bindings, the phy type is not passed between drivers. Use quirks in phy individual PHY drivers to differentiate minor harware differences and drop the enum. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Tested-by: Stephen Boyd <[email protected]> # on sc7180 lazor Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/phy/dsi_phy.h')
-rw-r--r--drivers/gpu/drm/msm/dsi/phy/dsi_phy.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 244d2c900d40..39abb86446f9 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -13,9 +13,6 @@
#define dsi_phy_read(offset) msm_readl((offset))
#define dsi_phy_write(offset, data) msm_writel((data), (offset))
-/* v3.0.0 10nm implementation that requires the old timings settings */
-#define V3_0_0_10NM_OLD_TIMINGS_QUIRK BIT(0)
-
struct msm_dsi_phy_ops {
int (*pll_init)(struct msm_dsi_phy *phy);
int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
@@ -37,7 +34,6 @@ struct msm_dsi_pll_ops {
};
struct msm_dsi_phy_cfg {
- enum msm_dsi_phy_type type;
struct dsi_reg_config reg_cfg;
struct msm_dsi_phy_ops ops;
const struct msm_dsi_pll_ops pll_ops;