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| author | Mika Kuoppala <[email protected]> | 2018-12-05 13:46:12 +0000 |
|---|---|---|
| committer | Mika Kuoppala <[email protected]> | 2018-12-07 12:05:34 +0000 |
| commit | d8f505311717cfc2033c44a8b26ba96c66187303 (patch) | |
| tree | 06fcae5993042cfef0a4b2fd12a566403afc68f5 /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | drm/i915/execlists: Apply a full mb before execution for Braswell (diff) | |
| download | kernel-d8f505311717cfc2033c44a8b26ba96c66187303.tar.gz kernel-d8f505311717cfc2033c44a8b26ba96c66187303.zip | |
drm/i915/icl: Forcibly evict stale csb entries
Gen11 fails to deliver wrt global observation point on
tail/entry updates and we sometimes see old entry.
Use clflush to forcibly evict our possibly stale copy
of the cacheline in hopes that we get fresh one from gpu.
Obviously there is something amiss in the coherency protocol so
this can be consired as a workaround until real cause
is found.
The working hardware will do the evict without our cue anyways,
so the cost in there should be ameliorated by that fact.
v2: for next pass, s/flush/evict, add reset (Chris)
References: https://bugzilla.freedesktop.org/show_bug.cgi?id=108315
Cc: Chris Wilson <[email protected]>
Signed-off-by: Mika Kuoppala <[email protected]>
Reviewed-by: Chris Wilson <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
0 files changed, 0 insertions, 0 deletions