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| author | Chris Wilson <[email protected]> | 2018-12-06 08:44:31 +0000 |
|---|---|---|
| committer | Chris Wilson <[email protected]> | 2018-12-06 21:12:30 +0000 |
| commit | 490b8c65b9db45896769e1095e78725775f47b3e (patch) | |
| tree | f870c0ef4565072da1c43a5cebd55612340074ee /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | drm/i915/execlists: Move RCS mmio workaround to new common wa_list (diff) | |
| download | kernel-490b8c65b9db45896769e1095e78725775f47b3e.tar.gz kernel-490b8c65b9db45896769e1095e78725775f47b3e.zip | |
drm/i915/execlists: Apply a full mb before execution for Braswell
Braswell is really picky about having our writes posted to memory before
we execute or else the GPU may see stale values. A wmb() is insufficient
as it only ensures the writes are visible to other cores, we need a full
mb() to ensure the writes are in memory and visible to the GPU.
The most frequent failure in flushing before execution is that we see
stale PTE values and execute the wrong pages.
References: 987abd5c62f9 ("drm/i915/execlists: Force write serialisation into context image vs execution")
Signed-off-by: Chris Wilson <[email protected]>
Cc: Mika Kuoppala <[email protected]>
Cc: Tvrtko Ursulin <[email protected]>
Cc: Joonas Lahtinen <[email protected]>
Cc: [email protected]
Reviewed-by: Tvrtko Ursulin <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
0 files changed, 0 insertions, 0 deletions