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| author | Rodrigo Vivi <[email protected]> | 2024-12-19 21:00:19 +0000 |
|---|---|---|
| committer | Tvrtko Ursulin <[email protected]> | 2024-12-24 09:41:03 +0000 |
| commit | 20e7c5313ffbf11c34a46395345677adbe890bee (patch) | |
| tree | 878c8c222774b3258c01594eaeba9bf298f1de63 /drivers/fpga/xilinx-spi.c | |
| parent | drm/i915/cx0_phy: Fix C10 pll programming sequence (diff) | |
| download | kernel-20e7c5313ffbf11c34a46395345677adbe890bee.tar.gz kernel-20e7c5313ffbf11c34a46395345677adbe890bee.zip | |
drm/i915/dg1: Fix power gate sequence.
sub-pipe PG is not present on DG1. Setting these bits can disable
other power gates and cause GPU hangs on video playbacks.
VLK: 16314, 4304
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13381
Fixes: 85a12d7eb8fe ("drm/i915/tgl: Fix Media power gate sequence.")
Cc: Vinay Belgaumkar <[email protected]>
Cc: Himal Prasad Ghimiray <[email protected]>
Reviewed-by: Vinay Belgaumkar <[email protected]>
Reviewed-by: Himal Prasad Ghimiray <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Signed-off-by: Rodrigo Vivi <[email protected]>
(cherry picked from commit de7061947b4ed4be857d452c60d5fb795831d79e)
Signed-off-by: Tvrtko Ursulin <[email protected]>
Diffstat (limited to 'drivers/fpga/xilinx-spi.c')
0 files changed, 0 insertions, 0 deletions