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| author | Suraj Kandpal <[email protected]> | 2024-12-16 18:15:54 +0000 |
|---|---|---|
| committer | Tvrtko Ursulin <[email protected]> | 2024-12-24 09:41:00 +0000 |
| commit | 385a95cc72941c7f88630a7bc4176048cc03b395 (patch) | |
| tree | 65c45c31b36ba51e9d0809c871593df8aea97c1b /drivers/fpga/xilinx-spi.c | |
| parent | Linux 6.13-rc4 (diff) | |
| download | kernel-385a95cc72941c7f88630a7bc4176048cc03b395.tar.gz kernel-385a95cc72941c7f88630a7bc4176048cc03b395.zip | |
drm/i915/cx0_phy: Fix C10 pll programming sequence
According to spec VDR_CUSTOM_WIDTH register gets programmed after pll
specific VDR registers and TX Lane programming registers are done.
Moreover we only program into C10_VDR_CONTROL1 to update config and
setup master lane once all VDR registers are written into.
Bspec: 67636
Fixes: 51390cc0e00a ("drm/i915/mtl: Add Support for C10 PHY message bus and pll programming")
Signed-off-by: Suraj Kandpal <[email protected]>
Reviewed-by: Ankit Nautiyal <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
(cherry picked from commit f9d418552ba1e3a0e92487ff82eb515dab7516c0)
Signed-off-by: Tvrtko Ursulin <[email protected]>
Diffstat (limited to 'drivers/fpga/xilinx-spi.c')
0 files changed, 0 insertions, 0 deletions