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| author | Ciprian Marian Costea <[email protected]> | 2025-01-13 12:07:04 +0000 |
|---|---|---|
| committer | Marc Kleine-Budde <[email protected]> | 2025-02-19 10:09:07 +0000 |
| commit | 8503a4b1a24d32e95f3a233062e8f1dc0b2052bd (patch) | |
| tree | 7038027d4999fdcb8926dace584eb072b3695440 /arch/powerpc/lib/code-patching.c | |
| parent | can: flexcan: Add quirk to handle separate interrupt lines for mailboxes (diff) | |
| download | kernel-8503a4b1a24d32e95f3a233062e8f1dc0b2052bd.tar.gz kernel-8503a4b1a24d32e95f3a233062e8f1dc0b2052bd.zip | |
can: flexcan: add NXP S32G2/S32G3 SoC support
Add device type data for S32G2/S32G3 SoC.
FlexCAN module from S32G2/S32G3 is similar with i.MX SoCs, but interrupt
management is different.
On S32G2/S32G3 SoC, there are separate interrupts for state change, bus
errors, Mailboxes 0-7 and Mailboxes 8-127 respectively.
In order to handle this FlexCAN hardware particularity, first reuse the
'FLEXCAN_QUIRK_NR_IRQ_3' quirk provided by mcf5441x's irq handling
support. Secondly, use the newly introduced
'FLEXCAN_QUIRK_SECONDARY_MB_IRQ' quirk which handles the case where two
separate mailbox ranges are controlled by independent hardware interrupt
lines.
Signed-off-by: Ciprian Marian Costea <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Marc Kleine-Budde <[email protected]>
Diffstat (limited to 'arch/powerpc/lib/code-patching.c')
0 files changed, 0 insertions, 0 deletions