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path: root/drivers/pci/controller/pcie-brcmstb.c
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* Merge tag 'v6.17'saturneric2025-10-161-26/+51
|\ | | | | | | Linux 6.17
| * Merge branch 'pci/misc'Bjorn Helgaas2025-07-311-1/+1
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | - Remove resolved hotplug TODO item (Guilherme Giacomo Simoes) - Fix typos (Bjorn Helgaas) * pci/misc: PCI: Fix typos PCI: hotplug: Remove TODO about unused .get_power(), .hardware_test()
| | * PCI: Fix typosBjorn Helgaas2025-07-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix typos. Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Thomas Gleixner <[email protected]> Link: https://patch.msgid.link/[email protected]
| * | Merge branch 'pci/controller/brcmstb'Bjorn Helgaas2025-07-311-6/+27
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add optional DT 'num-lanes' property and if present, use it to override the Maximum Link Width advertised in Link Capabilities (Jim Quinlan) * pci/controller/brcmstb: PCI: brcmstb: Replace open coded value with PCIE_T_RRS_READY_MS MAINTAINERS: Drop Nicolas from maintaining pcie-brcmstb PCI: brcmstb: Set MLW based on "num-lanes" DT property if present dt-bindings: PCI: brcm,stb-pcie: Add num-lanes property
| | * | PCI: brcmstb: Replace open coded value with PCIE_T_RRS_READY_MSFlorian Fainelli2025-07-171-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The delay that we are waiting on in brcm_pcie_start_link() is PCIE_T_RRS_READY_MS, use it. Signed-off-by: Florian Fainelli <[email protected]> [mani: Removed the redundant comment] Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://patch.msgid.link/[email protected]
| | * | PCI: brcmstb: Set MLW based on "num-lanes" DT property if presentJim Quinlan2025-06-231-1/+26
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default, the driver relies on the default hardware defined value for the Max Link Width (MLW) capability. But if the "num-lanes" DT property is present, assume that the chip's default capability information is incorrect or undesired, and use the specified value instead. Signed-off-by: Jim Quinlan <[email protected]> [mani: reworded the description and comments] Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Link: https://patch.msgid.link/[email protected]
| * / PCI: brcmstb: Switch to msi_create_parent_irq_domain()Nam Cao2025-07-241-23/+22
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain() which was using legacy MSI domain setup. Signed-off-by: Nam Cao <[email protected]> [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <[email protected]> [bhelgaas: rebase on dev_fwnode() conversion, drop fwnode local var] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Thomas Gleixner <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Link: https://patch.msgid.link/fa72703e06c2ee2c7554082c7152913eb0dd294f.1750858083.git.namcao@linutronix.de
* | Merge tag 'v6.16-rc1'saturneric2025-06-111-2/+2
|\| | | | | | | Linux 6.16-rc1
| * PCI: Switch to irq_domain_create_linear()Jiri Slaby (SUSE)2025-05-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | irq_domain_add_linear() is going away as being obsolete now. Switch to the preferred irq_domain_create_linear(). That differs in the first parameter: It takes more generic struct fwnode_handle instead of struct device_node. Therefore, of_fwnode_handle() is added around the parameter. Note some of the users can likely use dev->fwnode directly instead of indirect of_fwnode_handle(dev->of_node). But dev->fwnode is not guaranteed to be set for all, so this has to be investigated on case to case basis (by people who can actually test with the HW). [ tglx: Fix up subject prefix and convert the new instance in dwc/pcie-amd-mdb.c ] Signed-off-by: Jiri Slaby (SUSE) <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/all/[email protected]
| * irqdomain: pci: Switch to of_fwnode_handle()Jiri Slaby (SUSE)2025-04-071-1/+1
| | | | | | | | | | | | | | | | | | | | of_node_to_fwnode() is irqdomain's reimplementation of the "officially" defined of_fwnode_handle(). The former is in the process of being removed, so use the latter instead. Signed-off-by: Jiri Slaby (SUSE) <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Link: https://patch.msgid.link/[email protected]
* | fix: compile and make rpi 5 work properlysaturneric2025-04-211-495/+575
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* | Merge remote-tracking UNTIL 21. Apr. 2025saturneric2025-04-211-87/+132
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| * Merge branch 'pci/misc'Bjorn Helgaas2025-03-271-2/+2
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Remove unused tools 'pci' build target left over after moving tests to tools/testing/selftests/pci_endpoint (Jianfeng Liu) - Fix typos and whitespace errors (Bjorn Helgaas) * pci/misc: PCI: Fix typos tools/Makefile: Remove pci target # Conflicts: # drivers/pci/endpoint/functions/pci-epf-test.c
| | * PCI: Fix typosBjorn Helgaas2025-03-081-2/+2
| | | | | | | | | | | | | | | | | | | | | Fix typos and whitespace errors. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Helgaas <[email protected]>
| * | PCI: brcmstb: Make const read-only arrays staticColin Ian King2025-03-231-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't populate the const read-only arrays "data" and "regs" on the stack at run time, instead make them static. Signed-off-by: Colin Ian King <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> [kwilczynski: commit log, wrap overly long line to 80 columns] Signed-off-by: Krzysztof Wilczyński <[email protected]> Link: https://lore.kernel.org/r/[email protected]
| * | PCI: brcmstb: Make irq_domain_set_info() parameter cast explicitJim Quinlan2025-03-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the cast to the irq_hw_number_t type for the parameter passed to irq_domain_set_info() function explicit. Signed-off-by: Jim Quinlan <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]>
| * | PCI: brcmstb: Make two changes in MDIO register fieldsJim Quinlan2025-03-041-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hardware has been updated with two changes to the MDIO packet format. The CMD field used to be 12 bits and now is only 1 bit. This change is backwards compatible because the field's starting bit position is unchanged, and the only commands we've used have values 0 and 1. The PORT field's width has been changed from 4 bits to 5 bits. When written, the new bit is not contiguous with the other four. However, this change is backwards compatible because the driver never used anything other than 0 for the port field's value. Thus, update the existing code to handle new changes to the hardware in a backwards-compatible manner. Signed-off-by: Jim Quinlan <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]>
| * | PCI: brcmstb: Use same constant table for config space accessJim Quinlan2025-03-041-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The constants EXT_CFG_DATA and EXT_CFG_INDEX vary by SoC, where one of the map_bus methods used these constants, and the other used a different set of constants. Thankfully, there was no problem because the SoCs that used the latter map_bus method all had the same register constants. Thus, remove redundant constants and adjust the code to use the correct constants accordingly. While at it, update the value of EXT_CFG_DATA to use the 4k-page based configuration space access system, which is what the second map_bus method was already using. Signed-off-by: Jim Quinlan <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Link: https://lore.kernel.org/r/[email protected] [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]>
| * | PCI: brcmstb: Fix potential premature regulator disablingJim Quinlan2025-03-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The platform supports enabling and disabling regulators only on ports below the Root Complex. Thus, we need to verify this both when adding and removing the bus, otherwise regulators may be disabled prematurely when a bus further down the topology is removed. Fixes: 9e6be018b263 ("PCI: brcmstb: Enable child bus device regulators from DT") Signed-off-by: Jim Quinlan <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]>
| * | PCI: brcmstb: Fix error path after a call to regulator_bulk_get()Jim Quinlan2025-03-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the regulator_bulk_get() returns an error and no regulators are created, we need to set their number to zero. If we don't do this and the PCIe link up fails, a call to the regulator_bulk_free() will result in a kernel panic. While at it, print the error value, as we cannot return an error upwards as the kernel will WARN() on an error from add_bus(). Fixes: 9e6be018b263 ("PCI: brcmstb: Enable child bus device regulators from DT") Signed-off-by: Jim Quinlan <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Link: https://lore.kernel.org/r/[email protected] [kwilczynski: commit log, use comma in the message to match style with other similar messages] Signed-off-by: Krzysztof Wilczyński <[email protected]>
| * | PCI: brcmstb: Do not assume that register field starts at LSBJim Quinlan2025-03-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When setting the LNKCAP and LNKCTL2 register fields, it was assumed that the field started at the LSB of the register. Although the masks do indeed start at the LSB, and this will probably not change, it is prudent to use a method that makes no assumption about the mask's placement in the register. Thus, use the u{16,32}p_replace_bits() helpers since they are already wildly used in this driver. Signed-off-by: Jim Quinlan <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]>
| * | PCI: brcmstb: Use internal register to change link capabilityJim Quinlan2025-03-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver has been mistakenly writing to a read-only (RO) configuration space register (PCI_EXP_LNKCAP) to change the PCIe link capability. Although harmless in this case, the proper write destination is an internal register that is reflected by PCI_EXP_LNKCAP. Thus, fix the brcm_pcie_set_gen() function to correctly update the link capability. Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver") Signed-off-by: Jim Quinlan <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]>
| * | PCI: brcmstb: Set generation limit before PCIe link upJim Quinlan2025-03-041-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the user elects to limit the PCIe generation via the appropriate devicetree property, apply the settings before the PCIe link up, not after. Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver") Signed-off-by: Jim Quinlan <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]>
| * | PCI: brcmstb: Add BCM2712 supportStanimir Varbanov2025-03-041-2/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a bare minimum amount of changes in order to support PCIe Root Complex hardware IP found on RPi5. The PCIe controller on BCM2712 is based on BCM7712 and as such it inherits register offsets, PERST# assertion, bridge_reset ops, and inbound windows count. Although, the implementation for BCM2712 needs a workaround related to the control of the bridge_reset where turning off of the Root Port must not shutdown the bridge_reset and this must be avoided. To implement this workaround a quirks field is introduced in pcie_cfg_data struct. The controller also needs adjustment of PHY PLL setup to use a 54MHz input refclk. The default input reference clock for the PHY PLL is 100Mhz, except for some devices where it is 54Mhz like BCM2712C1 and BCM2712D0. To implement those adjustments introduce a new .post_setup op in pcie_cfg_data and call it at the end of brcm_pcie_setup function. The BCM2712 .post_setup callback implements the required MDIO writes that switch the PLL refclk and also change PHY PM clock period. Without this RPi5 PCIex1 is unable to enumerate endpoint devices on the expansion connector. Signed-off-by: Stanimir Varbanov <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Jim Quinlan <[email protected]> Tested-by: Ivan T. Ivanov <[email protected]> Link: https://lore.kernel.org/r/[email protected] [commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]>
| * | PCI: brcmstb: Expand inbound window size up to 64GBStanimir Varbanov2025-02-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BCM2712 memory map can support up to 64GB of system memory, thus expand the inbound window size in calculation helper function. The change is safe for the currently supported SoCs that have smaller inbound window sizes. Signed-off-by: Stanimir Varbanov <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Jim Quinlan <[email protected]> Tested-by: Ivan T. Ivanov <[email protected]> Link: https://lore.kernel.org/r/[email protected] [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]>
| * | PCI: brcmstb: Reuse pcie_cfg_data structureStanimir Varbanov2025-02-281-40/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of copying fields from the pcie_cfg_data structure to brcm_pcie, reference it directly. Signed-off-by: Stanimir Varbanov <[email protected]> Reviewed-by: Florian Fainelil <[email protected]> Reviewed-by: Jim Quinlan <[email protected]> Tested-by: Ivan T. Ivanov <[email protected]> Link: https://lore.kernel.org/r/[email protected] [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]>
| * | PCI: brcmstb: Add a softdep to MIP MSI-X driverStanimir Varbanov2025-02-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Then the brcmstb PCIe driver and MIP MSI-X interrupt controller drivers are built as modules there could be a race in probing. To avoid this, add a softdep to MIP driver to guarantee that MIP driver will be load first. Signed-off-by: Stanimir Varbanov <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Tested-by: Ivan T. Ivanov <[email protected]> Link: https://lore.kernel.org/r/[email protected] [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]>
| * | PCI: brcmstb: Fix missing of_node_put() in brcm_pcie_probe()Stanimir Varbanov2025-02-241-4/+9
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A call to of_parse_phandle() is incrementing the refcount, and as such, the of_node_put() must be called when the reference is no longer needed. Thus, refactor the existing code and add a missing of_node_put() call following the check to ensure that "msi_np" matches "pcie->np" and after MSI initialization, but only if the MSI support is enabled system-wide. Cc: [email protected] # v5.10+ Fixes: 40ca1bf580ef ("PCI: brcmstb: Add MSI support") Signed-off-by: Stanimir Varbanov <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]>
* / fix: drivers patch make raspberry pi 5 work properlysaturneric2025-01-121-32/+551
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* PCI: controller: Switch back to struct platform_driver::remove()Sergio Paracuellos2024-10-031-1/+1
| | | | | | | | | | | | | | | | | After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all PCI controller drivers to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sergio Paracuellos <[email protected]> [bhelgaas: add pcie-xilinx-nwl.c and tidy whitespace per Uwe Kleine-König: https://lore.kernel.org/r/tdxrmmqyzcufupnwkdbg7lwgadizm7v3lxjirykijbml7x54ze@upbdzycdsilm] Signed-off-by: Bjorn Helgaas <[email protected]>
* Merge branch 'pci/controller/brcmstb'Bjorn Helgaas2024-09-191-158/+403
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Change DT binding maintainer to Jim Quinlan (Jim Quinlan) - Add DT binding maxItems for reset controllers (Jim Quinlan) - Refactor .probe() error handling (Jim Quinlan) - Use the 'bridge' reset method if described in the DT (Jim Quinlan) - Use the 'swinit' reset method if described in the DT (Jim Quinlan) - Add SoC-specific HARD_DEBUG, INTR2_CPU_BASE register offsets (Jim Quinlan) - Drop unused RGR1_SW_INIT_1_INIT_MASK, RGR1_SW_INIT_1_INIT_SHIFT offsets (Jim Quinlan) - Add 'has_phy' so the existence of a 'rescal' reset controller doesn't imply software control of it (Jim Quinlan) - Add support for many inbound DMA windows (Jim Quinlan) - Check return values of all reset_control_*() calls (Jim Quinlan) - Rename SoC 'type' to 'soc_base' express the fact that SoCs come in families of multiple similar devices (Jim Quinlan) - Add Broadcom 7712 DT description and driver support (Jim Quinlan) - Sort enums, pcie_offsets[], pcie_cfg_data, .compatible strings for maintainability (Bjorn Helgaas) * pci/controller/brcmstb: PCI: brcmstb: Sort enums, pcie_offsets[], pcie_cfg_data, .compatible strings PCI: brcmstb: Enable 7712 SoCs PCI: brcmstb: Change field name from 'type' to 'soc_base' PCI: brcmstb: Check return value of all reset_control_* calls PCI: brcmstb: Refactor for chips with many regular inbound windows PCI: brcmstb: Don't conflate the reset rescal with PHY ctrl PCI: brcmstb: Remove two unused constants from driver PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific PCI: brcmstb: Use swinit reset if available PCI: brcmstb: Use bridge reset if available PCI: brcmstb: Use common error handling code in brcm_pcie_probe() dt-bindings: PCI: brcm,stb-pcie: Add 7712 SoC description dt-bindings: PCI: brcm,stb-pcie: Use maxItems for reset controllers dt-bindings: PCI: brcm,stb-pcie: Change brcmstb maintainer and cleanup
| * PCI: brcmstb: Sort enums, pcie_offsets[], pcie_cfg_data, .compatible stringsBjorn Helgaas2024-09-101-45/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sort enum pcie_soc_base values. Rename pcie_offsets_bmips_7425[] to pcie_offsets_bcm7425[] to match BCM7425 pcie_soc_base enum, bcm7425_cfg, and "brcm,bcm7425-pcie" .compatible string. Rename pcie_offset_bcm7278[] to pcie_offsets_bcm7278[] to match other "pcie_offsets" names. Rename pcie_offset_bcm7712[] to pcie_offsets_bcm7712[] to match other "pcie_offsets" names. Sort pcie_offsets_*[] by SoC name, move them all together, indent values for easy reading. Sort pcie_cfg_data structs by SoC name. Sort .compatible strings by SoC name. No functional change intended. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Florian Fainelli <[email protected]>
| * PCI: brcmstb: Enable 7712 SoCsJim Quinlan2024-09-071-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Broadcom STB 7712 is the sibling chip of the RPi 5 (2712). It has one PCIe controller with a single port, supports gen2 and one lane only. The current revision of the chip is "C0" or "C1". Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jim Quinlan <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Stanimir Varbanov <[email protected]>
| * PCI: brcmstb: Change field name from 'type' to 'soc_base'Jim Quinlan2024-09-071-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'type' field used in the driver to discern SoC differences is confusing; change it to the more apt 'soc_base'. The 'base' is because some SoCs have the same characteristics as previous SoCs so it is convenient to classify them in the same group. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jim Quinlan <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * PCI: brcmstb: Check return value of all reset_control_* callsJim Quinlan2024-09-071-30/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Always check the return value for invocations of reset_control_xxx() and propagate the error to the next level. Although the current functions in reset-brcmstb.c cannot fail, this may someday change. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jim Quinlan <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Stanimir Varbanov <[email protected]>
| * PCI: brcmstb: Refactor for chips with many regular inbound windowsJim Quinlan2024-09-071-54/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide support for new chips with multiple inbound windows while keeping the legacy support for the older chips. In existing chips there are three inbound windows with fixed purposes: the first was for mapping SoC internal registers, the second was for memory, and the third was for memory but with the endian swapped. Typically, only one window was used. Complicating the inbound window usage was the fact that the PCIe HW would do a baroque internal mapping of system memory, and concatenate the regions of multiple memory controllers. Newer chips such as the 7712 and Cable Modem SoCs take a step forward and drop the internal mapping while providing for multiple inbound windows. This works in concert with the dma-ranges property, where each provided range becomes an inbound window. Link: https://lore.kernel.org/linux-pci/[email protected] Co-developed-by: Riyan Dhiman <[email protected]> Signed-off-by: Riyan Dhiman <[email protected]> Signed-off-by: Jim Quinlan <[email protected]> [kwilczynski: commit log, wrap code comments to 80 columns] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Stanimir Varbanov <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
| * PCI: brcmstb: Don't conflate the reset rescal with PHY ctrlJim Quinlan2024-09-041-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a "has_phy" field indicating that the internal PHY has SW control that requires configuration. Some previous chips only required the firing of the "rescal" reset controller. This change requires us to give the 7216 SoC its own cfg_data structure. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jim Quinlan <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Tested-by: Florian Fainelli <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Stanimir Varbanov <[email protected]>
| * PCI: brcmstb: Remove two unused constants from driverJim Quinlan2024-09-041-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove two constants in the driver which are no longer used: RGR1_SW_INIT_1_INIT_MASK and RGR1_SW_INIT_1_INIT_SHIFT. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Tested-by: Florian Fainelli <[email protected]> Reviewed-by: Stanimir Varbanov <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]>
| * PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specificJim Quinlan2024-09-041-15/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do preparatory work for the 7712 SoC, which is introduced in a future commit. Our HW design has changed two register offsets for the 7712, where previously it was a common value for all Broadcom SoCs with PCIe cores. Specifically, the two offsets are to the registers HARD_DEBUG and INTR2_CPU_BASE. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jim Quinlan <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Tested-by: Florian Fainelli <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Stanimir Varbanov <[email protected]>
| * PCI: brcmstb: Use swinit reset if availableJim Quinlan2024-09-041-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | The 7712 SoC adds a software init reset device for the PCIe HW. If found in the DT node, use it. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
| * PCI: brcmstb: Use bridge reset if availableJim Quinlan2024-09-041-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 7712 SoC has a bridge reset which can be described in the device tree. Use it if present. Otherwise, continue to use the legacy method to reset the bridge. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jim Quinlan <[email protected]> [kwilczynski: commit log, refactored function brcm_pcie_bridge_sw_init_set_generic()] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Stanimir Varbanov <[email protected]>
| * PCI: brcmstb: Use common error handling code in brcm_pcie_probe()Jim Quinlan2024-09-041-13/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the error handling in the bottom half of the probe function for readability. The invocation of clk_prepare_enable() is moved lower in the function and this simplifies a couple of return paths. The dev_err_probe() is also used when it is apt. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jim Quinlan <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
* | PCI: brcmstb: Silence 'set affinity failed' warningMarek Vasut2024-07-291-9/+2
|/ | | | | | | | | | | | | | | | | Use MSI_FLAG_NO_AFFINITY, which keeps .irq_set_affinity() unset and allows migrate_one_irq() to exit right away, without warnings like this: IRQ...: set affinity failed(-22) Remove the .irq_set_affinity() implementation that is no longer needed. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Marek Vasut <[email protected]> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Acked-by: Thomas Gleixner <[email protected]>
* PCI: brcmstb: Fix broken brcm_pcie_mdio_write() pollingJonathan Bell2024-03-101-1/+1
| | | | | | | | | | | | | | The MDIO_WT_DONE() macro tests bit 31, which is always 0 (== done) as readw_poll_timeout_atomic() does a 16-bit read. Replace with the readl variant. [kwilczynski: commit log] Fixes: ca5dcc76314d ("PCI: brcmstb: Replace status loops with read_poll_timeout_atomic()") Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jonathan Bell <[email protected]> Signed-off-by: Stefan Wahren <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Acked-by: Florian Fainelli <[email protected]>
* PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream deviceJim Quinlan2024-01-111-10/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Broadcom STB/CM PCIe HW core, which is also used in RPi SOCs, must be deliberately set by the PCIe RC HW into one of three mutually exclusive modes: "safe" -- No CLKREQ# expected or required, refclk is always provided. This mode should work for all devices but is not be capable of any refclk power savings. "no-l1ss" -- CLKREQ# is expected to be driven by the downstream device for CPM and ASPM L0s and L1. Provides Clock Power Management, L0s, and L1, but cannot provide L1 substate (L1SS) power savings. If the downstream device connected to the RC is L1SS capable AND the OS enables L1SS, all PCIe traffic may abruptly halt, potentially hanging the system. "default" -- Bidirectional CLKREQ# between the RC and downstream device. Provides ASPM L0s, L1, and L1SS, but not compliant to provide Clock Power Management; specifically, may not be able to meet the T_CLRon max timing of 400ns as specified in "Dynamic Clock Control", section 3.2.5.2.2 of the PCIe Express Mini CEM 2.1 specification. This situation is atypical and should happen only with older devices. Previously, this driver always set the mode to "no-l1ss", as almost all STB/CM boards operate in this mode. But now there is interest in activating L1SS power savings from STB/CM customers, which requires "aspm" mode. In addition, a bug was filed for RPi4 CM platform because most devices did not work in "no-l1ss" mode. Note that the mode is specified by the DT property "brcm,clkreq-mode". If this property is omitted, then "default" mode is chosen. Note: Since L1 substates are now possible, a modification was made regarding an internal bus timeout: During long periods of the PCIe RC HW being in an L1SS sleep state, there may be a timeout on an internal bus access, even though there may not be any PCIe access involved. Such a timeout will cause a subsequent CPU abort. Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217276 Link: https://lore.kernel.org/linux-pci/[email protected] Tested-by: Cyril Brulebois <[email protected]> Tested-by: Florian Fainelli <[email protected]> Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]>
* PCI: brcmstb: Remove stale commentJim Quinlan2023-08-241-1/+0
| | | | | | | | | | | | | A comment says that Multi-MSI is not supported by the driver. A past commit [1] added this feature, so the comment is incorrect and is removed. [1] commit 198acab1772f22f2 ("PCI: brcmstb: Enable Multi-MSI") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Florian Fainelli <[email protected]>
* PCI: brcmstb: Assert PERST# on BCM2711Jim Quinlan2023-08-241-0/+5
| | | | | | | | | | | The current PCIe driver assumes PERST# is asserted when probe() is invoked. Some older versions of the 2711/RPi bootloader left PERST# unasserted, as the Raspian OS does assert PERST# on probe(). For this reason, we assert PERST# for BCM2711 SOCs (i.e. RPi). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
* PCI: brcmstb: Convert to platform remove callback returning voidUwe Kleine-König2023-06-241-4/+2
| | | | | | | | | | | | | | | | | | The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Uwe Kleine-König <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Acked-by: Florian Fainelli <[email protected]>
* PCI: brcmstb: Set RCB_{MPS,64B}_MODE bitsJim Quinlan2022-11-111-1/+8
| | | | | | | | | | | | | | Set RCB_MPS mode bit so that data for PCIe read requests up to the size of the Maximum Payload Size (MPS) are returned in one completion, and data for PCIe read requests greater than the MPS are split at the specified Read Completion Boundary setting. Set RCB_64B so that the Read Compeletion Boundary is 64B. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Florian Fainelli <[email protected]>
* PCI: brcmstb: Drop needless 'inline' annotationsJim Quinlan2022-11-111-6/+6
| | | | | | | | | | | A number of inline functions are called rarely and/or are not time-critical. Take out the "inline" and let the compiler do its work. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jim Quinlan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Bjorn Helgaas <[email protected]> Acked-by: Florian Fainelli <[email protected]>
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