kernel - saturneric's kernel source tree

	Commit message (Collapse)	Author	Age	Files	Lines
*	PCI: qcom: Add RX lane margining settings for 16.0 GT/s	Shashank Babu Chinta Venkata	2024-09-13	1	-0/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Add RX lane margining settings for 16.0 GT/s (GEN 4) data rate. These settings improve link stability while operating at high date rates and helps to improve signal quality. Link: https://lore.kernel.org/linux-pci/[email protected] Tested-by: Johan Hovold <[email protected]> Signed-off-by: Shashank Babu Chinta Venkata <[email protected]> [mani: dropped the code refactoring and minor changes] Signed-off-by: Manivannan Sadhasivam <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
*	PCI: qcom: Add equalization settings for 16.0 GT/s	Shashank Babu Chinta Venkata	2024-09-13	1	-0/+13
	During high data transmission rates such as 16.0 GT/s, there is an increased risk of signal loss due to poor channel quality and interference. This can impact receiver's ability to capture signals accurately. Hence, as signal compensation is achieved through appropriate lane equalization, apply lane equalization settings at both transmitter and receiver which results in an increase in the PCIe signal strength. While at it, modify the pcie-tegra194 driver to make use of the common GEN3_EQ_CONTROL_OFF definitions in pcie-designware.h. Link: https://lore.kernel.org/linux-pci/[email protected] Tested-by: Johan Hovold <[email protected]> Signed-off-by: Shashank Babu Chinta Venkata <[email protected]> [mani: dropped the code refactoring and minor changes] Signed-off-by: Manivannan Sadhasivam <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>