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path: root/drivers/iommu/intel/cache.c
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* Merge tag 'iommu-updates-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2025-07-301-44/+11
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| * iommu/vt-d: Deduplicate cache_tag_flush_all by reusing flush_rangeEthan Milon2025-07-141-26/+8
| * iommu/vt-d: Fix missing PASID in dev TLB flush with cache_tag_flush_allEthan Milon2025-07-141-17/+1
| * iommu/vt-d: Create unique domain ops for each stageJason Gunthorpe2025-07-141-2/+3
* | iommu/vt-d: Assign devtlb cache tag on ATS enablementLu Baolu2025-07-041-3/+2
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* iommu/vt-d: Link cache tags of same iommu unit togetherZhenzhong Duan2025-01-071-1/+10
* iommu/vt-d: Fix qi_batch NULL pointer with nested parent domainYi Liu2024-12-131-7/+27
* iommu/vt-d: Introduce batched cache invalidationTina Zhang2024-09-021-15/+107
* iommu/vt-d: Add qi_batch for dmar_domainLu Baolu2024-09-021-0/+7
* iommu/vt-d: Refactor IOTLB and Dev-IOTLB flush for batchingTina Zhang2024-09-021-64/+78
* iommu/vt-d: Fix aligned pages in calculate_psi_aligned_address()Lu Baolu2024-07-101-0/+1
* iommu/vt-d: Limit max address mask to MAX_AGAW_PFN_WIDTHLu Baolu2024-07-101-1/+1
* iommu/vt-d: Add trace events for cache tag interfaceLu Baolu2024-04-261-0/+10
* iommu/vt-d: Add cache tag invalidation helpersLu Baolu2024-04-261-0/+195
* iommu/vt-d: Add cache tag assignment interfaceLu Baolu2024-04-261-0/+214
generated by cgit (git 2.51.2) at 2025-11-30 17:42:57 +0000