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path: root/drivers/gpu/drm/msm/dsi/phy
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* drm/msm/dsi: Fix 14nm DSI PHY PLL Lock issueLoic Poulain2025-08-132-42/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To configure and enable the DSI PHY PLL clocks, the MDSS AHB clock must be active for MMIO operations. Typically, this AHB clock is enabled as part of the DSI PHY interface enabling (dsi_phy_enable_resource). However, since these PLL clocks are registered as clock entities, they can be enabled independently of the DSI PHY interface, leading to enabling failures and subsequent warnings: ``` msm_dsi_phy 5e94400.phy: [drm:dsi_pll_14nm_vco_prepare] *ERROR* DSI PLL lock failed ------------[ cut here ]------------ dsi0pllbyte already disabled WARNING: CPU: 3 PID: 1 at drivers/clk/clk.c:1194 clk_core_disable+0xa4/0xac CPU: 3 UID: 0 PID: 1 Comm: swapper/0 Tainted: Tainted: [W]=WARN Hardware name: Qualcomm Technologies, Inc. Robotics RB1 (DT) pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [...] ``` This issue is particularly prevalent at boot time during the disabling of unused clocks (clk_disable_unused()) which includes enabling the parent clock(s) when CLK_OPS_PARENT_ENABLE flag is set (this is the case for the 14nm DSI PHY PLL consumers). To resolve this issue, we move the AHB clock as a PM dependency of the DSI PHY device (via pm_clk). Since the DSI PHY device is the parent of the PLL clocks, this resolves the PLL/AHB dependency. Now the AHB clock is enabled prior the PLL clk_prepare callback, as part of the runtime-resume chain. We also eliminate dsi_phy_[enable|disable]_resource functions, which are superseded by runtime PM. Note that it breaks compatibility with kernels before 6.0, as we do not support anymore the legacy `iface_clk` name. Signed-off-by: Loic Poulain <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/663239/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi/phy: Add support for SM8750Krzysztof Kozlowski2025-07-043-6/+76
| | | | | | | | | | | | | | | | Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with an incompatible hardware interface change: ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their offsets were just switched. Currently these registers are not used in the driver, so the easiest is to document both but keep them commented out to avoid conflict. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/659616/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi/dsi_phy_10nm: Fix missing initial VCO rateKrzysztof Kozlowski2025-06-091-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Driver unconditionally saves current state on first init in dsi_pll_10nm_init(), but does not save the VCO rate, only some of the divider registers. The state is then restored during probe/enable via msm_dsi_phy_enable() -> msm_dsi_phy_pll_restore_state() -> dsi_10nm_pll_restore_state(). Restoring calls dsi_pll_10nm_vco_set_rate() with pll_10nm->vco_current_rate=0, which basically overwrites existing rate of VCO and messes with clock hierarchy, by setting frequency to 0 to clock tree. This makes anyway little sense - VCO rate was not saved, so should not be restored. If PLL was not configured configure it to minimum rate to avoid glitches and configuring entire in clock hierarchy to 0 Hz. Suggested-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/sz4kbwy5nwsebgf64ia7uq4ee7wbsa5uy3xmlqwcstsbntzcov@ew3dcyjdzmi2/ Signed-off-by: Krzysztof Kozlowski <[email protected]> Fixes: a4ccc37693a2 ("drm/msm/dsi_pll_10nm: restore VCO rate during Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/654796/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi: add DSI PHY configuration on SA8775PAyushi Makhija2025-05-023-0/+30
| | | | | | | | | | | The SA8775P SoC uses the 5nm (v4.2) DSI PHY driver with different enable regulator load. Signed-off-by: Ayushi Makhija <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/649842/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi/phy: add configuration for SAR2130PDmitry Baryshkov2025-05-023-0/+26
| | | | | | | | | | | | Qualcomm SAR2130P requires slightly different setup for the DSI PHY. It is a 5nm PHY (like SM8450), so supplies are the same, but the rest of the configuration is the same as SM8550 DSI PHY. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Jessica Zhang <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/649257/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi/phy: Define PHY_CMN_CLK_CFG[01] bitfields and simplify savingKrzysztof Kozlowski2025-02-261-4/+6
| | | | | | | | | | | | Add bitfields for PHY_CMN_CLK_CFG0 and PHY_CMN_CLK_CFG1 registers to avoid hard-coding bit masks and shifts and make the code a bit more readable. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/638324/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi/phy: Use dsi_pll_cmn_clk_cfg1_update() when registering PLLKrzysztof Kozlowski2025-02-261-5/+3
| | | | | | | | | | | | | | | | | | Newly added dsi_pll_cmn_clk_cfg1_update() wrapper protects concurrent updates to PHY_CMN_CLK_CFG1 register between driver and Common Clock Framework. pll_7nm_register() still used in one place previous readl+writel, which can be simplified with this new wrapper. This is purely for readability and simplification and should have no functional impact, because the code touched here is before clock is registered via CCF, so there is no concurrency issue. Suggested-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/638323/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi/phy: Program clock inverters in correct registerKrzysztof Kozlowski2025-02-261-1/+1
| | | | | | | | | | | | | | | Since SM8250 all downstream sources program clock inverters in PLL_CLOCK_INVERTERS_1 register and leave the PLL_CLOCK_INVERTERS as reset value (0x0). The most recent Hardware Programming Guide for 3 nm, 4 nm, 5 nm and 7 nm PHYs also mention PLL_CLOCK_INVERTERS_1. Signed-off-by: Krzysztof Kozlowski <[email protected]> Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Reviewed-by: Dmitry Baryshkov <[email protected]> Reported-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/634489/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi/phy: Use the header with clock IDsKrzysztof Kozlowski2025-02-266-3/+7
| | | | | | | | | | | Use the header with clock IDs to bind the interface between driver and DTS. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/634149/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi/phy: Do not overwite PHY_CMN_CLK_CFG1 when choosing bitclk sourceKrzysztof Kozlowski2025-02-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI clock divider, source of bitclk and two for enabling the DSI PHY PLL clocks. dsi_7nm_set_usecase() sets only the source of bitclk, so should leave all other bits untouched. Use newly introduced dsi_pll_cmn_clk_cfg1_update() to update respective bits without overwriting the rest. While shuffling the code, define and use PHY_CMN_CLK_CFG1 bitfields to make the code more readable and obvious. Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/637380/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abhinav Kumar <[email protected]>
* drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driverKrzysztof Kozlowski2025-02-151-13/+22
| | | | | | | | | | | | | | | | | | | | | | PHY_CMN_CLK_CFG1 register is updated by the PHY driver and by a mux clock from Common Clock Framework: devm_clk_hw_register_mux_parent_hws(). There could be a path leading to concurrent and conflicting updates between PHY driver and clock framework, e.g. changing the mux and enabling PLL clocks. Add dedicated spinlock to be sure all PHY_CMN_CLK_CFG1 updates are synchronized. While shuffling the code, define and use PHY_CMN_CLK_CFG1 bitfields to make the code more readable and obvious. Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/637378/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abhinav Kumar <[email protected]>
* drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver sideKrzysztof Kozlowski2025-02-151-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | PHY_CMN_CLK_CFG0 register is updated by the PHY driver and by two divider clocks from Common Clock Framework: devm_clk_hw_register_divider_parent_hw(). Concurrent access by the clocks side is protected with spinlock, however driver's side in restoring state is not. Restoring state is called from msm_dsi_phy_enable(), so there could be a path leading to concurrent and conflicting updates with clock framework. Add missing lock usage on the PHY driver side, encapsulated in its own function so the code will be still readable. While shuffling the code, define and use PHY_CMN_CLK_CFG0 bitfields to make the code more readable and obvious. Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/637376/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abhinav Kumar <[email protected]>
* drm/msm/dsi: Add dsi phy support for SM6150Li Liu2024-12-153-0/+24
| | | | | | | | | | | Add phy configuration for SM6150 Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Li Liu <[email protected]> Signed-off-by: Fange Zhang <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/628009/ Link: https://lore.kernel.org/r/20241210-add-display-support-for-qcs615-platform-v4-6-2d875a67602d@quicinc.com Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi: correct programming sequence for SM8350 / SM8450Dmitry Baryshkov2024-09-011-1/+11
| | | | | | | | | | | | According to the display-drivers, 5nm DSI PLL (v4.2, v4.3) have different boundaries for pll_clock_inverters programming. Follow the vendor code and use correct values. Fixes: 2f9ae4e395ed ("drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450") Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/606947/ Link: https://lore.kernel.org/r/[email protected]
* drm/msm/dsi: Add phy configuration for MSM8937Daniil Titov2024-06-243-0/+21
| | | | | | | | | | | | | Add phy configuration for 28nm dsi phy found on MSM8937 SoC. Only difference from existing msm8916 configuration is number of phy and io_start addresses. Signed-off-by: Daniil Titov <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Barnabás Czémán <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/600518/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi: Remove dsi_phy_write_[un]delay()Konrad Dybcio2024-06-223-33/+54
| | | | | | | | | | | These are dummy wrappers that do literally nothing interesting. Remove them. Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/590703/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi: Remove dsi_phy_read/write()Konrad Dybcio2024-06-227-700/+642
| | | | | | | | | | | These are dummy wrappers that do literally nothing interesting. Remove them. Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/590700/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm: Drop msm_read/writelKonrad Dybcio2024-04-221-4/+4
| | | | | | | | | | Totally useless. Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Andrew Halaney <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/588804/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* Merge remote-tracking branch 'drm-misc/drm-misc-next' into msm-nextRob Clark2023-12-101-1/+1
|\ | | | | | | | | | | | | | | | | | | Backmerge drm-misc-next to pick up some dependencies for drm/msm patches, in particular: https://patchwork.freedesktop.org/patch/570219/?series=127251&rev=1 https://patchwork.freedesktop.org/series/123411/ Signed-off-by: Rob Clark <[email protected]>
| * drm/msm/dsi: use the correct VREG_CTRL_1 value for 4nm cphyJonathan Marek2023-11-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use the same value as the downstream driver. This change is needed for CPHY mode to work correctly. Fixes: 8b034e677111 ("drm/msm/dsi: add support for DSI-PHY on SM8550") Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/566987/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abhinav Kumar <[email protected]>
* | drm/msm: dsi: add support for DSI-PHY on SM8650Neil Armstrong2023-12-053-0/+30
| | | | | | | | | | | | | | | | | | | | Add DSI PHY support for the SM8650 platform. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/564976/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* | drm/msm/dsi: Enable runtime PMKonrad Dybcio2023-12-031-0/+4
| | | | | | | | | | | | | | | | | | | | | | Some devices power the DSI PHY/PLL through a power rail that we model as a GENPD. Enable runtime PM to make it suspendable. Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/543352/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* | drm/msm/dsi: Use pm_runtime_resume_and_get to prevent refcnt leaksKonrad Dybcio2023-12-031-1/+3
|/ | | | | | | | | | | | | | This helper has been introduced to avoid programmer errors (missing _put calls leading to dangling refcnt) when using pm_runtime_get, use it. While at it, start checking the return value. Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Fixes: 5c8290284402 ("drm/msm/dsi: Split PHY drivers to separate files") Patchwork: https://patchwork.freedesktop.org/patch/543350/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi: Reuse QCM2290 14nm DSI PHY configuration for SM6125Marijn Suijten2023-07-271-0/+2
| | | | | | | | | | | | | | | SM6125 features only a single PHY (despite a secondary PHY PLL source being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream sources for this "trinket" SoC do not define the typical "vcca" regulator to be available nor used. This, including the register offset is identical to QCM2290, whose config struct can trivially be reused. Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Marijn Suijten <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/548980/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi: Drop unused regulators from QCM2290 14nm DSI PHY configMarijn Suijten2023-07-271-2/+0
| | | | | | | | | | | | | | | The regulator setup was likely copied from other SoCs by mistake. Just like SM6125 the DSI PHY on this platform is not getting power from a regulator but from the MX power domain. Fixes: 572e9fd6d14a ("drm/msm/dsi: Add phy configuration for QCM2290") Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Marijn Suijten <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/548959/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi: Add phy configuration for MSM8226Luca Weiss2023-06-043-1/+101
| | | | | | | | | | | | | | | | | | | | | | | | | MSM8226 uses a modified PLL lock sequence compared to MSM8974, which is based on the function dsi_pll_enable_seq_m in the msm-3.10 kernel. Worth noting that the msm-3.10 downstream kernel also will try other sequences in case this one doesn't work, but during testing it has shown that the _m sequence succeeds first time also: .pll_enable_seqs[0] = dsi_pll_enable_seq_m, .pll_enable_seqs[1] = dsi_pll_enable_seq_m, .pll_enable_seqs[2] = dsi_pll_enable_seq_d, .pll_enable_seqs[3] = dsi_pll_enable_seq_d, .pll_enable_seqs[4] = dsi_pll_enable_seq_f1, .pll_enable_seqs[5] = dsi_pll_enable_seq_c, .pll_enable_seqs[6] = dsi_pll_enable_seq_e, We may need to expand this in the future. Signed-off-by: Luca Weiss <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/540618/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi: don't allow enabling 14nm VCO with unprogrammed rateDmitry Baryshkov2023-05-201-0/+3
| | | | | | | | | | | | | | | | | If the dispcc uses CLK_OPS_PARENT_ENABLE (e.g. on QCM2290), CCF can try enabling VCO before the rate has been programmed. This can cause clock lockups and/or other boot issues. Program the VCO to the minimal PLL rate if the read rate is 0 Hz. Cc: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Reported-by: Vladimir Zapolskiy <[email protected]> Reported-by: Konrad Dybcio <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Fixes: f079f6d999cb ("drm/msm/dsi: Add PHY/PLL for 8x96") Patchwork: https://patchwork.freedesktop.org/patch/534813/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi: correct byte intf clock rate for 14nm DSI PHYDmitry Baryshkov2023-01-221-0/+4
| | | | | | | | | | | | | | | | | | | | According to the vendor kernel, byte intf clock rate should be a half of the byte clock only when DSI PHY version is above 2.0 (in other words, 10nm PHYs and later) and only if PHY is used in D-PHY mode. Currently MSM DSI code handles only the second part of the clause (C-PHY vs D-PHY), skipping DSI PHY version check, which causes issues on some of 14nm DSI PHY platforms (e.g. qcm2290). Move divisor selection to DSI PHY code, pass selected divisor through shared timings and set byte intf clock rate accordingly. Cc: Loic Poulain <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Tested-by: Konrad Dybcio <[email protected]> # SM6115P J606F Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/519006/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi: Add phy configuration for SM6375Konrad Dybcio2023-01-223-0/+23
| | | | | | | | | | SM6375 uses a boring standard 7nm PHY. Add a configuration entry for it. Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/518511/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi: add support for DSI-PHY on SM8550Neil Armstrong2023-01-223-14/+77
| | | | | | | | | | | SM8550 use a 4nm DSI PHYs, which share register definitions with 7nm DSI PHYs. Rather than duplicating the driver, handle 4nm variant inside the common 5+7nm driver. Signed-off-by: Neil Armstrong <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/517515/ Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-mdss-dsi-v3-6-660c3bcb127f@linaro.org Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450Dmitry Baryshkov2023-01-223-10/+115
| | | | | | | | | | | | | | | | | SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm variants inside the common 5+7nm driver. Co-developed-by: Robert Foss <[email protected]> Signed-off-by: Robert Foss <[email protected]> Tested-by: Vinod Koul <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/514230/ Link: https://lore.kernel.org/r/[email protected] [DB: changed compatibles per Krzysztof's request] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi/phy: rework register setting for 7nm PHYDmitry Baryshkov2023-01-081-13/+13
| | | | | | | | | | | | | In preparation to adding the sm8350 and sm8450 PHYs support, rearrange register values calculations in dsi_7nm_phy_enable(). This change bears no functional changes itself, it is merely a preparation for the next patch. Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/514232/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi: Add phy configuration for QCM2290Loic Poulain2022-11-043-0/+20
| | | | | | | | | | | | | | The QCM2290 SoC a the 14nm (V2.0) single DSI phy. The platform is not fully compatible with the standard 14nm PHY, so it requires a separate compatible and config entry. Signed-off-by: Loic Poulain <[email protected]> [DB: rebased and updated commit msg] Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/504578/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi: Improve dsi_phy_driver_probe() probe error handlingDouglas Anderson2022-09-181-47/+27
| | | | | | | | | | | | | | | | | | | | | | | The dsi_phy_driver_probe() function has a "goto fail" for no reason. Change it to just always return directly when it sees an error. Make this simpler by leveraging dev_err_probe() which is designed to make code like this shorter / simpler. NOTE: as part of this, we now pass through error codes directly from msm_ioremap_size() rather than translating to -ENOMEM. This changed mostly because it's much more convenient when using dev_err_probe() and also it's usually encouraged not to hide error codes like the old code was doing unless there is a good reason. I can't see any reason why we'd need to return -ENOMEM instead of -EINVAL from the probe function. Signed-off-by: Douglas Anderson <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/496324/ Link: https://lore.kernel.org/r/20220804073608.v4.6.I969118a35934a0e5007fe4f80e3e28e9c0b7602a@changeid Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* drm/msm/dsi: Take advantage of devm_regulator_bulk_get_const()Douglas Anderson2022-09-188-112/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of the commit 1de452a0edda ("regulator: core: Allow drivers to define their init data as const") we no longer need to do copying of regulator bulk data from initdata to something dynamic. Let's take advantage of that. In addition to saving some code, this also moves us to using ARRAY_SIZE() to specify how many regulators we have which is less error prone. This gets rid of some layers of wrappers which makes it obvious that we can get rid of an extra error print. devm_regulator_bulk_get_const() prints errors for you so you don't need an extra layer of printing. In all cases here I have preserved the old settings without any investigation about whether the loads being set are sensible. In the cases of some of the PHYs if several PHYs in the same file used exactly the same settings I had them point to the same data structure. NOTE: Though I haven't done the math, this is likely an overall savings in terms of "static const" data. We previously always allocated space for 8 supplies. Each of these supplies took up 36 bytes of data (32 for name, 4 for an int). Signed-off-by: Douglas Anderson <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/496325/ Link: https://lore.kernel.org/r/20220804073608.v4.5.I55a9e65cb1c22221316629e98768ff473f47a067@changeid Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* drm/msm/dsi: Use the new regulator bulk feature to specify the loadDouglas Anderson2022-09-181-10/+3
| | | | | | | | | | | | | | | As of commit 6eabfc018e8d ("regulator: core: Allow specifying an initial load w/ the bulk API") we can now specify the initial load in the bulk data rather than having to manually call regulator_set_load() on each regulator. Let's use it. Signed-off-by: Douglas Anderson <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/496319/ Link: https://lore.kernel.org/r/20220804073608.v4.4.I7b3c72949883846badb073cfeae985c55239da1d@changeid Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* drm/msm/dsi: Don't set a load before disabling a regulatorDouglas Anderson2022-09-187-61/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of commit 5451781dadf8 ("regulator: core: Only count load for enabled consumers"), a load isn't counted for a disabled regulator. That means all the code in the DSI driver to specify and set loads before disabling a regulator is not actually doing anything useful. Let's remove it. It should be noted that all of the loads set that were being specified were pointless noise anyway. The only use for this number is to pick between low power and high power modes of regulators. Regulators appear to do this changeover at loads on the order of 10000 uA. You would need a lot of clients of the same rail for that 100 uA number to count for anything. Note that now that we get rid of the setting of the load at disable time, we can just set the load once when we first get the regulator and then forget it. It should also be noted that the regulator functions regulator_bulk_enable() and regulator_set_load() already print error messages when they encounter problems so while moving things around we get rid of some extra error prints. Signed-off-by: Douglas Anderson <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/496320/ Link: https://lore.kernel.org/r/20220804073608.v4.3.If1f94fbbdb7c1d0fb3961de61483a851ad1971a7@changeid Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* drm/msm/dsi_phy_7nm: Replace parent names with clk_hw pointersMarijn Suijten2022-09-181-36/+34
| | | | | | | | | | | | | parent_hw pointers are easier to manage and cheaper to use than repeatedly formatting the parent name and subsequently leaving the clk framework to perform lookups based on that name. Signed-off-by: Marijn Suijten <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/491927/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* drm/msm/dsi_phy_10nm: Replace parent names with clk_hw pointersMarijn Suijten2022-09-181-42/+35
| | | | | | | | | | | | | parent_hw pointers are easier to manage and cheaper to use than repeatedly formatting the parent name and subsequently leaving the clk framework to perform lookups based on that name. Signed-off-by: Marijn Suijten <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/491923/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* drm/msm/dsi_phy_14nm: Replace parent names with clk_hw pointersMarijn Suijten2022-09-181-21/+19
| | | | | | | | | | | | | parent_hw pointers are easier to manage and cheaper to use than repeatedly formatting the parent name and subsequently leaving the clk framework to perform lookups based on that name. Signed-off-by: Marijn Suijten <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/491921/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* drm/msm/dsi_phy_28nm: Replace parent names with clk_hw pointersMarijn Suijten2022-09-181-27/+23
| | | | | | | | | | | | | parent_hw pointers are easier to manage and cheaper to use than repeatedly formatting the parent name and subsequently leaving the clk framework to perform lookups based on that name. Signed-off-by: Marijn Suijten <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/491925/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* drm/msm/dsi_phy_28nm_8960: Replace parent names with clk_hw pointersMarijn Suijten2022-09-181-7/+8
| | | | | | | | | | | | | parent_hw pointers are easier to manage and cheaper to use than repeatedly formatting the parent name and subsequently leaving the clk framework to perform lookups based on that name. Signed-off-by: Marijn Suijten <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/491929/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* drm/msm/dsi/phy: Replace hardcoded char-array length with sizeof()Marijn Suijten2022-09-185-60/+60
| | | | | | | | | | | | | | | Now that the last DSI PHY PLL driver (dsi_phy_28nm_8960) has been converted to use a simple stack-local char-array instead of a devm_kzalloc heap allocation we can safely call sizeof() on every string variable (that's now a sized array instead of a pointer) passed into snprintf instead of hardcoding the size. Signed-off-by: Marijn Suijten <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/491920/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* drm/msm/dsi_phy_28nm_8960: Use stack memory for temporary clock namesMarijn Suijten2022-09-181-13/+1
| | | | | | | | | | | | | | | | | The clock names formatted into the hw_clk's init structure are only used for the duration of the registration function where they are kstrdup'ed, making it unnecessary to keep the allocations alive for the duration of the device (through devm). Just like the other DSI PHY PLL clock trees, use a stack-local char array and save on memory outside of the pll_28nm_register function. Signed-off-by: Marijn Suijten <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/491917/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* drm/msm/dsi/phy: Reindent and reflow multiline function callsMarijn Suijten2022-09-185-164/+161
| | | | | | | | | | | | | | | | | | | | | | | | | The commit 613cbd1da3c9 ("drm/msm/dsi: use devm_clk_*register to registe DSI PHY clocks") introduced the devm_ prefix to clk_hw registration calls, without updating the indentation of the arguments on the following lines. Similarly commit e55b3fbbbbc8 ("drm/msm/dsi: drop PLL accessor functions") moved from pll_write to dsi_phy_write without updating the indentation of followup arguments either. Preparing for a series that heavily touches the clk calls, reflow and reindent function calls that are adhering to an 80-char column limit by spanning multiple lines. Where function names are very long the arguments are indented with a fixed number of two tab characters instead of aligning with the opening parenthesis of the function call. Signed-off-by: Marijn Suijten <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/491931/ Link: https://lore.kernel.org/r/[email protected] [DB: adjusted commit message to make checkpatch happy] Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* drm/msm/dsi: fix the inconsistent indentingsunliming2022-09-181-1/+1
| | | | | | | | | | | | | | | | | Fix the inconsistent indenting in function msm_dsi_dphy_timing_calc_v3(). Fix the following smatch warnings: drivers/gpu/drm/msm/dsi/phy/dsi_phy.c:350 msm_dsi_dphy_timing_calc_v3() warn: inconsistent indenting Fixes: f1fa7ff44056 ("drm/msm/dsi: implement auto PHY timing calculator for 10nm PHY") Reported-by: kernel test robot <[email protected]> Signed-off-by: sunliming <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/494662/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abhinav Kumar <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* drm/msm/dsi: pll_7nm: remove unsupported dividers for DSI pixel clockDmitry Baryshkov2022-05-061-6/+4
| | | | | | | | | | | Remove dividers that are not recommended for DSI DPHY mode when setting up the clock tree for the DSI pixel clock. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/484333/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/msm/dsi: fix address for second DSI PHY on SDM660Dmitry Baryshkov2022-05-061-1/+1
| | | | | | | | | | | | | | Correct a typo in the address of the second DSI PHY in the SDM660 device config. Fixes: 694dd304cc29 ("drm/msm/dsi: Add phy configuration for SDM630/636/660") Cc: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/484697/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
*-. Merge branches 'msm-next-lumag-core', 'msm-next-lumag-dpu', ↵Dmitry Baryshkov2022-02-197-19/+151
|\ \ | | | | | | | | | 'msm-next-lumag-dp', 'msm-next-lumag-dsi', 'msm-next-lumag-hdmi' and 'msm-next-lumag-mdp5' into msm-next-lumag
| | * drm/msm/dsi/phy: fix 7nm v4.0 settings for C-PHY modeDmitry Baryshkov2022-02-181-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dsi_7nm_phy_enable() disagrees with downstream for glbl_str_swi_cal_sel_ctrl and glbl_hstx_str_ctrl_0 values. Update programmed settings to match downstream driver. To remove the possibility for such errors in future drop less_than_1500_mhz assignment and specify settings explicitly. Fixes: 5ac178381d26 ("drm/msm/dsi: support CPHY mode for 7nm pll/phy") Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
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