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path: root/drivers/gpu/drm/amd/pm/amdgpu_pm.c
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* drm/amd/pm: Add debugfs node to read private bufferLijo Lazar2021-05-101-0/+44
| | | | | | | | | | | Add debugfs interface to read region allocated for FW private buffer Signed-off-by: Lijo Lazar <[email protected]> Suggested-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* amdgpu/pm: set pp_dpm_dcefclk to readonly on NAVI10 and newer gpusDarren Powell2021-04-291-0/+8
| | | | | | | | | | | | v2 : change condition to apply to all chips after NAVI10 Writing to dcefclk causes the gpu to become unresponsive, and requires a reboot. Patch prevents user from successfully writing to file pp_dpm_dcefclk on parts NAVI10 and newer, and gives better user feedback that this operation is not allowed. Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Ensure dcefclk isn't created on AldebaranKent Russell2021-04-151-1/+3
| | | | | | | | | Like Arcturus, this isn't available on Aldebaran, so remove it accordingly Signed-off-by: Kent Russell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: Convert sysfs sprintf/snprintf family to sysfs_emitTian Tao2021-04-091-45/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following coccicheck warning: drivers/gpu/drm/amd/pm/amdgpu_pm.c:1940:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:1978:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:2022:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:294:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:154:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:496:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:512:9-17: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:1740:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:1667:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:2074:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:2047:9-17: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:2768:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:2738:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:2442:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:3246:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:3253:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:2458:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:3047:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:3133:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:3209:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:3216:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:2410:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:2496:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:2470:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:2426:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:2965:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:2972:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:3006:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/amd/pm/amdgpu_pm.c:3013:8-16: WARNING: use scnprintf or sprintf Signed-off-by: Tian Tao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/pm: bail on sysfs/debugfs queries during platform suspendAlex Deucher2021-04-091-0/+98
| | | | | | | | | | The GPU is in the process of being shutdown. Spurious queries during suspend and resume can put the SMU into a bad state. Runtime PM is handled dynamically so we check if we are in non-runtime suspend. Reviewed-by: Evan Quan <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: label these APIs used internally as staticEvan Quan2021-04-091-9/+1
| | | | | | | | Also drop unnecessary header file and declarations. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: Mundane typo fixes in the file amdgpu_pm.cBhaskar Chowdhury2021-03-241-2/+2
| | | | | | | | | | s/"an minimum"/"a minimum"/ s/"an maxmum"/"a maximum"/ Reviewed-by: Huang Rui <[email protected]> Acked-by: Randy Dunlap <[email protected]> Signed-off-by: Bhaskar Chowdhury <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: add a new sysfs entry for default power limitEric Huang2021-03-241-4/+49
| | | | | | | | | Driver doesn't keep the default bootup power limit and expose it to user. As requested we add it in driver. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: Remove min/max overload of pp_dpm_sclkLijo Lazar2021-03-241-85/+0
| | | | | | | | | To maintain consistency with legacy usage, remove min/max clock overload of pp_dpm_sclk node. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: Enable performance determinism on aldebaranLijo Lazar2021-03-241-0/+88
| | | | | | | | | | | | | | | | | | | | Performance Determinism is a new mode in Aldebaran where PMFW tries to maintain sustained performance level. It can be enabled on a per-die basis on aldebaran. To guarantee that it remains within the power cap, a max GFX frequency needs to be specified in this mode. A new power_dpm_force_performance_level, "perf_determinism", is defined to enable this mode in amdgpu. The max frequency (in MHz) can be specified through pp_dpm_sclk. The mode will be disabled once any other performance level is chosen. Ex: To enable perf determinism at 900Mhz max gfx clock echo perf_determinism > /sys/bus/pci/devices/.../power_dpm_force_performance_level echo max 900 > /sys/bus/pci/devices/.../pp_dpm_sclk Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable one vf mode on sienna cichlid vfHorace Chen2021-03-051-1/+1
| | | | | | | | | | | | | | sienna cichlid needs one vf mode which allows vf to set and get clock status from guest vm. So now expose the required interface and allow some smu request on VF mode. Also since this asic blocked direct MMIO access, use KIQ to send SMU request under sriov vf. OD use same command as getting pp table which is not allowed for sienna cichlid, so remove OD feature under sriov vf. Signed-off-by: Horace Chen <[email protected]> Reviewed-by: Monk Liu<[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* amdgpu/pm: Powerplay API for smu , updates to some pm functionsDarren Powell2021-02-261-62/+36
| | | | | | | | | | | | | | | | | | | | v3: updated to include new clocks od_vddgfx_offset, od_cclk Context mismatch with revision v3 to patch 0003 Modified Functions smu_sys_set_pp_table() - modifed signature to match Powerplay API set_pp_table smu_force_performance_level() - modifed arg0 to match Powerplay API force_performance_level smu_od_edit_dpm_table() - modifed arg0 to match Powerplay API odn_edit_dpm_table Other Changes smu_od_edit_dpm_table() - removed call to task(READJUST_POWER_STATE) after COMMIT_TABLE, now handled in calling function amdgpu_set_power_dpm_force_performance_level() - now checks thermal for swsmu systems before trying to change level amdgpu_set_pp_od_clk_voltage() - now attempts to set fine_grain_clock_vol before swsmu edit dpm table Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* amdgpu/pm: Powerplay API for smu , changes to clock and profile mode functionsDarren Powell2021-02-261-415/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v3: updated to include new clocks vclk, dclk, od_vddgfx_offset, od_cclk Added forward declaration for function smu_force_smuclk_levels to resolve clash with other commits Resolved context clashes with other commits and v3 updates to patches 0003, 0004 v2: fix errors flagged by checkpatch New Functions smu_bump_power_profile_mode() - changes profile mode assuming calling function already has mutex smu_force_ppclk_levels() - accepts Powerplay enum pp_clock_type to specify clock to change smu_print_ppclk_levels() - accepts Powerplay enum pp_clock_type to request clock levels amdgpu_get_pp_dpm_clock() - accepts Powerplay enum pp_clock_type to request clock levels and allows all the amdgpu_get_pp_dpm_$CLK functions to have a single codepath amdgpu_set_pp_dpm_clock() - accepts Powerplay enum pp_clock_type to set clock levels and allows all the amdgpu_set_pp_dpm_$CLK functions to have a single codepath Modified Functions smu_force_smuclk_levels - changed function name to make clear difference to smu_force_ppclk_levels smu_force_ppclk_levels() - modifed signature to implement Powerplay API force_clock_level - calls smu_force_smuclk_levels smu_print_smuclk_levels - changed function name to make clear difference to smu_print_ppclk_levels smu_print_ppclk_levels() - modifed signature to implement Powerplay API force_clock_level - calls smu_print_smuclk_levels smu_sys_get_gpu_metrics - modifed arg0 to match Powerplay API get_gpu_metrics smu_get_power_profile_mode - modifed arg0 to match Powerplay API get_power_profile_mode smu_set_power_profile_mode - modifed arg0 to match Powerplay API set_power_profile_mode - removed arg lock_needed, mutex always locked, internal functions can call smu_bump if they already hold lock smu_switch_power_profile - now calls smu_bump as already holds mutex lock smu_adjust_power_state_dynamic - now calls smu_bump as already holds mutex lock amdgpu_get_pp_od_clk_voltage - uses smu_print_ppclk_levels amdgpu_{set,get}_pp_dpm_$CLK - replace logic with call helper function amdgpu_{set,get}_pp_dpm_clock() CLK ={sclk, mclk, socclk, fclk, dcefclk, pci, vclkd, dclk} Other Changes added 5 smu Powerplay functions to swsmu_dpm_funcs removed special smu handling in pm functions and called through Powerplay API Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* amdgpu/pm: Powerplay API for smu , changed 9 pm power functions to use APIDarren Powell2021-02-261-41/+21
| | | | | | | | | | | | | | | | | | | | | | v2: remove check for error during swsmu amdgpu_dpm_get_pp_num_states() call to match previous powerplay behaviour v3: removed smu implementation of powerplay get_power_limit Resolved context clashes with other commits Modified Files smu_set_power_limit() - modifed arg0 to match Powerplay API set_power_limit smu_sys_get_pp_table() - modifed signature to match Powerplay API get_pp_table smu_get_power_num_states() - modifed arg0 to match Powerplay API get_pp_num_states smu_get_current_power_state() - modifed arg0 to match Powerplay API get_current_power_state smu_sys_get_pp_feature_mask() - modifed signature to match Powerplay API get_ppfeature_status smu_sys_set_pp_feature_mask() - modifed arg0 to match Powerplay API set_ppfeature_status Other Changes added 6 above smu Powerplay functions to swsmu_dpm_funcs removed special smu handling of above functions and called through Powerplay API Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* amdgpu/pm: Powerplay API for smu , changed 6 pm hwmon fan functions to use APIDarren Powell2021-02-261-64/+31
| | | | | | | | | | | | | | | | | | | | | | | v2: changed error return value of smu_get_fan_control_mode to AMD_FAN_CTRL_NONE fixed type in amdgpu_hwmon_get_pwm1_enable() print statement fixed indent flagged by checkpatch.pl Modified Functions smu_set_fan_speed_rpm() - modifed arg0 to match Powerplay API set_fan_speed_rpm smu_get_fan_control_mode() - modifed signature to match Powerplay API get_fan_control_mode smu_set_fan_control_mode() - modifed signature to match Powerplay API set_fan_control_mode smu_get_fan_speed_percent() - modifed signature to match Powerplay API get_fan_speed_percent smu_set_fan_speed_percent() - modifed signature to match Powerplay API set_fan_speed_percent smu_get_fan_speed_rpm() - modifed arg0 to match Powerplay API get_fan_speed_rpm Other Changes added 6 above smu fan Powerplay functions to swsmu_dpm_funcs removed special smu handling of above functions and called through Powerplay API Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* amdgpu/pm: Powerplay API for smu , added get_performance_levelDarren Powell2021-02-261-3/+1
| | | | | | | | | | | | | | | | v2: updated the structure name to swsmu_pm_funcs Modified Functions smu_get_performance_level() - modifed arg0 to match Powerplay API get_performance_level Other Changes added a new structure swsmu_dpm_funcs to hold smu functions for Powerplay API removed special smu handling from amdgpu_get_power_dpm_force_performance_level Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: do not use drm middle layer for debugfsNirmoy Das2021-02-181-13/+12
| | | | | | | | | | | | Use debugfs API directly instead of drm middle layer. v2: * checkpatch.pl: use '0444' instead of S_IRUGO. * remove S_IFREG from mode. * remove mode variable. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: add support for hwmon control of slow and fast PPT limit on vangoghXiaomeng Hou2021-02-091-5/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement hwmon API for reading/setting slow and fast PPT limit. APU power is managed to system-level requirements through the PPT (package power tracking) feature. PPT is intended to limit power to the requirements of the power source and could be dynamically updated to maximize APU performance within the system power budget. Here FAST_PPT_LIMIT manages the ~10 ms moving average of APU power, while SLOW_PPT_LIMIT manages the configurable, thermally significant moving average of APU power (default ~5000 ms). User could read slow/fast ppt limit using command "cat power*_cap" or "sensors" in the hwmon device directory. User could adjust values of slow/fast ppt limit as needed depending on workloads through command "echo ## > power*_cap". Example: $ echo 15000000 > power1_cap $ echo 18000000 > power2_cap $ sensors amdgpu-pci-0300 Adapter: PCI adapter slowPPT: 9.04W (cap = 15.00 W) fastPPT: 9.04W (cap = 18.00 W) v2: align with existing interfaces for the getting/setting of PPT limits. Encode the upper 8 bits of limit value to distinguish slow and fast power limit type. Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: modify the power limit level parameter from bool to enum typeXiaomeng Hou2021-02-091-2/+2
| | | | | | | | | | The original smu_get_power_limit callback accepts the power limit level parameter as bool which limits to max and current. For possible needs to retrieve other level like min, extend the parameter type using enum. Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Prevent shift wrapping in amdgpu_read_mask()Dan Carpenter2021-02-021-3/+3
| | | | | | | | | | If the user passes a "level" value which is higher than 31 then that leads to shift wrapping. The undefined behavior will lead to a syzkaller stack dump. Fixes: 5632708f4452 ("drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)") Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: correct string parsing for extra separator characters caseEvan Quan2021-02-011-0/+2
| | | | | | | | Supplement of previous fix. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/pm: Account for extra separator characters in sysfs interfaceMatt Coffin2021-02-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Currently, the the input to the pp_od_clk_voltage sysfs interface has two adjacent separator characters, i.e. "\n\0", then we try to parse an argument out of the empty string, whereas we really should just ignore this case, and treat any number of adjacent separators as one separator for arguments. We do this here by simply skipping the argument parsing for all empy-string arguments. An example test case would be `echo 's 1 900' > pp_od_clk_voltage` (note the two spaces after the 's'. This also solves the issue where the written string ends with both a newline, and a nul-terminator, '\n\0', as is the case for `echo 's 1 900' > pp_od_clk_voltage` since the recent rebase. Got lost during code rebase/merge. No need to port this to other branches. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Matt Coffin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Revert "Revert "drm/amdgpu: Fix NULL dereference in dpm sysfs handlers""Evan Quan2021-02-011-6/+3
| | | | | | | | This reverts commit 2456c290a7889be492cb96092b62d16c11176f72. Got lost during code rebase/merge. No need to port this to other branches. Signed-off-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: fix build error without x86 kconfig (v2)Huang Rui2021-01-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to fix below build error while we are using the kconfig without x86. drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c: In function 'vangogh_get_smu_metrics_data': drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c:300:10: error: 'boot_cpu_data' undeclared (first use in this function); did you mean 'boot_cpuid'? 300 | boot_cpu_data.x86_max_cores * sizeof(uint16_t)); | ^~~~~~~~~~~~~ | boot_cpuid drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c: In function 'vangogh_read_sensor': drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c:1320:11: error: 'boot_cpu_data' undeclared (first use in this function); did you mean 'boot_cpuid'? 1320 | *size = boot_cpu_data.x86_max_cores * sizeof(uint16_t); | ^~~~~~~~~~~~~ | boot_cpuid drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c: In function 'vangogh_od_edit_dpm_table': drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.c:1460:19: error: 'boot_cpu_data' undeclared (first use in this function); did you mean 'boot_cpuid'? 1460 | if (input[0] >= boot_cpu_data.x86_max_cores) { | ^~~~~~~~~~~~~ | boot_cpuid v2: fix #ifdef and add comment for APU only Reported-by: Stephen Rothwell <[email protected]> Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: modify the fine grain tuning function for RenoirXiaojian Du2021-01-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | This patch is to modify the fine grain tuning function for Renoir. The fine grain tuning function uses the sysfs node -- pp_od_clk_voltage to config gfxclk. Meanwhile, another sysfs node -- power_dpm_force_perfomance_level also affects the gfx clk. It will cause confusion when these two sysfs nodes works together. It is risky to add two new flags to common smu struct, so this patch uses the existing flag to make these two sysfs nodes works separately. Only when power_dpm_force_perfomance_level is changed to "manual" mode, the fine grain function will be started. In other profile modes, including "auto", "high", "low", "profile_peak", "profile_standard", "profile_min_sclk", "profile_min_mclk", the fine grain tuning function will be shut down and the frequency range of gfx will be restored the default value. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: implement processor fine grain feature for vangogh (v3)Huang Rui2021-01-141-0/+3
| | | | | | | | | | | | | | | | | | | | | This patch is to implement the processor fine grain feature for vangogh. It's similar with gfx clock, the only difference is below: echo "p core_id level value" > pp_od_clk_voltage 1. "p" - set the cclk (processor) frequency 2. "core_id" - 0/1/2/3, represents which cpu core you want to select 2. "level" - 0 or 1, "0" represents the min value, "1" represents the max value 3. "value" - the target value of cclk frequency, it should be limited in the safe range v2: fix some missing changes as Evan's suggestion. v3: add version check and fix the restore. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: implement the processor clocks which read by metricHuang Rui2021-01-141-0/+25
| | | | | | | | | The core processor clocks will be stored in smu metric table, then we add this runtime information into amdgpu_pm_info interface. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: modify the fine grain tuning function for RenoirXiaojian Du2021-01-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to improve the fine grain tuning function for Renoir. The fine grain tuning function uses the sysfs node -- pp_od_clk_voltage to config gfxclk. Meanwhile, another sysfs node -- power_dpm_force_perfomance_level also affects the gfx clk. It will cause confusion when these two sysfs nodes works together. And the flag "od_enabled" is used to control the overdrive function for dGPU, like navi10, navi14 and navi21. APU like Renior or Vangogh uses this "od_enabled" to configure the frequency range of gfx clock, but the max value of frequency range will not be higher than the safe limit, it is not "overdrive". So this patch adds two new flags -- "fine_grain_enabled" and "fine_grain_started" to avoid this confusion, the flag will make these two sysfs nodes work separately. The flag "fine_grain_enabled" is set as "enabled" by default, so the fine grain tuning function will be enabled by default. But the flag "fine_grain_started" is set as "false" by default, so the fine grain function will not take effect until it is set as "true". Only when power_dpm_force_perfomance_level is changed to "manual" mode, the flag "fine_grain_started" will be set as "true", and the fine grain tuning function will be started. In other profile modes, including "auto", "high", "low", "profile_peak", "profile_standard", "profile_min_sclk", "profile_min_mclk", the flag "fine_grain_started" will be set as "false", and the od range of fine grain tuning function will be restored default value. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: add two new sysfs nodes for vangoghXiaojian Du2021-01-051-0/+140
| | | | | | | | | | | | This patch is to add two new sysfs nodes for vangogh: pp_dpm_dclk and pp_dpm_vclk. The two sysfs nodes are similar to pp_dpm_fclk/memclk/socclk. pp_dpm_dclk represents the DPM frequency of dcn unit. pp_dpm_vclk represents the DPM frequency of vcn unit. Signed-off-by: Xiaojian Du <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: support overdrive vddgfx offset setting(V2)Evan Quan2020-12-231-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish. For these ASICs, the target voltage calculation can be illustrated by "voltage = voltage calculated from v/f curve + overdrive vddgfx offset". V2: limit the smu_version check for Sienna Cichlid only Here are some sample usages about this new OD setting: 1. Check current vddgfx offset setting by cat /sys/class/drm/card0/device/pp_od_clk_voltage ... ... OD_VDDGFX_OFFSET: 0mV ... ... 2. Set new vddgfx offset by echo "vo 10" > /sys/class/drm/card0/device/pp_od_clk_voltage cat /sys/class/drm/card0/device/pp_od_clk_voltage ... ... OD_VDDGFX_OFFSET: 10mV ... ... 3. Commit the new setting by echo "c" > /sys/class/drm/card0/device/pp_od_clk_voltage Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: enable Sienna Cichlid overdrive supportEvan Quan2020-12-231-1/+2
| | | | | | | | Enable Sienna Cichlid gfxclk/uclk overdrive support. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add missing clock gating info in amdgpu_pm_infoKevin Wang2020-11-051-0/+5
| | | | | | | | | | | | | | add missing clock gating informations in amdgpu_pm_info 1. AMD_CG_SUPPORT_VCN_MGCG 2. AMD_CG_SUPPORT_HDP_DS 3. AMD_CG_SUPPORT_HDP_SD 4. AMD_CG_SUPPORT_IH_CG 5. AMD_CG_SUPPORT_JPEG_MGCG Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: cleanup debug log in amdgpu_set_pp_features()Kevin Wang2020-11-041-2/+0
| | | | | | Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Add GFX Fine Grain Clock Gating flagJinzhou.Su2020-11-041-0/+1
| | | | | | | | Add AMD_CG_SUPPORT_GFX_FGCG for FGCG Signed-off-by: Jinzhou.Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: set the initial value of pm info to zeroXiaojian Du2020-10-301-1/+1
| | | | | | | | | | | | | | | | | This patch is to set the initial value of pm info to zero. The "value64" is ported to the hwmon and debugfs node, it is a uint64 type. When it is used for NV10/VEGA10/VEGA20, its word size is appropriate, because NV10/VEGA10/VEGA20 has a 64bit smu feature mask, which is separated to high 32bit and low 32bit. But some asic has only 32bit smu feature mask,and this 32bit mask will fill the low 32bit of "value64". So if this "value64" is not initialized to zero, the high 32bit will be filled by a meaningless value, when the whole "value64" is ported to the "SMC Feature Mask" in the "amdgpu_pm_info" on some specific asic, it will be a wrong value. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: populate Arcturus PCIE link stateEvan Quan2020-10-151-3/+0
| | | | | | | | Populate current link speed, width and clock domain frequency. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/swsmu: clean up a bunch of stale interfacesAlex Deucher2020-10-091-4/+4
| | | | | | | | | These were leftover from the initial implementation, but never used. Drop them. Reviewed-by: Evan Quan <[email protected]> Noticed-by: Ryan Taylor <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/powerplay: add one sysfs file to support the feature to modify gfx ↵Xiaojian Du2020-09-291-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clock on Raven/Raven2/Picasso APU. This patch is to add one sysfs file -- "pp_od_clk_voltage" for Raven/Raven2/Picasso APU, which is only used by dGPU like VEGA10. This sysfs file supports the feature to modify gfx engine clock(Mhz units), it can be used to configure the min value and the max value for gfx clock limited in the safe range. Command guide: echo "s level clock" > pp_od_clk_voltage s - adjust teh sclk level level - 0 or 1, "0" represents the min value, "1" represents the max value clock - the clock value(Mhz units), like 400, 800 or 1200, the value must be within the OD_RANGE limits. Example: $ cat pp_od_clk_voltage OD_SCLK: 0: 200Mhz 1: 1400Mhz OD_RANGE: SCLK: 200MHz 1400MHz $ echo "s 0 600" > pp_od_clk_voltage $ echo "s 1 1000" > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 600Mhz 1: 1000Mhz OD_RANGE: SCLK: 200MHz 1400MHz Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Get DRM dev from adev by inline-fLuben Tuikov2020-08-241-97/+97
| | | | | | | | | Add a static inline adev_to_drm() to obtain the DRM device pointer from an amdgpu_device pointer. Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: drm_device to amdgpu_device by inline-f (v2)Luben Tuikov2020-08-241-40/+40
| | | | | | | | | | | | | | Get the amdgpu_device from the DRM device by use of an inline function, drm_to_adev(). The inline function resolves a pointer to struct drm_device to a pointer to struct amdgpu_device. v2: Use a typed visible static inline function instead of an invisible macro. Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: refine codes to avoid reentering GPU recoveryDennis Li2020-08-241-58/+58
| | | | | | | | | | | | | if other threads have holden the reset lock, recovery will fail to try_lock. Therefore we introduce atomic hive->in_reset and adev->in_gpu_reset, to avoid reentering GPU recovery. v2: drop "? true : false" in the definition of amdgpu_in_reset Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Dennis Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/pm: only hide average power on SI and pre-RENOIR APUsAlex Deucher2020-08-181-2/+7
| | | | | | | | | We can get this on RENOIR and newer via the SMU metrics table. Reviewed-by: Evan Quan <[email protected]> Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/pm: remove duplicate checkAlex Deucher2020-08-181-2/+1
| | | | | | | | FAMILY_KV is APUs and we already check for APUs. Reviewed-by: Evan Quan <[email protected]> Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: optimize the power related source code layoutEvan Quan2020-08-141-0/+3613
The target is to provide a clear entry point(for power routines). Also this can help to maintain a clear view about the frameworks used on different ASICs. Hopefully all these can make power part more friendly to play with. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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