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authorDarren Powell <[email protected]>2021-04-07 22:40:34 +0000
committerAlex Deucher <[email protected]>2021-04-29 03:35:49 +0000
commitede14a1b32234685e2d6893205ff24c959b3f021 (patch)
tree698babb78ae6545bd3e45bde86df5b6f30e6ebab /drivers/gpu/drm/amd/pm/amdgpu_pm.c
parentamdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID (diff)
downloadkernel-ede14a1b32234685e2d6893205ff24c959b3f021.tar.gz
kernel-ede14a1b32234685e2d6893205ff24c959b3f021.zip
amdgpu/pm: set pp_dpm_dcefclk to readonly on NAVI10 and newer gpus
v2 : change condition to apply to all chips after NAVI10 Writing to dcefclk causes the gpu to become unresponsive, and requires a reboot. Patch prevents user from successfully writing to file pp_dpm_dcefclk on parts NAVI10 and newer, and gives better user feedback that this operation is not allowed. Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/pm/amdgpu_pm.c')
-rw-r--r--drivers/gpu/drm/amd/pm/amdgpu_pm.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 8128603ef495..4e459ef632ef 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1893,6 +1893,14 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
}
}
+ if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
+ /* SMU MP1 does not support dcefclk level setting */
+ if (asic_type >= CHIP_NAVI10) {
+ dev_attr->attr.mode &= ~S_IWUGO;
+ dev_attr->store = NULL;
+ }
+ }
+
#undef DEVICE_ATTR_IS
return 0;