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path: root/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c
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* drm/amd/display: fix graphics hang in multi-display mst caseGabe Teeger2024-09-021-10/+2
| | | | | | | | | | | | | | | | | | | [what] Graphics hang observed with 3 displays connected to DP2.0 mst dock. [why] There's a mismatch in dml and dc between the assignments of hpo link encoders. [how] Add a new array in dml that tracks the current mapping of HPO stream encoders to HPO link encoders in dc. Reviewed-by: Sung joon Kim <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Gabe Teeger <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: remove extraneous ; after statementsColin Ian King2024-08-131-1/+1
| | | | | | | | There are a several statements with two following semicolons, replace these with just one semicolon. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Check top sink only when multiple streams for DP2Sung Joon Kim2024-07-231-3/+3
| | | | | | | | | | | | | | | | | | | [why] When switching from extended to second display only mode, the top remote sink is not removed while the top stream itself is released. This causes DML to think there is no DP2 output encoder because top remote sink does not match with the second stream and disables DTBCLK and causes hang. [how] For DP2.0 MST hubs, only treat 1st remote sink as an encoder only when there are multiple displays connected. Reviewed-by: Michael Strauss <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix array-index-out-of-bounds in dml2/FCLKChangeSupportRoman Li2024-07-011-1/+1
| | | | | | | | | | | | | | | | | [Why] Potential out of bounds access in dml2_calculate_rq_and_dlg_params() because the value of out_lowest_state_idx used as an index for FCLKChangeSupport array can be greater than 1. [How] Currently dml2 core specifies identical values for all FCLKChangeSupport elements. Always use index 0 in the condition to avoid out of bounds access. Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Choose HUBP unbounded request based on DML outputSung Joon Kim2024-07-011-10/+2
| | | | | | | | | | | | | | | | | | | | [why] Previously, we decide on the unbounded request purely based on pipe_cnt which is a wrong variable to use to determine how many pipes are in "use". DML already accounts for number of pipes in use along with other various factors and is a more reliable method of determination. [how] Use UnboundedRequestEnabledThisState to decide on unbounbded_req_enabled. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add dwb support to dml2Charlene Liu2024-04-101-0/+65
| | | | | | | | | | | | | | | | | | | | [why] dwb was not POR previosly. now need to enable dwb in dml2. Limitation: HW DML assumes only one DWB one set of watermark for all 4 watermark sets one stream has one DWB only. WB scaling dml input has one set of scaling tap. (no chroma so far) needs to follow up Reviewed-by: Chris Park <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix compiler warnings on high compiler warning levelsAric Cyr2024-04-101-1/+1
| | | | | | | | | | | | | | | | [why] Enabling higher compiler warning levels results in many issues that can be trivially resolved as well as some potentially critical issues. [how] Fix all compiler warnings found with various compilers and higher warning levels. Primarily, potentially uninitialized variables and unreachable code. Reviewed-by: Leo Li <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Skip pipe if the pipe idx not set properlyMuhammad Ahmed2024-03-271-0/+5
| | | | | | | | | | | | | | [why] Driver crashes when pipe idx not set properly [how] Add code to skip the pipe that idx not set properly Reviewed-by: Charlene Liu <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Muhammad Ahmed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: fix debug key not working on dml2Charlene Liu2024-03-221-0/+6
| | | | | | | | | | | [why] need to apply the debug key check for max displayclk. Reviewed-by: Chris Park <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Simplify the calculation of variablesJiapeng Chong2024-02-071-1/+1
| | | | | | | | | ./drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c:236:49-51: WARNING !A || A && B is equivalent to !A || B. Reported-by: Abaci Robot <[email protected]> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=8169 Signed-off-by: Jiapeng Chong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix Mismatch between pipe and streamGabe Teeger2024-01-031-3/+3
| | | | | | | | | | | | | | | | [Why] Failing mode validation during dc_commit, leading to blackscreen with an 8k DP2 display during mode change. [What] Fix mixmatch between pipe and stream, which prevented us from recognizing the link as DP2. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Gabe Teeger <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix lightup regression with DP2 single display configsMichael Strauss2023-12-191-0/+8
| | | | | | | | | | | | | | | [WHY] Previous fix for multiple displays downstream of DP2 MST hub caused regression [HOW] Match sink IDs instead of sink struct addresses Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Refactor dc_state interfaceDillon Varone2023-12-191-2/+4
| | | | | | | | | | | | | | | | | | | [WHY?] Part of the dc_state interface that deals with adding streams and planes should remain public, while others that deal with internal status' and subvp should be private to DC. [HOW?] Move and rename the public functions to dc_state.h and private functions to dc_state_priv.h. Also add some additional functions for extracting subvp meta data from the state. Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Revert DP2 MST hub triple display fixMichael Strauss2023-12-131-7/+0
| | | | | | | | | | | | | [WHY] Introduces regression with DP2 native displays [HOW] Revert the change Reviewed-by: Charlene Liu <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix null pointerJohnson Chen2023-12-061-0/+2
| | | | | | | | | | Add guard for NULL pointer access Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Johnson Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Only enumerate top local sink as DP2 outputMichael Strauss2023-12-061-0/+9
| | | | | | | | | | | | | | | | | | [WHY] Many DCN generations only have two HPO link encoders and therefore only support driving a max of two DP2 PHYs. DP2 MST hubs currently can not pass 3x display validation as each downstream sink is enumerated as separate DP2 output. [HOW] Count MST hubs once by treating only 1st remote sink in topology as an encoder. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: always use mpc factor of 2 for stereo timingsWenjing Liu2023-11-291-1/+1
| | | | | | | | | | | | | [why] In the new pipe resource management logic, the special handling for stereo timings is missing. This commit implements the same stereo timings handling as old pipe resource management code. Reviewed-by: Chaitanya Dhere <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix handling duplicate planes on one streamSung Joon Kim2023-11-071-7/+11
| | | | | | | | | | | | | | | | | | | | | [why] DML2 does not handle the case when we have a single stream sourcing 2 or more planes that are duplicates of one another. To properly handle this scenario, pipe index to plane index mapping is used to decide which plane is being processed and programmed. [how] Create static array of pipe index to plane index map. Populate the array properly and use in appropriate places. Reviewed-by: Xi (Alex) Liu <[email protected]> Acked-by: Hersen Wu <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Hersen Wu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix copyright notice in DML2 codeStylon Wang2023-10-261-0/+2
| | | | | | | | | [Why & How] Fix incomplete copyright notice in DML2 code. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Stylon Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Move stereo timing check to helperTaimur Hassan2023-10-091-0/+17
| | | | | | | | | | Rework dml2_map_dc_pipes to keep the logic clean. Reviewed-by: Chaitanya Dhere <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Use fixed DET Buffer SizeSung Joon Kim2023-10-091-9/+13
| | | | | | | | | | | | | | | [why] Regression from DML1.0 where we use differen DET buffer sizes for each pipe. From the spec, we need to use DET buffer size of 384 kb for each pipe [how] Ensure to use 384 kb DET buffer sizes for each available pipe. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Handle multiple streams sourcing same surfaceSung Joon Kim2023-10-091-7/+12
| | | | | | | | | | | | | | | | [why] There are cases where more than 1 stream can be mapped to the same surface. DML2.0 does not seem to handle these cases. [how] Make sure to account for the stream id when deriving the plane id. By doing this, each plane id will be unique based on the stream id. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add z8_marks in dmlCharlene Liu2023-10-091-0/+2
| | | | | | | | | Add z8 watermarks to struct for later ASIC use. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Introduce DML2Qingqing Zhuo2023-10-091-0/+452
DC is transitioning from DML to DML2, and this commit introduces all the required changes for some of the already available ASICs and adds the required code infra to support new ASICs under DML2. DML2 is also a generated code that provides better mode verification and programming models for software/hardware, and it enables a better way to create validation tools. This version is more like a middle step to the complete transition to the DML2 version. Changes since V1: - Alex: Fix typos Changes since V2: - Update DC includes Changes since V3: - Fix 32 bit compilation issues on x86 Changes since V4: - Avoid compilation of DML2 on some not supported 32-bit architecture - Update commit message Co-developed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Co-developed-by: Roman Li <[email protected]> Signed-off-by: Roman Li <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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