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* drm/amd/display: Only restore backlight after amdgpu_dm_init or dm_resumeMatthew Schwartz2025-09-231-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On clients that utilize AMD_PRIVATE_COLOR properties for HDR support, brightness sliders can include a hardware controlled portion and a gamma-based portion. This is the case on the Steam Deck OLED when using gamescope with Steam as a client. When a user sets a brightness level while HDR is active, the gamma-based portion and/or hardware portion are adjusted to achieve the desired brightness. However, when a modeset takes place while the gamma-based portion is in-use, restoring the hardware brightness level overrides the user's overall brightness level and results in a mismatch between what the slider reports and the display's current brightness. To avoid overriding gamma-based brightness, only restore HW backlight level after boot or resume. This ensures that the backlight level is set correctly after the DC layer resets it while avoiding interference with subsequent modesets. Fixes: 7875afafba84 ("drm/amd/display: Fix brightness level not retained over reboot") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4551 Signed-off-by: Matthew Schwartz <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]> (cherry picked from commit a490c8d77d500b5981e739be3d59c60cfe382536) Cc: [email protected]
* drm/amd/display: Deprecate Loading Bounding Box From DMUB On DCN4Austin Zheng2025-06-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] dml2_soc_bb struct can continuously receive updates for future ASICs. Alignment issues may arise since VBIOS DMCUB contains an older version of the SOC BB. Populating the bounding box with values from DMCUB is no longer necessary since values such as UCLK will be overridden by values acquired by PMFW anyways. [HOW] Use bb_from_dmub to store DCN specific bounding box parameters in DMCUB. Add helpers to translate DCN specific struct to the corresponding dml2_soc_bb field. To avoid alignment issues: Deprecate applying DMCUB SoC BB for DCN4 For future projects: Create a flattened struct containing all sensitive parameters in the bounding box. New parameters can be added to the bottom of the new struct as needed. Reviewed-by: Dillon Varone <[email protected]> Signed-off-by: Austin Zheng <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Restructure DMI quirksMario Limonciello2025-05-131-0/+9
| | | | | | | | | | | | | | | | [Why] DMI quirks are relatively big code that makes amdgpu_dm 200 lines larger. [How] Move DMI quirks into a dedicated source file and make all quirks variables for `struct amdgpu_display_manager`. Reviewed-by: Alex Hung <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Ray Wu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add htmldocs description for fused_io interfaceRoman Li2025-04-111-0/+5
| | | | | | | | | | | | | | | [Why] htmldocs build warning: "Function parameter or struct member 'fused_io' not described in 'amdgpu_display_manager'". [How] Add missing description. Fixes: ce801e5d6c1b ("drm/amd/display: HDCP Locality check using DMUB Fused IO") Reported-by: Stephen Rothwell <[email protected]> Signed-off-by: Roman Li <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: HDCP Locality check using DMUB Fused IODominik Kaszewski2025-04-071-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] HDCP locality check has strict timing requirements, currently broken due to reliance on msleep which does not guarantee accuracy. The PR moves the write-poll-read sequence into DMUB using new generic Fused IO interface, where the timing accuracy is greatly improved. New flow is enabled using DCN resource capability bit (none for now), or using a debug flag. [How] * Extended mod_hdcp_config with new function for requesting DMUB to execute a sequence of fused I2C/AUX commands and synchronously wait until an outbox reply arrives or a timeout expires. * If the timeout expires, send an abort to DMUB. * Update HDCP to use the DMUB for locality check if supported. * Add DC_HDCP_LC_FORCE_FW_ENABLE and DC_HDCP_LC_ENABLE_SW_FALLBACK. * Make the first enable new flow regardless of resource capabilities. * Make the second enable fallback to old SW flow. * Clean up makefile source file listings for easier updates. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Dominik Kaszewski <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: use drm_err in hpd rx offloadAurabindo Pillai2025-04-071-0/+4
| | | | | | | | | | | | add amdgpu_device pointer to data associated with the work struct such that hpd handlers has access to the drm device for use with drm_err() Reviewed-by: Alex Hung <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Fangzhi Zuo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Merge tag 'amd-drm-next-6.15-2025-03-07' of ↵Dave Airlie2025-03-091-0/+20
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.freedesktop.org/agd5f/linux into drm-next amdgpu: - Fix spelling typos - RAS updates - VCN 5.0.1 updates - SubVP fixes - DCN 4.0.1 fixes - MSO DPCD fixes - DIO encoder refactor - PCON fixes - Misc cleanups - DMCUB fixes - USB4 DP fixes - DM cleanups - Backlight cleanups and fixes - Support platform backlight curves - Misc code cleanups - SMU 14 fixes - JPEG 4.0.3 reset updates - SR-IOV fixes - SVM fixes - GC 12 DCC fixes - DC DCE 6.x fix - Hiberation fix amdkfd: - Fix possible NULL pointer in queue validation - Remove unnecessary CP domain validation - SDMA queue reset support - Add per process flags radeon: - Fix spelling typos - RS400 hyperZ fix UAPI: - Add KFD per process flags for setting precision Proposed user space: https://github.com/ROCm/ROCR-Runtime/commit/2a64fa5e06e80e0af36df4ce0c76ae52eeec0a9d Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
| * drm/amd: Pass luminance data to amdgpu_dm_backlight_capsMario Limonciello2025-03-051-0/+20
| | | | | | | | | | | | | | | | | | | | The ATIF method on some systems will provide a backlight curve. Pass this curve into amdgpu_dm add it to the structures. Reviewed-by: Alex Hung <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | Merge tag 'amd-drm-next-6.15-2025-02-21' of ↵Dave Airlie2025-02-261-1/+8
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.15-2025-02-21: amdgpu: - Add OEM i2c support for RGB lights, etc. - Add support for GC 11.5.3 - Add support for GC 11.5.2 - Add support for SDMA 6.1.3 - Add support for NBIO 7.11.2 - Add support for NBIO 7.9.1 - Add support for MMHUB 3.3.2 - Add support for MMHUB 1.8.1 - Add support for SMU 14.0.5 - Add support for SMUIO 13.0.11 - Add support for PSP 14.0.5 - Add support for UMC 12.5.0 - Add support for DCN 3.6.0 - JPEG 4.0.3 updates - Add dynamic workload profile switching for GC 10-12 - support larger vbios sizes - GC 9.5.0 updates - SMU 13.0.12 updates - SMU 13.0.6 updates - IP discovery updates - GC 10 queue reset updates - DCN 4.0.1 updates - UHBR link rate fixes - Aborted suspend fix - Mark gttsize parameter as deprecated - GC 10 cleaner shader updates - PSR-SU fixes - Clean up PM4 headers - Cursor fixes - Enable devcoredump for JPEG - Misc cleanups - Runpm cleanups - MES updates - GC 9 gfxoff fixes - Vbios fetching cleanups - Documentation updates - Update secondary plane handling - DML2 updates - SDMA fixes for MI - Cleaner shader fixes for GC 11/12 - ACA updates - Initial JPEG queue reset support - RAS updates - Initial RAS CPER support - DCN/DCE panic screen handling cleanup - BT2020 fixes - SR-IOV fixes amdkfd: - synchronize pasid values between KGD and KFD - Misc cleanups - Improve GTT/VRAM handling for APUs - Topology updates - Fix user queue validation on GC 7/8 UAPI: - Enable "Broadcast RGB" drm property - Add INFO IOCTL query for virtualization mode Proposed userspace: https://github.com/ROCm/amdsmi/commit/e663bed7d6b3df79f5959e73981749b1f22ec698 From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Dave Airlie <[email protected]>
| * drm/amd/display: Don't treat wb connector as physical in ↵Harry Wentland2025-02-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | create_validate_stream_for_sink Don't try to operate on a drm_wb_connector as an amdgpu_dm_connector. While dereferencing aconnector->base will "work" it's wrong and might lead to unknown bad things. Just... don't. Reviewed-by: Alex Hung <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amd/display/dm: add support for OEM i2c busAlex Deucher2025-02-131-0/+7
| | | | | | | | | | | | | | | | Expose the OEM i2c bus on boards that support it. This bus is used for OEM specific features like RGB, etc. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | Merge drm/drm-next into drm-misc-nextMaxime Ripard2025-02-061-4/+12
|\| | | | | | | | | | | Bring rc1 to start the new release dev. Signed-off-by: Maxime Ripard <[email protected]>
| * drm/amd/display: Reduce accessing remote DPCD overheadWayne Lin2025-01-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Observed frame rate get dropped by tool like glxgear. Even though the output to monitor is 60Hz, the rendered frame rate drops to 30Hz lower. It's due to code path in some cases will trigger dm_dp_mst_is_port_support_mode() to read out remote Link status to assess the available bandwidth for dsc maniplation. Overhead of keep reading remote DPCD is considerable. [How] Store the remote link BW in mst_local_bw and use end-to-end full_pbn as an indicator to decide whether update the remote link bw or not. Whenever we need the info to assess the BW, visit the stored one first. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3720 Fixes: fa57924c76d9 ("drm/amd/display: Refactor function dm_dp_mst_is_port_support_mode()") Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Reviewed-by: Jerry Zuo <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Signed-off-by: Tom Chung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amd/display: add CEC notifier to amdgpu driverKun Liu2025-01-101-0/+6
| | | | | | | | | | | | | | | | | | | | This patch adds the cec_notifier feature to amdgpu driver. The changes will allow amdgpu driver code to notify EDID and HPD changes to an eventual CEC adapter. Signed-off-by: Kun Liu <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amd/display: Adjust secure_display_context data structureWayne Lin2024-12-101-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Variables relates to secure display are spreading out within struct amdgpu_display_manager. [How] Encapsulate relevant variables into struct secure_display_context and adjust relevant affected codes. Reviewed-by: HaoPing Liu <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amd/display: Fix phy id mapping issue for secure displayWayne Lin2024-12-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Under mst scenario, mst streams are from the same link_enc_hw_inst. As the result, can't utilize that as the phy index for distinguising different stream sinks. [How] Sort the connectors by: link_enc_hw_instance->mst tree depth->mst RAD After sorting the phy index assignment, store connector's relevant info into dm mapping array. Once need the index, just look up the static array. Reviewed-by: HaoPing Liu <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | drm/connector: make mode_valid take a const struct drm_display_modeDmitry Baryshkov2025-01-071-1/+1
|/ | | | | | | | | | | | | | | | | The mode_valid() callbacks of drm_encoder, drm_crtc and drm_bridge take a const struct drm_display_mode argument. Change the mode_valid callback of drm_connector to also take a const argument. Acked-by: Jani Nikula <[email protected]> Reviewed-by: Liviu Dudau <[email protected]> Reviewed-by: Raphael Gallais-Pou <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Reviewed-by: Maxime Ripard <[email protected]> Reviewed-by: Thomas Zimmermann <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20241214-drm-connector-mode-valid-const-v2-5-4f9498a4c822@linaro.org Signed-off-by: Dmitry Baryshkov <[email protected]>
* drm/amd/display: Change some variable name of psrTom Chung2024-11-081-1/+1
| | | | | | | | | | Panel Replay feature may also use the same variable with PSR. Change the variable name and make it not specify for PSR. Reviewed-by: Leo Li <[email protected]> Signed-off-by: Tom Chung <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: switch amdgpu_dm_connector to use struct drm_edidMelissa Wen2024-10-071-2/+2
| | | | | | | | | | | | | | Replace raw edid handling (struct edid) with the opaque EDID type (struct drm_edid) on amdgpu_dm_connector for consistency. It may also prevent mismatch of approaches in different parts of the driver code. Signed-off-by: Melissa Wen <[email protected]> Co-developed-by: Mario Limonciello <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: fix a memleak issue when driver is removedAurabindo Pillai2024-10-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Running "modprobe amdgpu" the second time (followed by a modprobe -r amdgpu) causes a call trace like: [ 845.212163] Memory manager not clean during takedown. [ 845.212170] WARNING: CPU: 4 PID: 2481 at drivers/gpu/drm/drm_mm.c:999 drm_mm_takedown+0x2b/0x40 [ 845.212177] Modules linked in: amdgpu(OE-) amddrm_ttm_helper(OE) amddrm_buddy(OE) amdxcp(OE) amd_sched(OE) drm_exec drm_suballoc_helper drm_display_helper i2c_algo_bit amdttm(OE) amdkcl(OE) cec rc_core sunrpc qrtr intel_rapl_msr intel_rapl_common snd_hda_codec_hdmi edac_mce_amd snd_hda_intel snd_intel_dspcfg snd_intel_sdw_acpi snd_usb_audio snd_hda_codec snd_usbmidi_lib kvm_amd snd_hda_core snd_ump mc snd_hwdep kvm snd_pcm snd_seq_midi snd_seq_midi_event irqbypass crct10dif_pclmul snd_rawmidi polyval_clmulni polyval_generic ghash_clmulni_intel sha256_ssse3 sha1_ssse3 snd_seq aesni_intel crypto_simd snd_seq_device cryptd snd_timer mfd_aaeon asus_nb_wmi eeepc_wmi joydev asus_wmi snd ledtrig_audio sparse_keymap ccp wmi_bmof input_leds k10temp i2c_piix4 platform_profile rapl soundcore gpio_amdpt mac_hid binfmt_misc msr parport_pc ppdev lp parport efi_pstore nfnetlink dmi_sysfs ip_tables x_tables autofs4 hid_logitech_hidpp hid_logitech_dj hid_generic usbhid hid ahci xhci_pci igc crc32_pclmul libahci xhci_pci_renesas video [ 845.212284] wmi [last unloaded: amddrm_ttm_helper(OE)] [ 845.212290] CPU: 4 PID: 2481 Comm: modprobe Tainted: G W OE 6.8.0-31-generic #31-Ubuntu [ 845.212296] RIP: 0010:drm_mm_takedown+0x2b/0x40 [ 845.212300] Code: 1f 44 00 00 48 8b 47 38 48 83 c7 38 48 39 f8 75 09 31 c0 31 ff e9 90 2e 86 00 55 48 c7 c7 d0 f6 8e 8a 48 89 e5 e8 f5 db 45 ff <0f> 0b 5d 31 c0 31 ff e9 74 2e 86 00 66 0f 1f 84 00 00 00 00 00 90 [ 845.212302] RSP: 0018:ffffb11302127ae0 EFLAGS: 00010246 [ 845.212305] RAX: 0000000000000000 RBX: ffff92aa5020fc08 RCX: 0000000000000000 [ 845.212307] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000000 [ 845.212309] RBP: ffffb11302127ae0 R08: 0000000000000000 R09: 0000000000000000 [ 845.212310] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000004 [ 845.212312] R13: ffff92aa50200000 R14: ffff92aa5020fb10 R15: ffff92aa5020faa0 [ 845.212313] FS: 0000707dd7c7c080(0000) GS:ffff92b93de00000(0000) knlGS:0000000000000000 [ 845.212316] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 845.212318] CR2: 00007d48b0aee200 CR3: 0000000115a58000 CR4: 0000000000f50ef0 [ 845.212320] PKRU: 55555554 [ 845.212321] Call Trace: [ 845.212323] <TASK> [ 845.212328] ? show_regs+0x6d/0x80 [ 845.212333] ? __warn+0x89/0x160 [ 845.212339] ? drm_mm_takedown+0x2b/0x40 [ 845.212344] ? report_bug+0x17e/0x1b0 [ 845.212350] ? handle_bug+0x51/0xa0 [ 845.212355] ? exc_invalid_op+0x18/0x80 [ 845.212359] ? asm_exc_invalid_op+0x1b/0x20 [ 845.212366] ? drm_mm_takedown+0x2b/0x40 [ 845.212371] amdgpu_gtt_mgr_fini+0xa9/0x130 [amdgpu] [ 845.212645] amdgpu_ttm_fini+0x264/0x340 [amdgpu] [ 845.212770] amdgpu_bo_fini+0x2e/0xc0 [amdgpu] [ 845.212894] gmc_v12_0_sw_fini+0x2a/0x40 [amdgpu] [ 845.213036] amdgpu_device_fini_sw+0x11a/0x590 [amdgpu] [ 845.213159] amdgpu_driver_release_kms+0x16/0x40 [amdgpu] [ 845.213302] devm_drm_dev_init_release+0x5e/0x90 [ 845.213305] devm_action_release+0x12/0x30 [ 845.213308] release_nodes+0x42/0xd0 [ 845.213311] devres_release_all+0x97/0xe0 [ 845.213314] device_unbind_cleanup+0x12/0x80 [ 845.213317] device_release_driver_internal+0x230/0x270 [ 845.213319] ? srso_alias_return_thunk+0x5/0xfbef5 This is caused by lost memory during early init phase. First time driver is removed, memory is freed but when second time the driver is inserted, VBIOS dmub is not active, since the PSP policy is to retain the driver loaded version on subsequent warm boots. Hence, communication with VBIOS DMUB fails. Fix this by aborting further communication with vbios dmub and release the memory immediately. Fixes: f59549c7e705 ("drm/amd/display: free bo used for dmub bounding box") Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Add dmub hpd sense callbackRoman Li2024-09-181-1/+1
| | | | | | | | | | | | | | | | [WHY] HPD sense notification has been implemented in DMUB, which can occur during low power states and need to be notified from firmware to driver. [HOW] Define callback and register new HPD sense notification. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Roman Li <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Revert "drm/amd: Add power_saving_policy drm property to eDP connectors"Hamza Mahfooz2024-08-021-2/+0
| | | | | | | | | | This reverts commit 9d8c094ddab05db88d183ba82e23be807848cad8. It was merged without meeting userspace requirements. Signed-off-by: Hamza Mahfooz <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
* Merge drm/drm-next into drm-misc-nextThomas Zimmermann2024-07-291-2/+53
|\ | | | | | | | | | | Backmerging to get a late RC of v6.10 before moving into v6.11. Signed-off-by: Thomas Zimmermann <[email protected]>
| * drm/amd/display: Add function banner for idle_workqueueRoman Li2024-07-161-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] htmldocs warning: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h: warning: Function parameter or struct member 'idle_workqueue' not described in 'amdgpu_display_manager'. [How] Add comment section for idle_workqueue with param description. Reported-by: Stephen Rothwell <[email protected]> Link: https://lore.kernel.org/dri-devel/[email protected]/ Signed-off-by: Roman Li <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amd/display: fix doc entry for bb_from_dmubAurabindo Pillai2024-07-151-1/+3
| | | | | | | | | | | | | | | | | | | | | | Fixes the warning: Function parameter or struct member 'bb_from_dmub' not described in 'amdgpu_display_manager' Reported-by: Stephen Rothwell <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amd/display: Use periodic detection for ipx/headlessRoman Li2024-06-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] Hotplug is not detected in headless (no eDP) mode on dcn35x. With no display dcn35x goes to IPS2 powersaving state where HPD interrupt is not handled. [HOW] Use idle worker thread for periodic detection of HPD in headless mode. Reviewed-by: Aurabindo Pillai <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amd/display: Introduce overlay cursor modeLeo Li2024-06-141-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] DCN is the display hardware for amdgpu. DRM planes are backed by DCN hardware pipes, which carry pixel data from one end (memory), to the other (output encoder). Each DCN pipe has the ability to blend in a cursor early on in the pipeline. In other words, there are no dedicated cursor planes in DCN, which makes cursor behavior somewhat unintuitive for compositors. For example, if the cursor is in RGB format, but the top-most DRM plane is in YUV format, DCN will not be able to blend them. Because of this, amdgpu_dm rejects all configurations where a cursor needs to be enabled on top of a YUV formatted plane. From a compositor's perspective, when computing an allocation for hardware plane offloading, this cursor-on-yuv configuration result in an atomic test failure. Since the failure reason is not obvious at all, compositors will likely fall back to full rendering, which is not ideal. Instead, amdgpu_dm can try to accommodate the cursor-on-yuv configuration by opportunistically reserving a separate DCN pipe just for the cursor. We can refer to this as "overlay cursor mode". It is contrasted with "native cursor mode", where the native DCN per-pipe cursor is used. [How] On each crtc, compute whether the cursor plane should be enabled in overlay mode. If it is, mark the CRTC as requesting overlay cursor mode. Overlay cursor should be enabled whenever there exists a underlying plane that has YUV format, or is scaled differently than the cursor. It should also be enabled if there is no underlying plane, or if underlying planes do not cover the entire CRTC. During DC validation, attempt to enable a separate DCN pipe for the cursor if it's in overlay mode. If that fails, or if no overlay mode is requested, then fallback to native mode. v2: * Update commit message for when overlay cursor should be enabled * Also consider scale and no-underlying-plane case (cursor on crtc bg) * Consider all underlying planes when determinig overlay/native, not just the plane immediately beneath the cursor, as it may not cover the entire CRTC. * Fix typo s/decending/descending/ * Force native cursor on pre-DCN hardware Reviewed-by: Harry Wentland <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Leo Li <[email protected]> Acked-by: Harry Wentland <[email protected]> Acked-by: Pekka Paalanen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amd/display: Correct the defined value for AMDGPU_DMUB_NOTIFICATION_MAXWayne Lin2024-06-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | [Why & How] It actually exposes '6' types in enum dmub_notification_type. Not 5. Using smaller number to create array dmub_callback & dmub_thread_offload has potential to access item out of array bound. Fix it. Reviewed-by: Jerry Zuo <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amd/display: Set default brightness according to ACPIMario Limonciello2024-06-141-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, amdgpu will always set up the brightness at 100% when it loads. However this is jarring when the BIOS has it previously programmed to a much lower value. The ACPI ATIF method includes two members for "ac_level" and "dc_level". These represent the default values that should be used if the system is brought up in AC and DC respectively. Use these values to set up the default brightness when the backlight device is registered. v2: squash in ACPI fix Reviewed-by: Leo Li <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amd/display: Enable copying of bounding box data from VBIOS DMUBAurabindo Pillai2024-05-291-0/+10
| | | | | | | | | | | | | | | | | | Allocate some memory, send the address in chunks to dmub, and finally ask it to copy the bounding box data into the newly allocated memory. Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amd/display: Drop pixel_clock_mhzMario Limonciello2024-05-171-1/+0
| | | | | | | | | | | | | | | | | | | | The pixel_clock_mhz property is populated in amdgpu_dm when Freesync is setup, but it is not used anywhere in amdgpu_dm. Remove the dead code. Cc: [email protected] Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Tom Chung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amd/display: Add periodic detection for IPSRoman Li2024-04-301-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] HPD interrupt cannot be handled in IPS2 state. So if there's a display topology change while system in IPS2 it can be missed. [How] Implement worker to check each 5 sec in IPS for HPD. Reviewed-by: Hamza Mahfooz <[email protected]> Acked-by: Wayne Lin <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | drm/amd: Add power_saving_policy drm property to eDP connectorsMario Limonciello2024-07-101-0/+2
|/ | | | | | | | | | | | | | | | | When the `power_saving_policy` property is set to bit mask "Require color accuracy" ABM should be disabled immediately and any requests by sysfs to update will return an -EBUSY error. When the `power_saving_policy` property is set to bit mask "Require low latency" PSR should be disabled. When the property is restored to an empty bit mask ABM and PSR can be enabled again. Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Leo Li <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
* drm/amd/display: add debugfs disallow edp psrHersen Wu2024-01-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] fix reading edp rx crc timeout failure. after bootup, kernel setup psr with dpcd 0x170 = 5. this notify rx psr enable and let rx fw start checking crc for fw internal logic. rx fw may not update crc read count within dpcd 0x246. read count is always 0. this will lead tx crc reading timeout. [How] add debugfs to let test app to disbable rx crc checking for rx internal logic. then test app can read rx crc dpcd 0x246 successfully. expected app sequence is as below: 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2. 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but without dpcd 0x170 = 5. 4. read crc from rx dpcd 0x270, 0x246, etc. 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr. this will let eDP back to normal with psr setup dpcd 0x170 = 5. Reviewed-by: Wayne Lin <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Hersen Wu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Fix recent checkpatch errors in amdgpu_dmHarry Wentland2024-01-051-2/+2
| | | | | | | | | - Use tabs, not spaces. - Brace and parentheses placement Signed-off-by: Harry Wentland <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add plane CTM driver-specific propertyMelissa Wen2023-12-141-0/+7
| | | | | | | | | | | Plane CTM for pre-blending color space conversion. Only enable driver-specific plane CTM property on drivers that support both pre- and post-blending gamut remap matrix, i.e., DCN3+ family. Otherwise it conflits with DRM CRTC CTM property. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add plane shaper LUT supportMelissa Wen2023-12-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | Map DC shaper LUT to DM plane color management. Shaper LUT can be used to delinearize and/or normalize the color space for computational efficiency and achiving specific visual styles. If a plane degamma is apply to linearize the color space, a custom shaper 1D LUT can be used just before applying 3D LUT. v2: - use DPP color caps to verify plane 3D LUT support - add debug message if shaper LUT programming fails v4: - remove helper to check 3D LUT color caps (Harry) - update desc of lut3d-setup helper from MPC to DPP v5: - remove color_mgmt_changed check that prevents color updates (Joshua) Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add plane degamma TF and LUT supportJoshua Ashton2023-12-131-0/+1
| | | | | | | | | | | | | | Set DC plane with user degamma LUT or predefined TF from driver-specific plane color properties. If plane and CRTC degamma are set in the same time, plane degamma has priority. That means, we only set CRTC degamma if we don't have plane degamma LUT or TF to configure. We return -EINVAL if we don't have plane degamma settings, so we can continue and check CRTC degamma. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Joshua Ashton <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add CRTC gamma TF driver-specific propertyMelissa Wen2023-12-131-0/+8
| | | | | | | | | | | | | | | | | | | | | | | Add AMD pre-defined transfer function property to default DRM CRTC gamma to convert to wire encoding with or without a user gamma LUT. There is no post-blending regamma ROM for pre-defined TF. When setting Gamma TF (!= Identity) and LUT at the same time, the color module will combine the pre-defined TF and the custom LUT values into the LUT that's actually programmed. v2: - enable CRTC prop in the end of driver-specific prop sequence - define inverse EOTFs as supported regamma TFs - reword driver-specific function doc to remove shaper/3D LUT v3: - spell out TF+LUT behavior in the commit and comments (Harry) Reviewed-by: Harry Wentland <[email protected]> Co-developed-by: Joshua Ashton <[email protected]> Signed-off-by: Joshua Ashton <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add plane blend LUT and TF driver-specific propertiesJoshua Ashton2023-12-131-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Blend 1D LUT or a pre-defined transfer function (TF) can be set to linearize content before blending, so that it's positioned just before blending planes in the AMD color mgmt pipeline, and after 3D LUT (non-linear space). Shaper and Blend LUTs are 1D LUTs that sandwich 3D LUT. Drivers should advertize blend properties according to HW caps. There is no blend ROM for pre-defined TF. When setting blend TF (!= Identity) and LUT at the same time, the color module will combine the pre-defined TF and the custom LUT values into the LUT that's actually programmed. v3: - spell out TF+LUT behavior in the commit and comments (Harry) v5: - get blend blob correctly Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Joshua Ashton <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add plane shaper LUT and TF driver-specific propertiesMelissa Wen2023-12-131-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On AMD HW, 3D LUT always assumes a preceding shaper 1D LUT used for delinearizing and/or normalizing the color space before applying a 3D LUT. Add pre-defined transfer function to enable delinearizing content with or without shaper LUT, where AMD color module calculates the resulted shaper curve. We apply an inverse EOTF to go from linear values to encoded values. If we are already in a non-linear space and/or don't need to normalize values, we can bypass shaper LUT with a linear transfer function that is also the default TF value. There is no shaper ROM. When setting shaper TF (!= Identity) and LUT at the same time, the color module will combine the pre-defined TF and the custom LUT values into the LUT that's actually programmed. v2: - squash commits for shaper LUT and shaper TF - define inverse EOTF as supported shaper TFs v3: - spell out TF+LUT behavior in the commit and comments (Harry) - replace BT709 EOTF by inv OETF v5: - get shaper blob correctly (Joshua) Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add plane 3D LUT driver-specific propertiesMelissa Wen2023-12-131-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 3D LUT property for plane color transformations using a 3D lookup table. 3D LUT allows for highly accurate and complex color transformations and is suitable to adjust the balance between color channels. It's also more complex to manage and require more computational resources. Since a 3D LUT has a limited number of entries in each dimension we want to use them in an optimal fashion. This means using the 3D LUT in a colorspace that is optimized for human vision, such as sRGB, PQ, or another non-linear space. Therefore, userpace may need one 1D LUT (shaper) before it to delinearize content and another 1D LUT after 3D LUT (blend) to linearize content again for blending. The next patches add these 1D LUTs to the plane color mgmt pipeline. v3: - improve commit message about 3D LUT - describe the 3D LUT entries and size (Harry) v4: - advertise 3D LUT max size as the size of a single-dimension v5: - get lut3d blob correctly (Joshua) - fix doc about 3d-lut dimension size (Sebastian) Signed-off-by: Melissa Wen <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add plane HDR multiplier driver-specific propertyJoshua Ashton2023-12-131-0/+17
| | | | | | | | | | | | | | | | | Multiplier to 'gain' the plane. When PQ is decoded using the fixed func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on AMD at least) When sRGB is decoded, 1.0 -> 1.0. Therefore, 1.0 multiplier = 80 nits for SDR content. So if you want, 203 nits for SDR content, pass in (203.0 / 80.0). v4: - comment about the PQ TF need for L-to-NL (from Harry's review) Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Joshua Ashton <[email protected]> Co-developed-by: Melissa Wen <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: explicitly define EOTF and inverse EOTFMelissa Wen2023-12-131-8/+19
| | | | | | | | | | | | | | | | | Instead of relying on color block names to get the transfer function intention regarding encoding pixel's luminance, define supported Electro-Optical Transfer Functions (EOTFs) and inverse EOTFs, that includes pure gamma or standardized transfer functions. v3: - squash linear and unity TFs to identity (Pekka) - define the right TFs for BT.709 (Pekka and Harry) - add comment about AMD TF coefficients Suggested-by: Harry Wentland <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add plane degamma TF driver-specific propertyJoshua Ashton2023-12-131-0/+19
| | | | | | | | | | | | | | | | Allow userspace to tell the kernel driver the input space and, therefore, uses correct predefined transfer function (TF) to go from encoded values to linear values. v2: - rename TF enum prefix from DRM_ to AMDGPU_ (Harry) - remove HLG TF Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Joshua Ashton <[email protected]> Co-developed-by: Melissa Wen <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: add driver-specific property for plane degamma LUTMelissa Wen2023-12-131-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Hook up driver-specific atomic operations for managing AMD color properties. Create AMD driver-specific color management properties and attach them according to HW capabilities defined by `struct dc_color_caps`. First add plane degamma LUT properties that means user-blob and its size. We will add more plane color properties in the next patches. In addition, we define AMD_PRIVATE_COLOR to guard these driver-specific plane properties. Plane degamma can be used to linearize input space for arithmetical operations that are more accurate when applied in linear color. v2: - update degamma LUT prop description - move private color operations from amdgpu_display to amdgpu_dm_color v5: - get degamma blob correctly (Joshua) Reviewed-by: Harry Wentland <[email protected]> Co-developed-by: Joshua Ashton <[email protected]> Signed-off-by: Joshua Ashton <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Create amdgpu_dm_wb_connectorHarry Wentland2023-12-061-0/+8
| | | | | | | | | | | | | | | [WHY] We need to track the dc_link and it would get confusing if re-using the amdgpu_dm_connector. [HOW] Creating new amdgpu_dm_wb_connector. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alex Hung <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/display: Return drm_connector from find_first_crtc_matching_connectorHarry Wentland2023-12-061-1/+1
| | | | | | | | | | | | | | | [WHY] We will be dealing with two types of connector: amdgpu_dm_connector and drm_writeback_connector. [HOW] We want to find both and then cast to the appriopriate type afterwards. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alex Hung <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Revert "drm/amd/display: Return drm_connector from ↵Alex Hung2023-10-131-1/+1
| | | | | | | | | | | | | find_first_crtc_matching_connector" This reverts commit ca2b37a1c249d05f21eeb7522489036efbc6c7f8. [WHY & HOW] The writeback series cause a regression in thunderbolt display. Signed-off-by: Alex Hung <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Revert "drm/amd/display: Create amdgpu_dm_wb_connector"Alex Hung2023-10-131-8/+0
| | | | | | | | | | | This reverts commit a5f9523c9ca352d6454e81ff9e9a4419f457210a. [WHY & HOW] The writeback series cause a regression in thunderbolt display. Signed-off-by: Alex Hung <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
generated by cgit (git 2.51.2) at 2025-12-01 03:01:21 +0000