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path: root/drivers/gpu/drm/amd/amdgpu/soc21.c
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* drm/amdgpu: Use function for IP version checkLijo Lazar2023-09-201-6/+6
| | | | | | | | | Use an inline function for version check. Gives more flexibility to handle any format changes. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/soc21: don't remap HDP registers for SR-IOVAlex Deucher2023-09-111-1/+1
| | | | | | | | This matches the behavior for soc15 and nv. Acked-by: Christian König <[email protected]> Reviewed-by: Timmy Tsai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable PG flags for VCNSaleemkhan Jamadar2023-08-311-0/+2
| | | | | | | | Enable PG flags for VCN and Jpeg on IP 11_5_0 Signed-off-by: Saleemkhan Jamadar <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/soc21: Add video cap query support for VCN_4_0_5Saleemkhan Jamadar2023-08-311-0/+1
| | | | | | | | Added the video capability query support for VCN version 4_0_5 Signed-off-by: Saleemkhan Jamadar <[email protected]> Reviewed-by: Veerabadhran Gopalakrishnan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu:enable CG and PG flags for VCNSaleemkhan Jamadar2023-08-311-2/+4
| | | | | | | | Enable CG and PG flags for VCN on IP 11_5_0 Signed-off-by: Saleemkhan Jamadar <[email protected]> Acked-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add doorbell index for VPELang Yu2023-08-311-0/+1
| | | | | | | Add doorbell index for Video Processing Engine. Signed-off-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/soc21: add initial GC 11.5.0 soc21 supportPrike Liang2023-08-301-0/+6
| | | | | | | Disable clock gating and power gating on the early bring up phase. Signed-off-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Clean up errors in soc21.cRan Sun2023-08-091-20/+10
| | | | | | | | | Fix the following errors reported by checkpatch: ERROR: that open brace { should be on the previous line Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Use nbio callback for nv and soc21Lijo Lazar2023-08-071-11/+1
| | | | | | | | | Make the new ascis to follow nbio callback method to get pcie replay count. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: retire set_vga_state for some ASICLikun Gao2023-06-091-6/+0
| | | | | | | | | | set_vga_state operation only allowed on SI generation ASIC, retire the realted function on those ASIC which did not do anything. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: change gfx 11.0.4 external_id rangeYifan Zhang2023-06-091-1/+1
| | | | | | | | | | | gfx 11.0.4 range starts from 0x80. Fixes: 311d52367d0a ("drm/amdgpu: add soc21 common ip block support for GC 11.0.4") Signed-off-by: Yifan Zhang <[email protected]> Reported-by: Yogesh Mohan Marimuthu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Enable doorbell selfring after resize FB BARShane Xiao2023-06-091-10/+13
| | | | | | | | | | | | | | | | | | | | | | | | | [Why] The selfring doorbell aperture will change when resize FB BAR successfully during gmc sw init, we should reorder the sequence of enabling doorbell selfring aperture. [How] Move enable_doorbell_selfring_aperture from *_common_hw_init to *_common_late_init. This fixes the potential issue that GPU ring its own doorbell when this device is in translated mode when iommu is on. v2: Remove *_enable_doorbell_aperture functions (Christian) v3: Add comments to note that why we need enable doorbell selfring late (Christian) Signed-off-by: Shane Xiao <[email protected]> Signed-off-by: Aaron Liu <[email protected]> Tested-by: Xiaomeng Hou <[email protected]> Reviewed-by: Christian K�nig <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add xcc index argument to rlc safe_mode func (v4)Le Ma2023-04-181-2/+2
| | | | | | | | | | | | | v1: To support multple XCD case (Le) v2: unify naming style (Le) v3: apply the changes to gc v11_0 (Hawking) v4: apply the changes to gc SOC21 (Morris) Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Morris Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add xcc index argument to select_sh_se function v2Le Ma2023-04-181-2/+2
| | | | | | | | | | v1: To support multiple XCD case (Le) v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking) Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Add fatal error handling in nbio v4_3Hawking Zhang2023-03-311-1/+14
| | | | | | | | | | | | | GPU will stop working once fatal error is detected. it will inform driver to do reset to recover from the fatal error. v2: squash in logic fix (Srinivasan) v3: squash in logic fix (Dan) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Candice Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Retire pcie_gen3_enable functionHawking Zhang2023-03-151-17/+0
| | | | | | | | | Not needed since from vi. drop the function so we don't duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Move to common helper to query soc rev_idHawking Zhang2023-03-151-6/+1
| | | | | | | | | | Replace soc15, nv, soc21 get_rev_id callback with common helper so we don't need to duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Move to common indirect reg access helperHawking Zhang2023-03-151-44/+4
| | | | | | | | | | | Replace soc15, nv, soc21 specific callbacks with common one. so we don't need to duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/vcn: custom video info caps for sriovJane Jian2023-03-131-10/+93
| | | | | | | | | for sriov, we added a new flag to indicate av1 support, this will override the original caps info. Signed-off-by: Jane Jian <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/soc21: Add video cap query support for VCN_4_0_4Veerabadhran Gopalakrishnan2023-03-081-0/+1
| | | | | | | | Added the video capability query support for VCN version 4_0_4 Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: fix error checking in amdgpu_read_mm_registers for soc21Alex Deucher2023-03-071-3/+4
| | | | | | | | Properly skip non-existent registers as well. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2442 Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/amdgpu: enable athub cg 11.0.3Kenneth Feng2023-02-081-1/+3
| | | | | | | | enable athub cg on gc 11.0.3 Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable HDP SD for gfx 11.0.3Evan Quan2023-01-311-1/+2
| | | | | | | | Enable HDP clock gating control for gfx 11.0.3. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/vcn4: add missing encoder capAlex Deucher2023-01-241-0/+1
| | | | | | | VCN4.x supports AV1 encode. Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/soc21: don't expose AV1 if VCN0 is harvestedAlex Deucher2023-01-191-13/+48
| | | | | | | Only VCN0 supports AV1. Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable VCN DPG for GC IP v11.0.4Saleemkhan Jamadar2023-01-031-0/+1
| | | | | | | | Enable VCN Dynamic Power Gating control for GC IP v11.0.4. Signed-off-by: Saleemkhan Jamadar <[email protected]> Reviewed-by: Veerabadhran Gopalakrishnan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable GFX IP v11.0.4 CG supportTim Huang2022-12-061-1/+17
| | | | | | | | Add CG support for GFX/MC/HDP/ATHUB/IH/BIF. Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Add nv mailbox irq in soc21YuBiao Wang2022-12-011-1/+17
| | | | | | | | | Under virtualization guest needs to receive notification from host to perform reset in some cases. Add nv mailbox irq in soc21. Signed-off-by: YuBiao Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* amdgpu/nv.c: Corrected typo in the video capabilities resolutionVeerabadhran Gopalakrishnan2022-11-291-1/+1
| | | | | | | | | | | | | Corrected the typo in the 4K resolution parameters. Fixes: b3a24461f9fb15 ("amdgpu/nv.c - Added codec query for Beige Goby") Fixes: 9075096b09e590 ("amdgpu/nv.c - Optimize code for video codec support structure") Fixes: 9ac0edaa0f8323 ("drm/amdgpu: add vcn_4_0_0 video codec query") Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Acked-by: Luben Tuikov <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Enable pg/cg flags on GC11_0_4 for VCNSaleemkhan Jamadar2022-11-291-2/+5
| | | | | | | | | | This enable VCN PG, CG and JPEG PG, CG Signed-off-by: Saleemkhan Jamadar <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.11Tim Huang2022-11-291-0/+1
| | | | | | | | | Set the default reset method to mode2 for SMU IP v13.0.11 Signed-off-by: Tim Huang <[email protected]> Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add soc21 common ip block support for GC 11.0.4Yifan Zhang2022-11-291-0/+6
| | | | | | | | Add common soc21 ip block support for GC 11.0.4. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/pm: enable mode1 reset on smu_v13_0_10Kenneth Feng2022-11-091-0/+1
| | | | | | | | | | | enable mode1 reset and prioritize debug port on smu_v13_0_10 as a more reliable message processing v2 - move mode1 reset callback to smu_v13_0_0_ppt.c Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Yang Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Clean up soc21 early init for SRIOVYiqing Yao2022-11-041-9/+3
| | | | | | | | Use virt_init_setting instead of per ip version setting. Signed-off-by: Yiqing Yao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Enable gmc soft reset on gmc_v11_0_3YiPeng Chai2022-10-171-0/+1
| | | | | | | | Enable gmc soft reset on gmc_v11_0_3. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/amdgpu: enable gfx clock gating features on smu_v13_0_10Kenneth Feng2022-10-171-1/+5
| | | | | | | | enable gfx clock gating features on smu_v13_0_10 Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Jack Gui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Enable VCN PG on GC11_0_1Sonny Jiang2022-10-061-0/+1
| | | | | | | | | Enable VCN PG on GC11_0_1 Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.0.x
* drm/amdgpu: Enable VCN DPG for GC11_0_1Sonny Jiang2022-09-301-0/+1
| | | | | | | | Enable VCN DPG on GC11_0_1 Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Enable full reset when RAS is supported on gc v11_0_0Candice Li2022-09-131-0/+1
| | | | | | | | | | Enable full reset for RAS supported configuration on gc v11_0_0. v2: simplify the code. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/vcn: Disable CG/PG for SRIOVJane Jian2022-09-011-0/+5
| | | | | | | | | | | For sriov, CG and MG are controlled from hypervisor side, no need to manage them again in ip init Acked-by: Christian König <[email protected]> Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Sonny Jiang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/admgpu: Skip CG/PG on SOC21 under SRIOV VFYifan Zha2022-09-011-0/+4
| | | | | | | | | | | | | | | [Why] There is no CG(Clock Gating)/PG(Power Gating) requirement on SRIOV VF. For multi VF, VF should not enable any CG/PG features. For one VF, PF will program CG/PG related registers. [How] Do not set any cg/pg flag bit at early init under sriov. Acked-by: Christian König <[email protected]> Signed-off-by: Yifan Zha <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Use RLCG to program GRBM_GFX_CNTL during full access timeYifan Zha2022-09-011-1/+1
| | | | | | | | | | | | | | [Why] KIQ register init requires GRBM_GFX_CNTL to select KIQ. [How] As RLCG accessing registers will save the data of GRBM_GFX_CNTL and restore it. Use RLCG indirect accessing register method to select grbm instead of mmio directly access. Acked-by: Christian König <[email protected]> Signed-off-by: Yifan Zha <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Enable pg/cg flags on GC11_0_3 for VCNSonny Jiang2022-08-291-2/+5
| | | | | | | | | This enable VCN PG, CG, DPG and JPEG PG, CG Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: initialize common sw config for v11_0_3Hawking Zhang2022-08-291-0/+5
| | | | | | | | init cp/pg_flags and extenal_rev_id Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add MGCG perfmon setting for gfx11Likun Gao2022-08-251-0/+15
| | | | | | | | | Enable GFX11 MGCG perfmon setting. V2: set rlc to saft mode before setting. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable NBIO IP v7.7.0 Clock GatingTim Huang2022-08-221-4/+3
| | | | | | | | Enable AMD_CG_SUPPORT_BIF_MGCG and AMD_CG_SUPPORT_BIF_LS support. Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable IH Clock Gating for OSS IP v6.0.1Tim Huang2022-08-161-0/+1
| | | | | | | | Enable AMD_CG_SUPPORT_IH_CG support. Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable ATHUB IP v3.0.1 Clock GatingTim Huang2022-08-161-0/+2
| | | | | | | | Enable AMD_CG_SUPPORT_ATHUB_MGCG and AMD_CG_SUPPORT_ATHUB_LS support. Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable HDP IP v5.2.1 Clock GatingTim Huang2022-08-161-0/+6
| | | | | | | | Enable AMD_CG_SUPPORT_HDP_MGCG and AMD_CG_SUPPORT_HDP_LS support. Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable MMHUB IP v3.0.1 Clock GatingTim Huang2022-08-161-0/+2
| | | | | | | | Enable AMD_CG_SUPPORT_MC_MGCG and AMD_CG_SUPPORT_MC_LS support. Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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