diff options
| author | Hawking Zhang <[email protected]> | 2023-03-23 02:21:49 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2023-03-31 15:18:32 +0000 |
| commit | 9af357bc3e05400eb632f3975986e1eac196f159 (patch) | |
| tree | c92262d206d942e959ecc41b1a71a6ecbcc90fee /drivers/gpu/drm/amd/amdgpu/soc21.c | |
| parent | drm/amd/display/amdgpu_dm: Pass proper parent for backlight device registrati... (diff) | |
| download | kernel-9af357bc3e05400eb632f3975986e1eac196f159.tar.gz kernel-9af357bc3e05400eb632f3975986e1eac196f159.zip | |
drm/amdgpu: Add fatal error handling in nbio v4_3
GPU will stop working once fatal error is detected.
it will inform driver to do reset to recover from
the fatal error.
v2: squash in logic fix (Srinivasan)
v3: squash in logic fix (Dan)
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Candice Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc21.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc21.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 67580761b44d..514bfc705d5a 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -754,6 +754,14 @@ static int soc21_common_late_init(void *handle) sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0)); } + } else { + if (adev->nbio.ras && + adev->nbio.ras_err_event_athub_irq.funcs) + /* don't need to fail gpu late init + * if enabling athub_err_event interrupt failed + * nbio v4_3 only support fatal error hanlding + * just enable the interrupt directly */ + amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); } return 0; @@ -801,8 +809,13 @@ static int soc21_common_hw_fini(void *handle) /* disable the doorbell aperture */ soc21_enable_doorbell_aperture(adev, false); - if (amdgpu_sriov_vf(adev)) + if (amdgpu_sriov_vf(adev)) { xgpu_nv_mailbox_put_irq(adev); + } else { + if (adev->nbio.ras && + adev->nbio.ras_err_event_athub_irq.funcs) + amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); + } return 0; } |