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* Backmerge tag 'v6.7-rc5' into drm-nextDave Airlie2023-12-121-5/+10
|\ | | | | | | | | | | | | | | Linux 6.7-rc5 Alex requested this for some amdkfd work relying on the symbols exports. Signed-off-by: Dave Airlie <[email protected]>
| * drm/amdgpu: Avoid querying DRM MGCG statusLijo Lazar2023-12-061-1/+2
| | | | | | | | | | | | | | | | | | MP0 v13.0.6 SOCs don't support DRM MGCG. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: Add NULL checks for function pointersLijo Lazar2023-12-061-4/+8
| | | | | | | | | | | | | | | | | | Check if function is implemented before making the call. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
| * drm/amdgpu: Use another offset for GC 9.4.3 remapLijo Lazar2023-11-291-0/+5
| | | | | | | | | | | | | | | | | | The legacy region at 0x7F000 maps to valid registers in GC 9.4.3 SOCs. Use 0x1A000 offset instead as MMIO register remap region. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | drm/amdgpu: Use another offset for GC 9.4.3 remapLijo Lazar2023-11-291-0/+5
| | | | | | | | | | | | | | | | | | The legacy region at 0x7F000 maps to valid registers in GC 9.4.3 SOCs. Use 0x1A000 offset instead as MMIO register remap region. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | drm/amdgpu: Read aquavanjaram PCIE register stateLijo Lazar2023-11-291-0/+1
|/ | | | | | | | Add support to read aqua vanjaram PCIE register state Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd: Move AMD_IS_APU check for ASPM into top level functionMario Limonciello2023-10-261-2/+1
| | | | | | | | | There is no need for every ASIC driver to perform the same check. Move the duplicated code into amdgpu_device_should_use_aspm(). Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Use function for IP version checkLijo Lazar2023-09-201-14/+13
| | | | | | | | | Use an inline function for version check. Gives more flexibility to handle any format changes. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Fix refclk reporting for SMU v13.0.6Lijo Lazar2023-09-061-1/+2
| | | | | | | | SMU v13.0.6 SOCs have 100MHz reference clock. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Add RREG64_PCIE_EXT/WREG64_PCIE_EXT functionsCandice Li2023-09-061-0/+2
| | | | | | | | | | Add 64bits register access support on register whose address is greater than 32bits. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Add SMU v13.0.6 default reset methodsLijo Lazar2023-08-301-1/+3
| | | | | | | | | | | For APUs with SMU v13.0.6, mode-2 reset is kept as default and for others mode-1 is the default reset method. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Tested-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Add pci usage to nbio v7.9Asad Kamal2023-08-091-1/+1
| | | | | | | | | | Add implementation to get pcie usage for nbio v7.9. Signed-off-by: Asad Kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Reviewed-by: Shiwu Zhang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Add pci replay count to nbio v7.9Lijo Lazar2023-08-071-1/+1
| | | | | | | | Add implementation to get pcie replay count for nbio v7.9. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Revert "drm/amdgpu: change the reference clock for raven/raven2"Alex Deucher2023-06-091-3/+4
| | | | | | | | | | | | | This reverts commit fbc24293ca16b3b9ef891fe32ccd04735a6f8dc1. This results in inconsistent timing reported via asynchronous GPU queries. Link: https://lists.freedesktop.org/archives/amd-gfx/2023-May/093731.html Cc: [email protected] Cc: [email protected] Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: retire set_vga_state for some ASICLikun Gao2023-06-091-8/+0
| | | | | | | | | | set_vga_state operation only allowed on SI generation ASIC, retire the realted function on those ASIC which did not do anything. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Add FGCG for GFX v9.4.3Lijo Lazar2023-06-091-2/+3
| | | | | | | | It's not fine grain, behaves similar to MGCG. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Add mode-2 reset in SMU v13.0.6Lijo Lazar2023-06-091-0/+9
| | | | | | | | | Modifications to mode-2 reset flow for SMU v13.0.6 ASICs. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Le Ma <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Enable CG for IH v4.4.2Asad kamal2023-06-091-1/+2
| | | | | | | | Enable clock gating on IH v4.4.2 versions. Signed-off-by: Asad kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Enable MGCG on SDMAv4.4.2Lijo Lazar2023-06-091-2/+2
| | | | | | | | | Enable clock gating on SDMAv4.4.2 versions. Leave memory light sleep to default. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add vcn_4_0_3 codec querySonny Jiang2023-06-091-0/+24
| | | | | | | | Add support for vcn_4_0_3 video codec query Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Enable CGCG/LS for GC 9.4.3Lijo Lazar2023-06-091-1/+2
| | | | | | | | | Enable coarse grain clockgating/light sleep for GC v9.4.3. Remove programming that is not meant for GC 9.4.3. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: init gfx_v9_4_3 external_rev_idHawking Zhang2023-06-091-0/+1
| | | | | | | | | it is used for user space driver to identify gfx_v9_4_3 chip Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add helpers to access registers on different AIDsLe Ma2023-06-091-0/+1
| | | | | | | | | | | | SMN address which is larger than 32bit has different indications through bit[34:32] on different AIDs. v2: put smn addressing of different AIDs into asic specific place v3: change to ext_id/ext_offset naming Signed-off-by: Le Ma <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: switch to aqua_vanjaram_doorbell_index_initLe Ma2023-06-091-1/+23
| | | | | | | | New doorbell index assignment is used by aqua_vanjaram. Signed-off-by: Le Ma <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add indirect r/w interface for smn address greater than 32bitsLe Ma2023-06-091-0/+2
| | | | | | | | | | | | | On multiple AIDs platform, bit[34:32] in SMD address is leveraged to access nonAID0 register smn address and new PCI_INDEX_HI register is introduced to access the higher bits. v2: rebase on latest register accessors (Alex) Signed-off-by: Le Ma <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/vcn: enable vcn DPG mode for VCN4_0_3James Zhu2023-06-091-0/+1
| | | | | | | | Enable vcn DPG mode for VCN4_0_3. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/vcn: enable vcn pg for VCN4_0_3James Zhu2023-06-091-0/+1
| | | | | | | | Enable vcn pg for VCN4_0_3. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/vcn: enable vcn cg for VCN4_0_3James Zhu2023-06-091-0/+1
| | | | | | | | Enable vcn cg for VCN4_0_3. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/jpeg: enable jpeg pg for VCN4_0_3James Zhu2023-06-091-1/+2
| | | | | | | | Enable jpeg pg for VCN4_0_3. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/jpeg: enable jpeg cg for VCN4_0_3James Zhu2023-06-091-1/+2
| | | | | | | | Enable jpeg cg for VCN4_0_3. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Enable doorbell selfring after resize FB BARShane Xiao2023-06-091-10/+15
| | | | | | | | | | | | | | | | | | | | | | | | | [Why] The selfring doorbell aperture will change when resize FB BAR successfully during gmc sw init, we should reorder the sequence of enabling doorbell selfring aperture. [How] Move enable_doorbell_selfring_aperture from *_common_hw_init to *_common_late_init. This fixes the potential issue that GPU ring its own doorbell when this device is in translated mode when iommu is on. v2: Remove *_enable_doorbell_aperture functions (Christian) v3: Add comments to note that why we need enable doorbell selfring late (Christian) Signed-off-by: Shane Xiao <[email protected]> Signed-off-by: Aaron Liu <[email protected]> Tested-by: Xiaomeng Hou <[email protected]> Reviewed-by: Christian K�nig <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add xcc index argument to select_sh_se function v2Le Ma2023-04-181-2/+2
| | | | | | | | | | v1: To support multiple XCD case (Le) v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking) Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add xcc index argument to soc15_grbm_selectLe Ma2023-04-181-2/+2
| | | | | | | | | | To support grbm select for multiple XCD case. v2: unify naming style Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add common early init support for GC 9.4.3Hawking Zhang2023-04-141-0/+5
| | | | | | | | init asic funcs and cp/pg flags for GC 9.4.3 Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: change the reference clock for raven/raven2Jesse Zhang2023-04-141-4/+3
| | | | | | | | | | Due to switch to golden tsc register to get clock counter for raven/ raven2. Chang the reference clock from 25MHZ to 100MHZ. Suggested-by: shanshengwang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Jesse Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Retire pcie_gen3_enable functionHawking Zhang2023-03-151-20/+0
| | | | | | | | | Not needed since from vi. drop the function so we don't duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Move to common helper to query soc rev_idHawking Zhang2023-03-151-6/+1
| | | | | | | | | | Replace soc15, nv, soc21 get_rev_id callback with common helper so we don't need to duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Move to common indirect reg access helperHawking Zhang2023-03-151-45/+4
| | | | | | | | | | | Replace soc15, nv, soc21 specific callbacks with common one. so we don't need to duplicate code when introduce new asics. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: fix error checking in amdgpu_read_mm_registers for soc15Alex Deucher2023-03-071-2/+3
| | | | | | | | | Properly skip non-existent registers as well. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2442 Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* amdgpu/nv.c: Corrected typo in the video capabilities resolutionVeerabadhran Gopalakrishnan2022-11-291-12/+12
| | | | | | | | | | | | | Corrected the typo in the 4K resolution parameters. Fixes: b3a24461f9fb15 ("amdgpu/nv.c - Added codec query for Beige Goby") Fixes: 9075096b09e590 ("amdgpu/nv.c - Optimize code for video codec support structure") Fixes: 9ac0edaa0f8323 ("drm/amdgpu: add vcn_4_0_0 video codec query") Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]> Acked-by: Luben Tuikov <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: fix sdma doorbell init ordering on APUsAlex Deucher2022-10-201-0/+21
| | | | | | | | | | | | | | | | | | | | | | Commit 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") uncovered a bug in amdgpu that required a reordering of the driver init sequence to avoid accessing a special register on the GPU before it was properly set up leading to an PCI AER error. This reordering uncovered a different hw programming ordering dependency in some APUs where the SDMA doorbells need to be programmed before the GFX doorbells. To fix this, move the SDMA doorbell programming back into the soc15 common code, but use the actual doorbell range values directly rather than the values stored in the ring structure since those will not be initialized at this point. This is a partial revert, but with the doorbell assignment fixed so the proper doorbell index is set before it's used. Fixes: e3163bc8ffdfdb ("drm/amdgpu: move nbio sdma_doorbell_range() into sdma code for vega") Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] Cc: [email protected]
* drm/amdgpu: move nbio sdma_doorbell_range() into sdma code for vegaAlex Deucher2022-09-141-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This mirrors what we do for other asics and this way we are sure the sdma doorbell range is properly initialized. There is a comment about the way doorbells on gfx9 work that requires that they are initialized for other IPs before GFX is initialized. However, the statement says that it applies to multimedia as well, but the VCN code currently initializes doorbells after GFX and there are no known issues there. In my testing at least I don't see any problems on SDMA. This is a prerequisite for fixing the Unsupported Request error reported through AER during driver load. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216373 The error was unnoticed before and got visible because of the commit referenced below. This doesn't fix anything in the commit below, rather fixes the issue in amdgpu exposed by the commit. The reference is only to associate this commit with below one so that both go together. Fixes: 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") Acked-by: Christian König <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* drm/amdgpu: move nbio ih_doorbell_range() into ih code for vegaAlex Deucher2022-09-141-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This mirrors what we do for other asics and this way we are sure the ih doorbell range is properly initialized. There is a comment about the way doorbells on gfx9 work that requires that they are initialized for other IPs before GFX is initialized. In this case IH is initialized before GFX, so there should be no issue. This is a prerequisite for fixing the Unsupported Request error reported through AER during driver load. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216373 The error was unnoticed before and got visible because of the commit referenced below. This doesn't fix anything in the commit below, rather fixes the issue in amdgpu exposed by the commit. The reference is only to associate this commit with below one so that both go together. Fixes: 8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") Acked-by: Christian König <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* drm/amdgpu/discovery: move all table parsing into amdgpu_discovery.cAlex Deucher2022-04-281-13/+0
| | | | | | | | This data has no dependencies, so encapsulate it all within amdgpu_discovery.c. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: expand cg_flags from u32 to u64Evan Quan2022-04-081-1/+1
| | | | | | | | | With this, we can support more CG flags. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd: fix gfx hang on renoir in IGT reload testTianci.Yin2022-03-151-0/+4
| | | | | | | | | | | | | | [why] CP hangs in igt reloading test on renoir, more precisely, hangs on the second time insmod. [how] mode2 reset can make it recover, and mode2 reset only effects gfx core, dcn and the screen will not be impacted. Acked-by: Alex Deucher <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: centrally calls the .ras_fini function of all ras blocksyipechai2022-03-021-3/+0
| | | | | | | | centrally calls the .ras_fini function of all ras blocks. Signed-off-by: yipechai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Optimize xxx_ras_fini function of each ras blockyipechai2022-03-021-1/+1
| | | | | | | | | | | | 1. Move the variables of ras block instance members from specific xxx_ras_fini to general ras_fini call. 2. Function calls inside the modules only use parameters passed from xxx_ras_fini instead of ras block instance members. Signed-off-by: yipechai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Modify .ras_fini function pointer parameteryipechai2022-03-021-1/+1
| | | | | | | | | | Modify .ras_fini function pointer parameter so that we can remove redundant intermediate calls in some ras blocks. Signed-off-by: yipechai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Backmerge tag 'v5.17-rc6' into drm-nextDave Airlie2022-02-281-2/+2
|\ | | | | | | | | | | This backmerges v5.17-rc6 so I can merge some amdgpu and some tegra changes on top. Signed-off-by: Dave Airlie <[email protected]>
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