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authorLe Ma <[email protected]>2022-04-02 11:39:59 +0000
committerAlex Deucher <[email protected]>2023-06-09 13:45:29 +0000
commit0c552ed38780f24b7ac235c3d10c6c94686ecfdf (patch)
tree5c8bb30c898f2c3db5dc639888226b9069090fa8 /drivers/gpu/drm/amd/amdgpu/soc15.c
parentdrm/amdkfd: EOP Removal - Handle size 0 correctly (diff)
downloadkernel-0c552ed38780f24b7ac235c3d10c6c94686ecfdf.tar.gz
kernel-0c552ed38780f24b7ac235c3d10c6c94686ecfdf.zip
drm/amdgpu: add indirect r/w interface for smn address greater than 32bits
On multiple AIDs platform, bit[34:32] in SMD address is leveraged to access nonAID0 register smn address and new PCI_INDEX_HI register is introduced to access the higher bits. v2: rebase on latest register accessors (Alex) Signed-off-by: Le Ma <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/soc15.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index b7e8af56df84..b9bcb12bff91 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -866,6 +866,8 @@ static int soc15_common_early_init(void *handle)
adev->smc_wreg = NULL;
adev->pcie_rreg = &amdgpu_device_indirect_rreg;
adev->pcie_wreg = &amdgpu_device_indirect_wreg;
+ adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext;
+ adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext;
adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;