aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
Commit message (Collapse)AuthorAgeFilesLines
* drm/amdgpu: Do not program AGP BAR regs under SRIOV in gfxhub_v1_0.cVictor Lu2025-03-051-5/+5
| | | | | | | | | SRIOV VF does not have write access to AGP BAR regs. Skip the writes to avoid a dmesg warning. Signed-off-by: Victor Lu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Retire query_utcl2_poison_status callbackHawking Zhang2024-08-231-18/+0
| | | | | | | | | Driver switches to interrupt source id to identify utcl2 poison event. polling interface is not needed. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add utcl2 poison query for gfxhubTao Zhou2024-03-201-0/+17
| | | | | | | | | | Implement it for gfxhub 1.0 and 1.2. v2: input logical xcc id for poison query interface. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: apply the RV2 system aperture fix to RN/CZN as wellAlex Deucher2024-01-051-1/+3
| | | | | | | | | These chips needs the same fix. This was previously not seen on then since the AGP aperture expanded the system aperture, but this showed up again when AGP was disabled. Reviewed-and-tested-by: Jiadong Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add hub->ctx_distance in setup_vmid_configYifan Zhang2023-10-091-1/+1
| | | | | | | | | | | | add hub->ctx_distance when read CONTEXT1_CNTL, align w/ write back operation. v2: fix coding style errors reported by checkpatch.pl (Christian) Signed-off-by: Yifan Zhang <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Fix warnings in gfxhub_ v1_0, v1_2.cSrinivasan Shanmugam2023-07-101-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the below checkpatch warnings: WARNING: Block comments should align the * on each line + /* + * Raven2 has a HW issue that it is unable to use the WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + unsigned num_level, block_size; WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + unsigned i; WARNING: Missing a blank line after declarations + u32 tmp; + tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); WARNING: Block comments should align the * on each line + /* + * Raven2 has a HW issue that it is unable to use the WARNING: Prefer 'unsigned int' to bare use of 'unsigned' + unsigned num_level, block_size; Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: introduce vmhub definition for multi-partition cases (v3)Hawking Zhang2023-06-091-5/+5
| | | | | | | | | | | | | | | | | | | v1: Each partition has its own gfxhub or mmhub. adjust the num of MAX_VMHUBS and the GFXHUB/MMHUB layout (Le) v2: re-design the AMDGPU_GFXHUB/AMDGPU_MMHUB layout (Le) v3: apply the gfxhub/mmhub layout to new IPs (Hawking) v4: fix up gmc11 (Alex) v5: rebase (Alex) Signed-off-by: Le Ma <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: rename vram_scratch into mem_scratchChristian König2023-01-031-1/+1
| | | | | | | | | | | | | Rename vram_scratch into mem_scratch and allow allocating it into GTT as well. The only problem with that is that we won't have a default page for the system aperture any more. Signed-off-by: Christian König <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: don't override default ECO_BITs settingHawking Zhang2021-12-141-1/+0
| | | | | | | | | Leave this bit as hardware default setting Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* drm/amd/amdgpu: Avoid writing GMC registers under sriov in gmc9YuBiao Wang2021-11-051-0/+4
| | | | | | | | | | | | | [Why] For Vega10, disabling gart of gfxhub could mess up KIQ and PSP under sriov mode, and lead to DMAR on host side. [How] Skip writing GMC registers under sriov. Signed-off-by: YuBiao Wang <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: remove sriov vf gfxhub fb location programmingZhigang Luo2021-06-081-12/+0
| | | | | | | | | | host driver programmed the gfxhub fb location for vf, no need to program in guest side. Signed-off-by: Zhigang Luo <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-By : Shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Enable retry faults unconditionally on AldebaranFelix Kuehling2021-04-211-2/+6
| | | | | | | | | | This is needed to allow per-process XNACK mode selection in the SQ when booting with XNACK off by default. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Philip Yang <[email protected]> Tested-by: Alex Sierra <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Revert "drm/amdgpu: workaround the TMR MC address issue (v2)"Oak Zeng2021-04-211-15/+6
| | | | | | | | | | | This reverts commit 2f055097daef498da57552f422f49de50a1573e6. 2f055097daef498da57552f422f49de50a1573e6 was a driver workaround when PSP firmware was not ready. Now the PSP fw is ready so we revert this driver workaround. Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Calling address translation functions to simplify codesOak Zeng2021-04-151-2/+1
| | | | | | | | | | Use amdgpu_gmc_vram_pa and amdgpu_gmc_vram_cpu_pa to simplify codes. No logic change. Signed-off-by: Oak Zeng <[email protected]> Signed-off-by: Harish Kasiviswanathan <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: workaround the TMR MC address issue (v2)Oak Zeng2021-03-241-6/+15
| | | | | | | | | | | | | | | | | | | With the 2-level gart page table, vram is squeezed into gart aperture and FB aperture is disabled. Therefore all VRAM virtual addresses are in the GART aperture. However currently PSP requires TMR addresses in FB aperture. So we need some design change at PSP FW level to support this 2-level gart table driver change. Right now this PSP FW support doesn't exist. To workaround this issue temporarily, FB aperture is added back and the gart aperture address is converted back to FB aperture for this PSP TMR address. Will revert it after we get a fix from PSP FW. v2: squash in tmr fix for other asics (Kevin) Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: HW setup of 2-level vmid0 page tableOak Zeng2021-03-241-9/+41
| | | | | | | | | | | | | | | Set up HW for 2-level vmid0 page table: 1. Set up PAGE_TABLE_START/END registers. Currently only plan to do 2-level page table for ALDEBARAN, so only gfxhub1.0 and mmhub1.7 is changed. 2. Set page table base register. For 2-level page table, the page table base should point to PDB0. 3. Disable AGP and FB aperture as they are not used. Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Christian Konig <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Use different gart table parameters for 2-level gart tableOak Zeng2021-03-241-1/+4
| | | | | | | | | | | | | If use gart for FB translation, we will squeeze vram into sysvm aperture. This requires 2 level gart table. Add page table depth and page table block size parameters to gmc. This is prepare work to 2-level gart table construction Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Christian Konig <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Use physical translation mode to access page tableOak Zeng2021-03-241-2/+7
| | | | | | | | | | | | On A+A platform, CPU write page directory and page table in cached mode. So it is necessary for page table walker to snoop CPU cache. This setting is necessary for page walker to snoop page directory and page table data out of CPU cache. Signed-off-by: Oak Zeng <[email protected]> Acked-by: Christian Konig <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: make gfxhub_v1_0 callback functions to be staticHawking Zhang2020-11-171-8/+9
| | | | | | | | | Those functions should be invoked through gfxhub.funcs pointer. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: remove gfxhub_v1_1_funcs setKevin Wang2020-10-161-0/+2
| | | | | | | | | remove duplicate gfxhub v1.1 function set. put function of gfxhub_v1_1_get_xgmi_info to gfxhub v1_0 function set. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: use function pointer for gfxhub functionsOak Zeng2020-09-301-0/+10
| | | | | | | | | gfxhub functions are now called from function pointers, instead of from asic-specific functions. Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: store noretry parameter per driver instanceAlex Deucher2020-09-251-1/+1
| | | | | | | | | This will allow us to have different defaults per asic in a future patch. Reviewed-by: Christian König <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: use register distance member instead of hardcode in gfxhub v1Huang Rui2020-07-081-16/+25
| | | | | | | | | | This patch updates to use register distance member instead of hardcode in gfxhub v1. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add register distance members into vmhub structureHuang Rui2020-07-081-0/+7
| | | | | | | | | | | This patch is to abstract register distances between two continuous context domains and invalidation engines. In different ip headers, these distances may be differences. Signed-off-by: Huang Rui <[email protected]> Tested-by: AnZhong Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add apu flags (v2)Alex Deucher2020-05-221-1/+1
| | | | | | | | | | | | | Add some APU flags to simplify handling of different APU variants. It's easier to understand the special cases if we use names flags rather than checking device ids and silicon revisions. v2: rebase on latest code Acked-by: Evan Quan <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/amdgpu: L1 Policy(2/5) - removed GC GRBM violations from gfxhubZhigang Luo2020-01-071-32/+39
| | | | | | | Signed-off-by: Zhigang Luo <[email protected]> Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: remove FB location config for sriovFrank.Min2019-12-231-1/+1
| | | | | | | | | FB location is already programmed by HV driver for arcutus so remove this part Signed-off-by: Frank.Min <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: initialize vm_inv_eng0_sem for gfxhub and mmhubchangzhu2019-11-221-0/+2
| | | | | | | | | | | | | SW must acquire/release one of the vm_invalidate_eng*_sem around the invalidation req/ack. Through this way,it can avoid losing invalidate acknowledge state across power-gating off cycle. To use vm_invalidate_eng*_sem, it needs to initialize vm_invalidate_eng*_sem firstly. Signed-off-by: changzhu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* drm/amdgpu: Disable retry faults in VMID0Felix Kuehling2019-09-161-0/+2
| | | | | | | | | There is no point retrying page faults in VMID0. Those faults are always fatal. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-and-Tested-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: rename AMDGPU_GFXHUB/MMHUB macro with hub numberLe Ma2019-07-181-1/+1
| | | | | | | | The number of GFXHUB/MMHUB may be expanded in later ASICs. Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdkfd: Consistently apply noretry settingFelix Kuehling2019-07-161-1/+2
| | | | | | | | | | | | | | Apply the same setting to SH_MEM_CONFIG and VM_CONTEXT1_CNTL. This makes the noretry param no longer KFD-specific. On GFX10 I'm not changing SH_MEM_CONFIG in this commit because GFX10 has different retry behaviour in the SQ and I don't have a way to test it at the moment. Suggested-by: Christian König <[email protected]> CC: Philip Yang <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by : Shaoyun.liu < [email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/sriov: Correct some register program methodEmily Deng2019-05-311-4/+4
| | | | | | | | For the VF, some registers only could be programmed with RLC. Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Trigger Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: RLC to program regs for Vega10 SR-IOVTrigger Huang2019-05-241-10/+10
| | | | | | | | | Under Vega10 SR-IOV, with new RLC's new feature, VF should call RLC to program some registers if supported Signed-off-by: Trigger Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: re-enable retry faultsChristian König2019-03-211-1/+1
| | | | | | | | | Now that we have re-reoute faults to the other IH ring we can enable retries again. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0Yong Zhao2019-03-191-1/+1
| | | | | | | | | | | | | | | | This is recommended by HW designers. Previously when it was set to 1, the PDE walk error in VM fault will be treated as PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT. As a result, the retry control in VM_CONTEXT*_CNTL will change accordingly. The above behavior is kind of abnormal. Furthermore, the PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs and it never made it way to production. Therefore, we should set it to 0. Signed-off-by: Yong Zhao <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Merge branch 'drm-next-4.21' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2018-11-191-7/+12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next New features for 4.21: amdgpu: - Support for SDMA paging queue on vega - Put compute EOP buffers into vram for better performance - Share more code with amdkfd - Support for scanout with DCC on gfx9 - Initial kerneldoc for DC - Updated SMU firmware support for gfx8 chips - Rework CSA handling for eventual support for preemption - XGMI PSP support - Clean up RLC handling - Enable GPU reset by default on VI, SOC15 dGPUs - Ring and IB test cleanups amdkfd: - Share more code with amdgpu ttm: - Move global init out of the drivers scheduler: - Track if schedulers are ready for work - Timeout/fault handling changes to facilitate GPU recovery Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
| * drm/amdgpu: Expose *_setup_vm_pt_regs for kfd to useYong Zhao2018-11-051-7/+12
| | | | | | | | | | | | | | | | | | | | | | kfd has the same need to set the VM page table base register, so expose them for kfd to use for better maintainability. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* | drm/amdgpu: set system aperture to cover whole FB regionshaoyunl2018-11-121-3/+3
|/ | | | | | | | | | In XGMI configuration, the FB region covers vram region from peer device, adjust system aperture to cover all of them Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: shaoyunl <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: fix the page fault of raven2Huang Rui2018-09-271-1/+2
| | | | | | | | | | | | | | | | While the apg_end address is 0xffffffff, if add 1 with it, the value will be overflow and roll back to 0. So when 0 is written to mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, the system aperture is actually disabled. And so any access to vram will trigger a page fault. Raven2's HW issue only need increase the vram end address, and needn't do it on the agp. Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: fix the VM fault while write at the top of the invisible vramHuang Rui2018-09-141-2/+13
| | | | | | | | | | | Raven2 has a HW issue that it is unable to use the vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the workaround that increase system aperture high address to get rid of the VM fault and hardware hang. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: enable AGP aperture for GMC9 v2Christian König2018-09-111-5/+5
| | | | | | | | | | Enable the old AGP aperture to avoid GART mappings. v2: don't enable it for SRIOV Signed-off-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add amdgpu_gmc_pd_addr helperChristian König2018-08-271-6/+1
| | | | | | | | | | Add a helper to get the root PD address and remove the workarounds from the GMC9 code for that. Signed-off-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: remove gart.table_addrChristian König2018-08-271-4/+3
| | | | | | | | We can easily figure out the address on the fly. Signed-off-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: use the TTM dummy page instead of allocating oneChristian König2018-02-271-2/+2
| | | | | | | | | We have a global dummy page in TTM, use that one instead of allocating a new one. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: move struct amdgpu_mc into amdgpu_gmc.hChristian König2018-02-191-12/+12
| | | | | | | | And rename it to amdgpu_gmc as well. Signed-off-by: Christian König <[email protected]> Reviewed-by: Samuel Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: implement 2+1 PD support for Raven v3Christian König2017-12-181-13/+29
| | | | | | | | | | | | Instead of falling back to 2 level and very limited address space use 2+1 PD support and 128TB + 512GB of virtual address space. v2: cleanup defines, rebase on top of level enum v3: fix inverted check in hardware setup Signed-off-by: Christian König <[email protected]> Reviewed-and-Tested-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/admgpu: Reduce the usage of soc15ip.hShaoyun Liu2017-12-081-1/+0
| | | | | | | | Remove the header where it's not used. Acked-by: Christian Konig <[email protected]> Signed-off-by: Shaoyun Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/include:cleanup vega10 header files.Feifei Xu2017-12-061-2/+2
| | | | | | | | Remove asic_reg/vega10 folder. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amd/include:cleanup vega10 gc header files.Feifei Xu2017-12-061-3/+3
| | | | | | | | | | Cleanup asic_reg/vega10/GC folder. Signed-off-by: Feifei Xu <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu:halt when vm faultMonk Liu2017-09-261-0/+6
| | | | | | | | only with this way we can debug the VMC page fault issue Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
generated by cgit (git 2.51.2) at 2025-11-30 20:31:42 +0000