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* drm/amdgpu: add mc wptr addr support for mesJack Xiao2022-06-281-0/+1
| | | | | | | | | MES requires mc wptr address for usermode queues. Export bo gart address for mc wptr address. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add mes queue id mask v2Jack Xiao2022-05-041-0/+1
| | | | | | | | | | | Add MES queue id mask. v2: move queue id mask to amdgpu_mes_ctx.h Signed-off-by: Jack Xiao <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/gfx10: associate mes queue id with fence v2Jack Xiao2022-05-041-0/+2
| | | | | | | | | | | | Associate mes queue id with fence, so that EOP trap handler can look up which queue has issued the fence. v2: move mes queue flag to amdgpu_mes_ctx.h Signed-off-by: Jack Xiao <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add the per-context meta data v3Jack Xiao2022-05-041-0/+118
The per-context meta data is a per-context data structure associated with a mes-managed hardware ring, which includes MCBP CSA, ring buffer and etc. v2: fix typo v3: a. use structure instead of typedef b. move amdgpu_mes_ctx_get_offs_* to amdgpu_ring.h c. use __aligned to make alignement Signed-off-by: Jack Xiao <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>