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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
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* drm/amdgpu: Clear overflow for SRIOVEmily Deng2025-04-211-0/+1
| | | | | | | | | For VF, it doesn't have the permission to clear overflow, clear the bit by reset. Signed-off-by: Emily Deng <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Fix missing drain retry fault the last entryEmily Deng2025-03-071-0/+3
| | | | | | | | | | | | | While the entry get in svm_range_unmap_from_cpu is the last entry, and the entry is page fault, it also need to be dropped. So for equal case, it also need to be dropped. v2: Only modify the svm_range_restore_pages. Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Xiaogang Chen<[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Show warning message if IH ring overflowPhilip Yang2024-12-181-0/+1
| | | | | | | | | | | | | | | If IH primary ring and KFD ih fifo overflows, we may miss CP, SDMA interrupts and cause application soft hang. Show warning message with ring name if overflow happens. Add function to get ih ring name to avoid duplicating it. To keep warning message consistent between GPU generations, change all *_ih.c except ASICs older than Vega which has only one ih ring. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Increase IH soft ring size for GFX v9.4.3 dGPUPhilip Yang2023-09-261-1/+1
| | | | | | | | | | | | | | On GFX v9.4.3 dGPU, applications have random timeout failure when XNACK on, dmesg log has "amdgpu: IH soft ring buffer overflow 0x900, 0x900", because dGPU mode has 272 cam entries. After increasing IH soft ring to 512 entries, no more IH soft ring overflow message and application passed. Fixes: bf80d34b6c58 ("drm/amdgpu: Increase soft IH ring size") Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Increase soft IH ring sizePhilip Yang2023-07-121-2/+5
| | | | | | | | | | | | | | | | | | | | | Retry faults are delegated to soft IH ring and then processed by deferred worker. Current soft IH ring size PAGE_SIZE can store 128 entries, which may overflow and drop retry faults, causes HW stucks because the retry fault is not recovered. Increase soft IH ring size to 8KB, enough to store 256 CAM entries because we clear the CAM entry after handling the retry fault from soft ring. Define macro IH_RING_SIZE and IH_SW_RING_SIZE to remove duplicate constant. Show warning message if soft IH ring overflows with CAM enabled because this should not happen. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: handle IH ring1 overflowPhilip Yang2021-12-011-2/+14
| | | | | | | | | | | | | | | | | | | | | IH ring1 is used to process GPU retry fault, overflow is enabled to drain retry fault because we want receive other interrupts while handling retry fault to recover range. There is no overflow flag set when wptr pass rptr. Use timestamp of rptr and wptr to handle overflow and drain retry fault. If fault timestamp goes backward, the fault is filtered and should not be processed. Drain fault is finished if processed_timestamp is equal to or larger than checkpoint timestamp. Add amdgpu_ih_functions interface decode_iv_ts for different chips to get timestamp from IV entry with different iv size and timestamp offset. amdgpu_ih_decode_iv_ts_helper is used for vega10, vega20, navi10. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: nuke the ih reentrant lockChristian König2021-03-241-1/+0
| | | | | | | | | | Interrupts on are non-reentrant on linux. This is just an ancient leftover from radeon where irq processing was kicked of from different places. Signed-off-by: Christian König <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add ih waiter on process until checkpointJonathan Kim2021-03-241-0/+5
| | | | | | | | | | | | | Add IH function to allow caller to wait until ring entries are processed until the checkpoint write pointer. This will be primarily used by HMM to drain pending page fault interrupts before memory unmap to prevent HMM from handling stale interrupts. Suggested-by: Christian König <[email protected]> Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add a helper function to decode ivHawking Zhang2020-12-231-1/+3
| | | | | | | | | | | | since from soc15, all the chips share the same iv format. create a common helper to decode iv Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add amdgpu_ih_regs structureHawking Zhang2020-12-231-0/+13
| | | | | | | | | | | | amdgpu_ih_regs holds all the registers for an ih ring Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add infrastructure for soft IH ringChristian König2020-11-241-0/+2
| | | | | | | | | | | Add a soft IH ring implementation similar to the hardware IH1/2. This can be used if the hardware delegation of interrupts to IH1/2 doesn't work for some reason. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: limit the number of IVs processed at onceChristian König2019-03-191-0/+3
| | | | | | | | | Only process a maximum of 32 IVs before writing back the RPTR. This improves hw handling when we get close to an overflow in the ring buffer. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: cleanup amdgpu_ih_process a bit moreChristian König2019-02-131-3/+1
| | | | | | | | Remove the callback and call the dispatcher directly. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: simplify IH programmingChristian König2019-01-141-9/+14
| | | | | | | | Calculate all the addresses and pointers in amdgpu_ih.c Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add IH ring to ih_get_wptr/ih_set_rptr v2Christian König2019-01-141-6/+7
| | | | | | | | | | Let's start to support multiple rings. v2: decode IV is needed as well Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: move IV prescreening into the GMC codeChristian König2018-12-071-2/+0
| | | | | | | | | | The GMC/VM subsystem is causing the faults, so move the handling here as well. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: move more defines into amdgpu_irq.hChristian König2018-09-271-21/+1
| | | | | | | | Everything that isn't related to the IH ring. Signed-off-by: Christian König <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: move more interrupt processing into amdgpu_irq.cChristian König2018-09-271-1/+3
| | | | | | | | Add a callback to amdgpu_ih_process to remove most of the IV logic. Signed-off-by: Christian König <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: cleanup amdgpu_ih.cChristian König2018-09-271-4/+4
| | | | | | | | Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings. Signed-off-by: Christian König <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Move fault hash table to amdgpu vmOak Zeng2018-09-121-11/+0
| | | | | | | | | | | | | In stead of share one fault hash table per device, make it per vm. This can avoid inter-process lock issue when fault hash table is full. Change-Id: I5d1281b7c41eddc8e26113e010516557588d3708 Signed-off-by: Oak Zeng <[email protected]> Suggested-by: Christian Konig <[email protected]> Suggested-by: Felix Kuehling <[email protected]> Reviewed-by: Christian Konig <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: move ih definitions into amdgpu_ih headerHuang Rui2018-08-271-0/+15
| | | | | | | | Demangle amdgpu.h Signed-off-by: Huang Rui <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Move IH clientid defs to separate fileOak Zeng2018-03-141-41/+2
| | | | | | | | | | This is preparation for sharing client ID definitions between amdgpu and amdkfd Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: rename pas_id to pasidChristian König2018-02-191-1/+1
| | | | | | | | | sed -i "s/pas_id/pasid/g" drivers/gpu/drm/amd/amdgpu/*.c sed -i "s/pas_id/pasid/g" drivers/gpu/drm/amd/amdgpu/*.h Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: rename vm_id to vmidChristian König2017-12-271-2/+2
| | | | | | | | | sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Track pending retry faults in IH and VM (v2)Felix Kuehling2017-09-261-0/+12
| | | | | | | | | | | | | | | | | | | | | | IH tracks pending retry faults in a hash table for fast lookup in interrupt context. Each VM has a short FIFO of pending VM faults for processing in a bottom half. The IH prescreening stage adds retry faults and filters out repeated retry interrupts to minimize the impact of interrupt storms. It's the VM's responsibility remove pending faults once they are handled. For now this is only done when the VM is destroyed. v2: - Made the hash table smaller and the FIFO longer. I never want the FIFO to fill up, because that would make prescreen take longer. 128 pending page faults should be enough to keep migrations busy. Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Christian König <[email protected]> (v1) Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add vcn ip block functions (v2)Leo Liu2017-05-241-1/+2
| | | | | | | | | | | Fill in the core VCN 1.0 setup functionality. v2: squash in fixup (Alex) Signed-off-by: Leo Liu <[email protected]> Acked-by: Chunming Zhou <[email protected]> Acked-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: update IH IV ring entry for soc-15Alex Deucher2017-03-301-1/+4
| | | | | | | Reflect the new format on soc-15 asics. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add clinetid definition for vega10ken2017-03-301-2/+40
| | | | | | Signed-off-by: ken <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu/ih: store the full context idAlex Deucher2017-03-301-1/+3
| | | | | | | | | | | | The contextID field (formerly known as src_data) of the IH vector stores client specific information about an interrupt. It was expanded from 32 bits to 128 on newer asics. Expand the src_id field to handle this. Reviewed-by: Harry Wentland <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: switch ih handling to two levels (v3)Alex Deucher2017-03-301-0/+6
| | | | | | | | | | | | | | Newer asics have a two levels of irq ids now: client id - the IP src id - the interrupt src within the IP v2: integrated Christian's comments. v3: fix rebase fail in SI and CIK Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Ken Wang <[email protected]> Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: Implement irq interfaces for CGSAlex Deucher2015-08-171-0/+1
| | | | | | | | This implements the irq src registrar. Reviewed-by: Jammy Zhou <[email protected]> Signed-off-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* drm/amdgpu: add core driver (v4)Alex Deucher2015-06-041-0/+62
This adds the non-asic specific core driver code. v2: remove extra kconfig option v3: implement minor fixes from Fengguang Wu v4: fix cast in amdgpu_ucode.c Acked-by: Christian König <[email protected]> Acked-by: Jammy Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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