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* clk: imx95-blk-ctl: Save/restore registers when RPM routines are calledLaurentiu Palcu2025-09-121-12/+21
| | | | | | | | | | | | | | When runtime PM is used for clock providers that are part of a power domain, the power domain supply is cut off during runtime suspend. This causes all BLK CTL registers belonging to that power domain to reset. To prevent this, save the state of the registers before entering suspend and restore them on resume. Additionally, disable the APB clock during suspend to minimize power consumption. Signed-off-by: Laurentiu Palcu <[email protected]> Reviewed-by: Frank Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* clk: imx95-blk-ctl: Save platform data in imx95_blk_ctl structureLaurentiu Palcu2025-09-121-23/+13
| | | | | | | | | | | | | Add a platform data (pdata) member to struct imx95_blk_ctl to store the result of of_device_get_match_data() during probe to avoid redundant calls in suspend and resume functions. Signed-off-by: Laurentiu Palcu <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Daniel Baluta <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* Merge branch 'clk-pm' into clk-nextStephen Boyd2025-07-292-2/+0
|\ | | | | | | | | | | | | | | | | | | | | | | * clk-pm: clk: qcom: Remove redundant pm_runtime_mark_last_busy() calls clk: imx: Remove redundant pm_runtime_mark_last_busy() calls Documentation: PM: *_autosuspend() functions update last busy time PM: runtime: Mark last busy stamp in pm_request_autosuspend() PM: runtime: Mark last busy stamp in pm_runtime_autosuspend() PM: runtime: Mark last busy stamp in pm_runtime_put_sync_autosuspend() PM: runtime: Mark last busy stamp in pm_runtime_put_autosuspend() PM: runtime: Document return values of suspend-related API functions
| * clk: imx: Remove redundant pm_runtime_mark_last_busy() callsSakari Ailus2025-07-242-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | pm_runtime_put_autosuspend(), pm_runtime_put_sync_autosuspend(), pm_runtime_autosuspend() and pm_request_autosuspend() now include a call to pm_runtime_mark_last_busy(). Remove the now-reduntant explicit call to pm_runtime_mark_last_busy(). Signed-off-by: Sakari Ailus <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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*-. \ Merge branches 'clk-rockchip', 'clk-thead', 'clk-microchip', 'clk-imx' and ↵Stephen Boyd2025-07-291-21/+74
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-qcom' into clk-next * clk-rockchip: clk: rockchip: rk3568: Add PLL rate for 132MHz * clk-thead: clk: thead: th1520-ap: Describe mux clocks with clk_mux clk: thead: th1520-ap: Correctly refer the parent of osc_12m clk: thead: Mark essential bus clocks as CLK_IGNORE_UNUSED * clk-microchip: clk: at91: sam9x7: update pll clk ranges * clk-imx: MAINTAINERS: Update i.MX Clock Entry clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR clk: imx95-blk-ctl: Rename lvds and displaymix csr blk clk: imx95-blk-ctl: Fix synchronous abort dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data * clk-qcom: (65 commits) dt-bindings: clock: qcom,sm4450-dispcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom,sm4450-camcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom,mmcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom,sm8150-camcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom: Remove double colon from description clk: qcom: Add Video Clock controller (VIDEOCC) driver for Milos dt-bindings: clock: qcom: document the Milos Video Clock Controller clk: qcom: Add Graphics Clock controller (GPUCC) driver for Milos dt-bindings: clock: qcom: document the Milos GPU Clock Controller clk: qcom: Add Display Clock controller (DISPCC) driver for Milos dt-bindings: clock: qcom: document the Milos Display Clock Controller clk: qcom: Add Camera Clock controller (CAMCC) driver for Milos dt-bindings: clock: qcom: document the Milos Camera Clock Controller clk: qcom: Add Global Clock controller (GCC) driver for Milos dt-bindings: clock: qcom: document the Milos Global Clock Controller clk: qcom: common: Add support to register rcg dfs in qcom_cc_really_probe clk: qcom: gcc-x1e80100: Add missing video resets dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets clk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100 clk: qcom: videocc-sm8550: Allow building without SM8550/SM8560 GCC ...
| | * clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSRPeng Fan2025-07-211-1/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX94 BLK CTL LVDS CSR's LVDS_PHY_CLOCK_CONTRL register controls the clock gating logic of LVDS units. Display CSR's DISPLAY_ENGINES_CLOCK_CONTROL register controls the selection of the clock feeding the display engine. Add clock gate support for the two CSRs. Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
| | * clk: imx95-blk-ctl: Rename lvds and displaymix csr blkSandor Yu2025-07-211-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename i.MX95 lvds and displaymix csr blk drvdata in order to add support for i.MX943. Signed-off-by: Sandor Yu <[email protected]> Signed-off-by: Laurentiu Palcu <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
| | * clk: imx95-blk-ctl: Fix synchronous abortLaurentiu Palcu2025-07-211-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When enabling runtime PM for clock suppliers that also belong to a power domain, the following crash is thrown: error: synchronous external abort: 0000000096000010 [#1] PREEMPT SMP Workqueue: events_unbound deferred_probe_work_func pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : clk_mux_get_parent+0x60/0x90 lr : clk_core_reparent_orphans_nolock+0x58/0xd8 Call trace: clk_mux_get_parent+0x60/0x90 clk_core_reparent_orphans_nolock+0x58/0xd8 of_clk_add_hw_provider.part.0+0x90/0x100 of_clk_add_hw_provider+0x1c/0x38 imx95_bc_probe+0x2e0/0x3f0 platform_probe+0x70/0xd8 Enabling runtime PM without explicitly resuming the device caused the power domain cut off after clk_register() is called. As a result, a crash happens when the clock hardware provider is added and attempts to access the BLK_CTL register. Fix this by using devm_pm_runtime_enable() instead of pm_runtime_enable() and getting rid of the pm_runtime_disable() in the cleanup path. Fixes: 5224b189462f ("clk: imx: add i.MX95 BLK CTL clk driver") Reviewed-by: Frank Li <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Laurentiu Palcu <[email protected]> Signed-off-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
| | * clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_dataXiaolei Wang2025-07-211-4/+8
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When num_parents is 4, __clk_register() occurs an out-of-bounds when accessing parent_names member. Use ARRAY_SIZE() instead of hardcode number here. BUG: KASAN: global-out-of-bounds in __clk_register+0x1844/0x20d8 Read of size 8 at addr ffff800086988e78 by task kworker/u24:3/59 Hardware name: NXP i.MX95 19X19 board (DT) Workqueue: events_unbound deferred_probe_work_func Call trace: dump_backtrace+0x94/0xec show_stack+0x18/0x24 dump_stack_lvl+0x8c/0xcc print_report+0x398/0x5fc kasan_report+0xd4/0x114 __asan_report_load8_noabort+0x20/0x2c __clk_register+0x1844/0x20d8 clk_hw_register+0x44/0x110 __clk_hw_register_mux+0x284/0x3a8 imx95_bc_probe+0x4f4/0xa70 Fixes: 5224b189462f ("clk: imx: add i.MX95 BLK CTL clk driver") Cc: [email protected] Reviewed-by: Frank Li <[email protected]> Signed-off-by: Xiaolei Wang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
* | clk: Fix typosBjorn Helgaas2025-07-276-6/+6
| | | | | | | | | | | | | | | | | | Fix typos, mostly in comments except CLKGATE_SEPERATED_* (definition and uses updated). Signed-off-by: Bjorn Helgaas <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
* | clk: imx: scu: convert from round_rate() to determine_rate()Brian Masney2025-07-241-27/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. This driver also implements both the determine_rate() and round_rate() clk ops, and the round_rate() clk ops is deprecated. When both are defined, clk_core_determine_round_nolock() from the clk core will only use the determine_rate() clk ops, so let's remove the round_rate() clk ops since it's unused. Signed-off-by: Brian Masney <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
* | clk: imx: pllv4: convert from round_rate() to determine_rate()Brian Masney2025-07-241-11/+18
| | | | | | | | | | | | | | | | | | | | | | The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
* | clk: imx: pllv3: convert from round_rate() to determine_rate()Brian Masney2025-07-241-32/+40
| | | | | | | | | | | | | | | | | | | | | | The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
* | clk: imx: pllv2: convert from round_rate() to determine_rate()Brian Masney2025-07-241-8/+15
| | | | | | | | | | | | | | | | | | | | | | The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
* | clk: imx: pll14xx: convert from round_rate() to determine_rate()Brian Masney2025-07-241-11/+18
| | | | | | | | | | | | | | | | | | | | | | The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
* | clk: imx: pfd: convert from round_rate() to determine_rate()Brian Masney2025-07-241-8/+10
| | | | | | | | | | | | | | | | | | | | | | The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
* | clk: imx: frac-pll: convert from round_rate() to determine_rate()Brian Masney2025-07-241-9/+11
| | | | | | | | | | | | | | | | | | | | | | The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
* | clk: imx: fracn-gppll: convert from round_rate() to determine_rate()Brian Masney2025-07-241-6/+11
| | | | | | | | | | | | | | | | | | | | | | The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
* | clk: imx: fixup-div: convert from round_rate() to determine_rate()Brian Masney2025-07-241-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. The change to call fixup_div->ops->determine_rate() instead of fixup_div->ops->round_rate() was done by hand. Signed-off-by: Brian Masney <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
* | clk: imx: cpu: convert from round_rate() to determine_rate()Brian Masney2025-07-241-4/+6
| | | | | | | | | | | | | | | | | | | | | | The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
* | clk: imx: busy: convert from round_rate() to determine_rate()Brian Masney2025-07-241-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. The change to call busy->div_ops->determine_rate() instead of busy->div_ops->round_rate() was done by hand. Signed-off-by: Brian Masney <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
* | clk: imx: composite-93: remove round_rate() in favor of determine_rate()Brian Masney2025-07-241-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | This driver implements both the determine_rate() and round_rate() clk ops, and the round_rate() clk ops is deprecated. When both are defined, clk_core_determine_round_nolock() from the clk core will only use the determine_rate() clk ops, so let's remove the round_rate() clk ops since it's unused. Signed-off-by: Brian Masney <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
* | clk: imx: composite-8m: remove round_rate() in favor of determine_rate()Brian Masney2025-07-241-16/+0
|/ | | | | | | | | | | | | This driver implements both the determine_rate() and round_rate() clk ops, and the round_rate() clk ops is deprecated. When both are defined, clk_core_determine_round_nolock() from the clk core will only use the determine_rate() clk ops, so let's remove the round_rate() clk ops since it's unused. Signed-off-by: Brian Masney <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
* clk: imx8mp: inform CCF of maximum frequency of clocksAhmad Fatoum2025-03-031-0/+151
| | | | | | | | | | | | | | | | | | | The IMX8MPCEC datasheet lists maximum frequencies allowed for different modules. Some of these limits are universal, but some depend on whether the SoC is operating in nominal or in overdrive mode. The imx8mp.dtsi currently assumes overdrive mode and configures some clocks in accordance with this. Boards wishing to make use of nominal mode will need to override some of the clock rates manually. As operating the clocks outside of their allowed range can lead to difficult to debug issues, it makes sense to register the maximum rates allowed in the driver, so the CCF can take them into account. Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Ahmad Fatoum <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* clk: clk-imx8mp-audiomix: fix dsp/ocram_a clock parentsLaurentiu Mihalcea2025-03-031-3/+3
| | | | | | | | | | | | | The DSP and OCRAM_A modules from AUDIOMIX are clocked by AUDIO_AXI_CLK_ROOT, not AUDIO_AHB_CLK_ROOT. Update the clock data accordingly. Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block control") Signed-off-by: Laurentiu Mihalcea <[email protected]> Reviewed-by: Iuliana Prodan <[email protected]> Reviewed-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* Merge branch 'clk-fixes' into clk-nextStephen Boyd2025-01-211-1/+2
|\ | | | | | | | | | | | | | | | | * clk-fixes: clk: clk-loongson2: Fix the number count of clk provider clk: mmp2: call pm_genpd_init() only after genpd.name is set clk: sunxi-ng: a100: enable MMC clock reparenting clk: clk-imx8mp-audiomix: fix function signature clk: thead: Fix TH1520 emmc and shdci clock rate
| * clk: clk-imx8mp-audiomix: fix function signatureNikolaus Voss2024-12-201-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk_imx8mp_audiomix_reset_controller_register() in the "if !CONFIG_RESET_CONTROLLER" branch had the first argument missing. It is an empty function for this branch so it wasn't immediately apparent. Fixes: 6f0e817175c5 ("clk: imx: clk-audiomix: Add reset controller") Cc: <[email protected]> # 6.12.x Signed-off-by: Nikolaus Voss <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Daniel Baluta <[email protected]> Acked-by: Shengjiu Wang <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
* | clk: imx: Apply some clks only for i.MX93Peng Fan2024-12-261-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | Enable the LVDS gate, MIPI DSI, PXP, FLEXIO and MU only for i.MX93, because i.MX91 does not support them. Update enet clk entry format to align with others. Fixes: a27bfff88dd2 ("clk: imx: add i.MX91 clk") Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* | clk: imx93: Add IMX93_CLK_SPDIF_IPG clockShengjiu Wang2024-12-261-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Split IMX93_CLK_SPDIF_IPG from IMX93_CLK_SPDIF_GATE because the IMX93_CLK_SPDIF_GATE controls the gate of IPG clock and root clock. Without this change, disabling IMX93_CLK_SPDIF_GATE would also disable the IPG clock, causing register access failures. Fixes: 1c4a4f7362fd ("arm64: dts: imx93: Add audio device nodes") Signed-off-by: Shengjiu Wang <[email protected]> Reviewed-by: Frank Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* | clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416xMarek Vasut2024-12-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The PLL1416x is used to implement SYS_PLL3 on i.MX8MP and can be used to drive CLKOUTn clock. Add 208 MHz and 416 MHz entries to the PLL so they can be generated by the PLL and used to produce e.g. 13 MHz or 26 MHz on CLKOUTn output. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* | clk: imx8mp: Fix clkout1/2 supportMarek Vasut2024-12-261-2/+3
|/ | | | | | | | | | | | | | | The CLKOUTn may be fed from PLL1/2/3, but the PLL1/2/3 has to be enabled first by setting PLL_CLKE bit 11 in CCM_ANALOG_SYS_PLLn_GEN_CTRL register. The CCM_ANALOG_SYS_PLLn_GEN_CTRL bit 11 is modeled by plln_out clock. Fix the clock tree and place the clkout1/2 under plln_sel instead of plain plln to let the clock subsystem correctly control the bit 11 and enable the PLL in case the CLKOUTn is supplied by PLL1/2/3. Fixes: 43896f56b59e ("clk: imx8mp: add clkout1/2 support") Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* clk: imx: imx8-acm: Fix return value check in clk_imx_acm_attach_pm_domains()Yang Yingliang2024-11-051-2/+2
| | | | | | | | | | | | If device_link_add() fails, it returns NULL pointer not ERR_PTR(), replace IS_ERR() with NULL pointer check, and return -EINVAL. Fixes: d3a0946d7ac9 ("clk: imx: imx8: add audio clock mux driver") Signed-off-by: Yang Yingliang <[email protected]> Reviewed-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* clk: imx: lpcg-scu: Skip HDMI LPCG clock save/restorePeng Fan2024-11-051-0/+6
| | | | | | | | | | | | | | | On i.MX8QM, HDMI LPCG clocks operation needs SCU clock "hdmi_ipg_clk" to be ON. While during noirq suspend phase, "hdmi_ipg_clk" is disabled by HDMI IRQ STEER driver, so SError will be triggered when accessing the HDMI LPCG registers. Skip all HDMI LPCG clocks save/restore to avoid SError during system suspend/resume, it will NOT introduce additional power consumption as their parent clock is disabled when suspend. Signed-off-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* clk: imx: clk-scu: fix clk enable state save and restoreDong Aisheng2024-11-051-1/+1
| | | | | | | | | | | | | | | | | | The scu clk_ops only inplements prepare() and unprepare() callback. Saving the clock state during suspend by checking clk_hw_is_enabled() is not safe as it's possible that some device drivers may only disable the clocks without unprepare. Then the state retention will not work for such clocks. Fixing it by checking clk_hw_is_prepared() which is more reasonable and safe. Fixes: d0409631f466 ("clk: imx: scu: add suspend/resume support") Reviewed-by: Peng Fan <[email protected]> Tested-by: Carlos Song <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* clk: imx: fracn-gppll: fix pll power upPeng Fan2024-11-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To i.MX93 which features dual Cortex-A55 cores and DSU, when using writel_relaxed to write value to PLL registers, the value might be buffered. To make sure the value has been written into the hardware, using readl to read back the register could achieve the goal. current PLL power up flow can be simplified as below: 1. writel_relaxed to set the PLL POWERUP bit; 2. readl_poll_timeout to check the PLL lock bit: a). timeout = ktime_add_us(ktime_get(), timeout_us); b). readl the pll the lock reg; c). check if the pll lock bit ready d). check if timeout But in some corner cases, both the write in step 1 and read in step 2 will be blocked by other bus transaction in the SoC for a long time, saying the value into real hardware is just before step b). That means the timeout counting has begins for quite sometime since step a), but value still not written into real hardware until bus released just at a point before step b). Then there maybe chances that the pll lock bit is not ready when readl done but the timeout happens. readl_poll_timeout will err return due to timeout. To avoid such unexpected failure, read back the reg to make sure the write has been done in HW reg. So use readl after writel_relaxed to fix the issue. Since we are here, to avoid udelay to run before writel_relaxed, use readl before udelay. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Co-developed-by: Jacky Bai <[email protected]> Signed-off-by: Jacky Bai <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* clk: imx: fracn-gppll: correct PLL initialization flowPeng Fan2024-11-051-3/+3
| | | | | | | | | | | | | | | | | | | | | | Per i.MX93 Reference Mannual 22.4 Initialization information 1. Program appropriate value of DIV[ODIV], DIV[RDIV] and DIV[MFI] as per Integer mode. 2. Wait for 5 μs. 3. Program the following field in CTRL register. Set CTRL[POWERUP] to 1'b1 to enable PLL block. 4. Poll PLL_STATUS[PLL_LOCK] register, and wait till PLL_STATUS[PLL_LOCK] is 1'b1 and pll_lock output signal is 1'b1. 5. Set CTRL[CLKMUX_EN] to 1'b1 to enable PLL output clock. So move the CLKMUX_EN operation after PLL locked. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Co-developed-by: Jacky Bai <[email protected]> Signed-off-by: Jacky Bai <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* clk: imx: lpcg-scu: SW workaround for errata (e10858)Peng Fan2024-11-051-8/+29
| | | | | | | | | | | | | | | | | | Back-to-back LPCG writes can be ignored by the LPCG register due to a HW bug. The writes need to be separated by at least 4 cycles of the gated clock. See https://www.nxp.com.cn/docs/en/errata/IMX8_1N94W.pdf The workaround is implemented as follows: 1. For clocks running greater than or equal to 24MHz, a read followed by the write will provide sufficient delay. 2. For clocks running below 24MHz, add a delay of 4 clock cylces after the write to the LPCG register. Fixes: 2f77296d3df9 ("clk: imx: add lpcg clock support") Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* clk: imx: add i.MX91 clkPengfei Li2024-10-231-24/+39
| | | | | | | | | | | | | | | Reuse i.MX93 clk driver for i.MX91, because i.MX91 reuses the Clock Control Module from i.MX93, with only a few clocks removed and a few clocks added. For clocks specific to i.MX93 use PLAT_IMX93 to flag them, for clocks specific to i.MX91, use PLAT_IMX91 to flag them. Others are shared by both. Signed-off-by: Pengfei Li <[email protected]> Reviewed-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* clk: imx93: Move IMX93_CLK_END macro to clk driverPengfei Li2024-10-231-0/+2
| | | | | | | | | | | | | IMX93_CLK_END was previously defined in imx93-clock.h to indicate the number of clocks. However, it is not part of the ABI. For starters it does no really appear in DTS. But what's more important - new clocks are described later, which contradicts this define in binding header. So move this macro to clock driver. Signed-off-by: Pengfei Li <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* clk: imx95-blk-ctl: Add one clock gate for HSIO blockRichard Zhu2024-10-221-0/+20
| | | | | | | | | | | | | | CREF_EN (Bit6) of LFAST_IO_REG control i.MX95 PCIe REF clock out enable/disable. Add compatible string "nxp,imx95-hsio-blk-ctl" to support PCIe REF clock out gate. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
* clk: Switch back to struct platform_driver::remove()Uwe Kleine-König2024-09-212-2/+2
| | | | | | | | | | | | | | | | After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all clk drivers to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. Signed-off-by: Uwe Kleine-König <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Geert Uytterhoeven <[email protected]> # renesas Signed-off-by: Stephen Boyd <[email protected]>
* Merge branch 'clk-imx-old' into clk-imxStephen Boyd2024-09-0514-49/+191
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-imx: (22 commits) clk: imx: composite-7ulp: Use NULL instead of 0 clk: imx: add missing MODULE_DESCRIPTION() macros clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate clk: imx: fracn-gppll: update rate table clk: imx: imx8qxp: Parent should be initialized earlier than the clock clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks clk: imx: imx8qxp: Add LVDS bypass clocks clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one clk: imx: imx8mn: add sai7_ipg_clk clock settings clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D clk: imx: imx8mp: fix clock tree update of TF-A managed clocks clk: imx: fracn-gppll: fix fractional part of PLL getting lost clk: imx: composite-7ulp: Check the PCC present bit clk: imx: composite-93: keep root clock on when mcore enabled clk: imx: composite-8m: Enable gate clk with mcore_booted clk: imx: imx6ul: fix default parent for enet*_ref_sel clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpll clk: imx: clk-audiomix: Add CLK_SET_RATE_PARENT flags for clocks ...
| * clk: imx: composite-7ulp: Use NULL instead of 0Peng Fan2024-06-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Address the sparse warnings " sparse warnings: (new ones prefixed by >>) >> drivers/clk/imx/clk-composite-7ulp.c:85:24: sparse: sparse: Using plain integer as NULL pointer " Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
| * clk: imx: add missing MODULE_DESCRIPTION() macrosJeff Johnson2024-06-242-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/imx/mxc-clk.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/imx/clk-imxrt1050.o Add the missing invocations of the MODULE_DESCRIPTION() macro. Signed-off-by: Jeff Johnson <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
| * clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rateMarek Vasut2024-06-212-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | The media_disp[12]_pix clock supply LCDIFv3 pixel clock output. These clocks are usually the only downstream clock from Video PLL on i.MX8MP. Allow these clocks to reconfigure the Video PLL, as that results in accurate pixel clock. If the Video PLL is not reconfigured, the pixel clock accuracy is low. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
| * clk: imx: fracn-gppll: update rate tablePeng Fan2024-06-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | - Add 1039.5MHz clock for video PLL to fulfill the LVDS display 148.5MHz * 7 requirement - Add 800MHz clock for ARM PLL Signed-off-by: Jacky Bai <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
| * clk: imx: imx8qxp: Parent should be initialized earlier than the clockPeng Fan2024-06-211-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The initialization order of SCU clocks affects the sequence of SCU clock resume. If there are no other effects, the earlier the initialization, the earlier the resume. During SCU clock resume, the clock rate is restored. As SCFW guidelines, configure the parent clock rate before configuring the child rate. Fixes: babfaa9556d7 ("clk: imx: scu: add more scu clocks") Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
| * clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clkPeng Fan2024-06-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The initialization order of SCU clocks affects the sequence of SCU clock resume. If there are no other effects, the earlier the initialization, the earlier the resume. During SCU clock resume, the clock rate is restored. As SCFW guidelines, configure the parent clock rate before configuring the child rate. Fixes: 91e916771de0 ("clk: imx: scu: remove legacy scu clock binding support") Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
| * clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocksOliver F. Brown2024-06-211-4/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPI Pixel and PHY Reference can use the bypass clock as a source. The MIPI bypass clock is the Pixel clock from the Display controller via the pixel link. Using the pixel clock for the PHY reference allows the MIPI bit clock match the pixel rate exactly. The MIPI pixel clock is currently set to be source from the bypass clock in the SCFW. This patch allows the pixel clock parent to be set by the kernel in the event that the SCFW default clock parent may change in the future. Signed-off-by: Oliver F. Brown <[email protected]> Signed-off-by: Robert Chiras <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
| * clk: imx: imx8qxp: Add LVDS bypass clocksPeng Fan2024-06-211-9/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For iMX8QXP and iMX8QM, add bypass clocks and register some of the LVDS clocks with imx_clk_scu2 as the parent needs to explicitly set. In order to make sure MIPI DSI works well after suspend/resume, the LVDS pixel and phy clocks must be initialized before the MIPI tx_esacpe and rx_escape clocks. LVDS phy, LVDS pixel, tx_escape, and rx_esacpe are all on the same MSLICE. They all share the same clock parent. So, setting the parent source or rate affects all of these clocks. In the LVDS use case the MIPI tx_escape and rx_escape are not saved and restored. So, LVDS works for either clock initialization order. For MIPI case, LVDS must be initialized first. Signed-off-by: Ranjani Vaidyanathan <[email protected]> Signed-off-by: Oliver F. Brown <[email protected]> Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
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