diff options
Diffstat (limited to 'drivers/misc')
| -rw-r--r-- | drivers/misc/Kconfig | 26 | ||||
| -rw-r--r-- | drivers/misc/Makefile | 3 | ||||
| -rw-r--r-- | drivers/misc/bcm2835_smi.c | 952 | ||||
| -rw-r--r-- | drivers/misc/rp1-fw-pio.h | 56 | ||||
| -rw-r--r-- | drivers/misc/rp1-pio.c | 1371 | ||||
| -rw-r--r-- | drivers/misc/ws2812-pio-rp1.c | 507 |
6 files changed, 2915 insertions, 0 deletions
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index b9c11f67315f..7567a4ef56c7 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -9,6 +9,32 @@ config SENSORS_LIS3LV02D tristate depends on INPUT +config BCM2835_SMI + tristate "Broadcom 283x Secondary Memory Interface driver" + depends on ARCH_BCM2835 + default m + help + Driver for enabling and using Broadcom's Secondary/Slow Memory Interface. + Appears as /dev/bcm2835_smi. For ioctl interface see drivers/misc/bcm2835_smi.h + +config RP1_PIO + tristate "Raspberry Pi RP1 PIO driver" + depends on FIRMWARE_RP1 || COMPILE_TEST + default n + help + Driver providing control of the Raspberry Pi PIO block, as found in + RP1. + +config WS2812_PIO_RP1 + tristate "Raspberry Pi PIO-base WS2812 driver" + depends on RP1_PIO || COMPILE_TEST + default n + help + Driver for the WS2812 (NeoPixel) LEDs using the RP1 PIO hardware. + The driver creates a character device to which rgbw pixels may be + written. Single-byte writes to offset 0 set the brightness at + runtime. + config AD525X_DPOT tristate "Analog Devices Digital Potentiometers" depends on (I2C || SPI) && SYSFS diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index b32a2597d246..9b9eba1ef245 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_AD525X_DPOT) += ad525x_dpot.o obj-$(CONFIG_AD525X_DPOT_I2C) += ad525x_dpot-i2c.o obj-$(CONFIG_AD525X_DPOT_SPI) += ad525x_dpot-spi.o obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o +obj-$(CONFIG_BCM2835_SMI) += bcm2835_smi.o obj-$(CONFIG_DUMMY_IRQ) += dummy-irq.o obj-$(CONFIG_ICS932S401) += ics932s401.o obj-$(CONFIG_LKDTM) += lkdtm/ @@ -19,6 +20,8 @@ obj-$(CONFIG_PHANTOM) += phantom.o obj-$(CONFIG_RPMB) += rpmb-core.o obj-$(CONFIG_QCOM_COINCELL) += qcom-coincell.o obj-$(CONFIG_QCOM_FASTRPC) += fastrpc.o +obj-$(CONFIG_RP1_PIO) += rp1-pio.o +obj-$(CONFIG_WS2812_PIO_RP1) += ws2812-pio-rp1.o obj-$(CONFIG_SENSORS_BH1770) += bh1770glc.o obj-$(CONFIG_SENSORS_APDS990X) += apds990x.o obj-$(CONFIG_ENCLOSURE_SERVICES) += enclosure.o diff --git a/drivers/misc/bcm2835_smi.c b/drivers/misc/bcm2835_smi.c new file mode 100644 index 000000000000..09246d5ea7d0 --- /dev/null +++ b/drivers/misc/bcm2835_smi.c @@ -0,0 +1,952 @@ +/** + * Broadcom Secondary Memory Interface driver + * + * Written by Luke Wren <[email protected]> + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2, as published by the Free + * Software Foundation. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <linux/clk.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/mm.h> +#include <linux/slab.h> +#include <linux/pagemap.h> +#include <linux/dma-mapping.h> +#include <linux/dmaengine.h> +#include <linux/semaphore.h> +#include <linux/spinlock.h> +#include <linux/io.h> + +#define BCM2835_SMI_IMPLEMENTATION +#include <linux/broadcom/bcm2835_smi.h> + +#define DRIVER_NAME "smi-bcm2835" + +#define N_PAGES_FROM_BYTES(n) ((n + PAGE_SIZE-1) / PAGE_SIZE) + +#define DMA_WRITE_TO_MEM true +#define DMA_READ_FROM_MEM false + +struct bcm2835_smi_instance { + struct device *dev; + struct smi_settings settings; + __iomem void *smi_regs_ptr; + phys_addr_t smi_regs_busaddr; + + struct dma_chan *dma_chan; + struct dma_slave_config dma_config; + + struct bcm2835_smi_bounce_info bounce; + + struct scatterlist buffer_sgl; + + struct clk *clk; + + /* Sometimes we are called into in an atomic context (e.g. by + JFFS2 + MTD) so we can't use a mutex */ + spinlock_t transaction_lock; +}; + +/**************************************************************************** +* +* SMI peripheral setup +* +***************************************************************************/ + +static inline void write_smi_reg(struct bcm2835_smi_instance *inst, + u32 val, unsigned reg) +{ + writel(val, inst->smi_regs_ptr + reg); +} + +static inline u32 read_smi_reg(struct bcm2835_smi_instance *inst, unsigned reg) +{ + return readl(inst->smi_regs_ptr + reg); +} + +/* Token-paste macro for e.g SMIDSR_RSTROBE -> value of SMIDSR_RSTROBE_MASK */ +#define _CONCAT(x, y) x##y +#define CONCAT(x, y) _CONCAT(x, y) + +#define SET_BIT_FIELD(dest, field, bits) ((dest) = \ + ((dest) & ~CONCAT(field, _MASK)) | (((bits) << CONCAT(field, _OFFS))& \ + CONCAT(field, _MASK))) +#define GET_BIT_FIELD(src, field) (((src) & \ + CONCAT(field, _MASK)) >> CONCAT(field, _OFFS)) + +static void smi_dump_context_labelled(struct bcm2835_smi_instance *inst, + const char *label) +{ + dev_err(inst->dev, "SMI context dump: %s", label); + dev_err(inst->dev, "SMICS: 0x%08x", read_smi_reg(inst, SMICS)); + dev_err(inst->dev, "SMIL: 0x%08x", read_smi_reg(inst, SMIL)); + dev_err(inst->dev, "SMIDSR: 0x%08x", read_smi_reg(inst, SMIDSR0)); + dev_err(inst->dev, "SMIDSW: 0x%08x", read_smi_reg(inst, SMIDSW0)); + dev_err(inst->dev, "SMIDC: 0x%08x", read_smi_reg(inst, SMIDC)); + dev_err(inst->dev, "SMIFD: 0x%08x", read_smi_reg(inst, SMIFD)); + dev_err(inst->dev, " "); +} + +static inline void smi_dump_context(struct bcm2835_smi_instance *inst) +{ + smi_dump_context_labelled(inst, ""); +} + +static void smi_get_default_settings(struct bcm2835_smi_instance *inst) +{ + struct smi_settings *settings = &inst->settings; + + settings->data_width = SMI_WIDTH_16BIT; + settings->pack_data = true; + + settings->read_setup_time = 1; + settings->read_hold_time = 1; + settings->read_pace_time = 1; + settings->read_strobe_time = 3; + + settings->write_setup_time = settings->read_setup_time; + settings->write_hold_time = settings->read_hold_time; + settings->write_pace_time = settings->read_pace_time; + settings->write_strobe_time = settings->read_strobe_time; + + settings->dma_enable = true; + settings->dma_passthrough_enable = false; + settings->dma_read_thresh = 0x01; + settings->dma_write_thresh = 0x3f; + settings->dma_panic_read_thresh = 0x20; + settings->dma_panic_write_thresh = 0x20; +} + +void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *inst) +{ + struct smi_settings *settings = &inst->settings; + int smidsr_temp = 0, smidsw_temp = 0, smics_temp, + smidcs_temp, smidc_temp = 0; + + spin_lock(&inst->transaction_lock); + + /* temporarily disable the peripheral: */ + smics_temp = read_smi_reg(inst, SMICS); + write_smi_reg(inst, 0, SMICS); + smidcs_temp = read_smi_reg(inst, SMIDCS); + write_smi_reg(inst, 0, SMIDCS); + + if (settings->pack_data) + smics_temp |= SMICS_PXLDAT; + else + smics_temp &= ~SMICS_PXLDAT; + + SET_BIT_FIELD(smidsr_temp, SMIDSR_RWIDTH, settings->data_width); + SET_BIT_FIELD(smidsr_temp, SMIDSR_RSETUP, settings->read_setup_time); + SET_BIT_FIELD(smidsr_temp, SMIDSR_RHOLD, settings->read_hold_time); + SET_BIT_FIELD(smidsr_temp, SMIDSR_RPACE, settings->read_pace_time); + SET_BIT_FIELD(smidsr_temp, SMIDSR_RSTROBE, settings->read_strobe_time); + write_smi_reg(inst, smidsr_temp, SMIDSR0); + + SET_BIT_FIELD(smidsw_temp, SMIDSW_WWIDTH, settings->data_width); + if (settings->data_width == SMI_WIDTH_8BIT) + smidsw_temp |= SMIDSW_WSWAP; + else + smidsw_temp &= ~SMIDSW_WSWAP; + SET_BIT_FIELD(smidsw_temp, SMIDSW_WSETUP, settings->write_setup_time); + SET_BIT_FIELD(smidsw_temp, SMIDSW_WHOLD, settings->write_hold_time); + SET_BIT_FIELD(smidsw_temp, SMIDSW_WPACE, settings->write_pace_time); + SET_BIT_FIELD(smidsw_temp, SMIDSW_WSTROBE, + settings->write_strobe_time); + write_smi_reg(inst, smidsw_temp, SMIDSW0); + + SET_BIT_FIELD(smidc_temp, SMIDC_REQR, settings->dma_read_thresh); + SET_BIT_FIELD(smidc_temp, SMIDC_REQW, settings->dma_write_thresh); + SET_BIT_FIELD(smidc_temp, SMIDC_PANICR, + settings->dma_panic_read_thresh); + SET_BIT_FIELD(smidc_temp, SMIDC_PANICW, + settings->dma_panic_write_thresh); + if (settings->dma_passthrough_enable) { + smidc_temp |= SMIDC_DMAP; + smidsr_temp |= SMIDSR_RDREQ; + write_smi_reg(inst, smidsr_temp, SMIDSR0); + smidsw_temp |= SMIDSW_WDREQ; + write_smi_reg(inst, smidsw_temp, SMIDSW0); + } else + smidc_temp &= ~SMIDC_DMAP; + if (settings->dma_enable) + smidc_temp |= SMIDC_DMAEN; + else + smidc_temp &= ~SMIDC_DMAEN; + + write_smi_reg(inst, smidc_temp, SMIDC); + + /* re-enable (if was previously enabled) */ + write_smi_reg(inst, smics_temp, SMICS); + write_smi_reg(inst, smidcs_temp, SMIDCS); + + spin_unlock(&inst->transaction_lock); +} +EXPORT_SYMBOL(bcm2835_smi_set_regs_from_settings); + +struct smi_settings *bcm2835_smi_get_settings_from_regs + (struct bcm2835_smi_instance *inst) +{ + struct smi_settings *settings = &inst->settings; + int smidsr, smidsw, smidc; + + spin_lock(&inst->transaction_lock); + + smidsr = read_smi_reg(inst, SMIDSR0); + smidsw = read_smi_reg(inst, SMIDSW0); + smidc = read_smi_reg(inst, SMIDC); + + settings->pack_data = (read_smi_reg(inst, SMICS) & SMICS_PXLDAT) ? + true : false; + + settings->data_width = GET_BIT_FIELD(smidsr, SMIDSR_RWIDTH); + settings->read_setup_time = GET_BIT_FIELD(smidsr, SMIDSR_RSETUP); + settings->read_hold_time = GET_BIT_FIELD(smidsr, SMIDSR_RHOLD); + settings->read_pace_time = GET_BIT_FIELD(smidsr, SMIDSR_RPACE); + settings->read_strobe_time = GET_BIT_FIELD(smidsr, SMIDSR_RSTROBE); + + settings->write_setup_time = GET_BIT_FIELD(smidsw, SMIDSW_WSETUP); + settings->write_hold_time = GET_BIT_FIELD(smidsw, SMIDSW_WHOLD); + settings->write_pace_time = GET_BIT_FIELD(smidsw, SMIDSW_WPACE); + settings->write_strobe_time = GET_BIT_FIELD(smidsw, SMIDSW_WSTROBE); + + settings->dma_read_thresh = GET_BIT_FIELD(smidc, SMIDC_REQR); + settings->dma_write_thresh = GET_BIT_FIELD(smidc, SMIDC_REQW); + settings->dma_panic_read_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICR); + settings->dma_panic_write_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICW); + settings->dma_passthrough_enable = (smidc & SMIDC_DMAP) ? true : false; + settings->dma_enable = (smidc & SMIDC_DMAEN) ? true : false; + + spin_unlock(&inst->transaction_lock); + + return settings; +} +EXPORT_SYMBOL(bcm2835_smi_get_settings_from_regs); + +static inline void smi_set_address(struct bcm2835_smi_instance *inst, + unsigned int address) +{ + int smia_temp = 0, smida_temp = 0; + + SET_BIT_FIELD(smia_temp, SMIA_ADDR, address); + SET_BIT_FIELD(smida_temp, SMIDA_ADDR, address); + + /* Write to both address registers - user doesn't care whether we're + doing programmed or direct transfers. */ + write_smi_reg(inst, smia_temp, SMIA); + write_smi_reg(inst, smida_temp, SMIDA); +} + +static void smi_setup_regs(struct bcm2835_smi_instance *inst) +{ + + dev_dbg(inst->dev, "Initialising SMI registers..."); + /* Disable the peripheral if already enabled */ + write_smi_reg(inst, 0, SMICS); + write_smi_reg(inst, 0, SMIDCS); + + smi_get_default_settings(inst); + bcm2835_smi_set_regs_from_settings(inst); + smi_set_address(inst, 0); + + write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ENABLE, SMICS); + write_smi_reg(inst, read_smi_reg(inst, SMIDCS) | SMIDCS_ENABLE, + SMIDCS); +} + +/**************************************************************************** +* +* Low-level SMI access functions +* Other modules should use the exported higher-level functions e.g. +* bcm2835_smi_write_buf() unless they have a good reason to use these +* +***************************************************************************/ + +static inline uint32_t smi_read_single_word(struct bcm2835_smi_instance *inst) +{ + int timeout = 0; + + write_smi_reg(inst, SMIDCS_ENABLE, SMIDCS); + write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_START, SMIDCS); + /* Make sure things happen in the right order...*/ + mb(); + while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) && + ++timeout < 10000) + ; + if (timeout < 10000) + return read_smi_reg(inst, SMIDD); + + dev_err(inst->dev, + "SMI direct read timed out (is the clock set up correctly?)"); + return 0; +} + +static inline void smi_write_single_word(struct bcm2835_smi_instance *inst, + uint32_t data) +{ + int timeout = 0; + + write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE, SMIDCS); + write_smi_reg(inst, data, SMIDD); + write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE | SMIDCS_START, + SMIDCS); + + while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) && + ++timeout < 10000) + ; + if (timeout >= 10000) + dev_err(inst->dev, + "SMI direct write timed out (is the clock set up correctly?)"); +} + +/* Initiates a programmed read into the read FIFO. It is up to the caller to + * read data from the FIFO - either via paced DMA transfer, + * or polling SMICS_RXD to check whether data is available. + * SMICS_ACTIVE will go low upon completion. */ +static void smi_init_programmed_read(struct bcm2835_smi_instance *inst, + int num_transfers) +{ + int smics_temp; + + /* Disable the peripheral: */ + smics_temp = read_smi_reg(inst, SMICS) & ~(SMICS_ENABLE | SMICS_WRITE); + write_smi_reg(inst, smics_temp, SMICS); + while (read_smi_reg(inst, SMICS) & SMICS_ENABLE) + ; + + /* Program the transfer count: */ + write_smi_reg(inst, num_transfers, SMIL); + + /* re-enable and start: */ + smics_temp |= SMICS_ENABLE; + write_smi_reg(inst, smics_temp, SMICS); + smics_temp |= SMICS_CLEAR; + /* Just to be certain: */ + mb(); + while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE) + ; + write_smi_reg(inst, smics_temp, SMICS); + smics_temp |= SMICS_START; + write_smi_reg(inst, smics_temp, SMICS); +} + +/* Initiates a programmed write sequence, using data from the write FIFO. + * It is up to the caller to initiate a DMA transfer before calling, + * or use another method to keep the write FIFO topped up. + * SMICS_ACTIVE will go low upon completion. + */ +static void smi_init_programmed_write(struct bcm2835_smi_instance *inst, + int num_transfers) +{ + int smics_temp; + + /* Disable the peripheral: */ + smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE; + write_smi_reg(inst, smics_temp, SMICS); + while (read_smi_reg(inst, SMICS) & SMICS_ENABLE) + ; + + /* Program the transfer count: */ + write_smi_reg(inst, num_transfers, SMIL); + + /* setup, re-enable and start: */ + smics_temp |= SMICS_WRITE | SMICS_ENABLE; + write_smi_reg(inst, smics_temp, SMICS); + smics_temp |= SMICS_START; + write_smi_reg(inst, smics_temp, SMICS); +} + +/* Initiate a read and then poll FIFO for data, reading out as it appears. */ +static void smi_read_fifo(struct bcm2835_smi_instance *inst, + uint32_t *dest, int n_bytes) +{ + if (read_smi_reg(inst, SMICS) & SMICS_RXD) { + smi_dump_context_labelled(inst, + "WARNING: read FIFO not empty at start of read call."); + while (read_smi_reg(inst, SMICS)) + ; + } + + /* Dispatch the read: */ + if (inst->settings.data_width == SMI_WIDTH_8BIT) + smi_init_programmed_read(inst, n_bytes); + else if (inst->settings.data_width == SMI_WIDTH_16BIT) + smi_init_programmed_read(inst, n_bytes / 2); + else { + dev_err(inst->dev, "Unsupported data width for read."); + return; + } + + /* Poll FIFO to keep it empty */ + while (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) + if (read_smi_reg(inst, SMICS) & SMICS_RXD) + *dest++ = read_smi_reg(inst, SMID); + + /* Ensure that the FIFO is emptied */ + if (read_smi_reg(inst, SMICS) & SMICS_RXD) { + int fifo_count; + + fifo_count = GET_BIT_FIELD(read_smi_reg(inst, SMIFD), + SMIFD_FCNT); + while (fifo_count--) + *dest++ = read_smi_reg(inst, SMID); + } + + if (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) + smi_dump_context_labelled(inst, + "WARNING: transaction finished but done bit not set."); + + if (read_smi_reg(inst, SMICS) & SMICS_RXD) + smi_dump_context_labelled(inst, + "WARNING: read FIFO not empty at end of read call."); + +} + +/* Initiate a write, and then keep the FIFO topped up. */ +static void smi_write_fifo(struct bcm2835_smi_instance *inst, + uint32_t *src, int n_bytes) +{ + int i, timeout = 0; + + /* Empty FIFOs if not already so */ + if (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) { + smi_dump_context_labelled(inst, + "WARNING: write fifo not empty at start of write call."); + write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_CLEAR, + SMICS); + } + + /* Initiate the transfer */ + if (inst->settings.data_width == SMI_WIDTH_8BIT) + smi_init_programmed_write(inst, n_bytes); + else if (inst->settings.data_width == SMI_WIDTH_16BIT) + smi_init_programmed_write(inst, n_bytes / 2); + else { + dev_err(inst->dev, "Unsupported data width for write."); + return; + } + /* Fill the FIFO: */ + for (i = 0; i < (n_bytes - 1) / 4 + 1; ++i) { + while (!(read_smi_reg(inst, SMICS) & SMICS_TXD)) + ; + write_smi_reg(inst, *src++, SMID); + } + /* Busy wait... */ + while (!(read_smi_reg(inst, SMICS) & SMICS_DONE) && ++timeout < + 1000000) + ; + if (timeout >= 1000000) + smi_dump_context_labelled(inst, + "Timed out on write operation!"); + if (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) + smi_dump_context_labelled(inst, + "WARNING: FIFO not empty at end of write operation."); +} + +/**************************************************************************** +* +* SMI DMA operations +* +***************************************************************************/ + +/* Disable SMI and put it into the correct direction before doing DMA setup. + Stops spurious DREQs during setup. Peripheral is re-enabled by init_*() */ +static void smi_disable(struct bcm2835_smi_instance *inst, + enum dma_transfer_direction direction) +{ + int smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE; + + if (direction == DMA_DEV_TO_MEM) + smics_temp &= ~SMICS_WRITE; + else + smics_temp |= SMICS_WRITE; + write_smi_reg(inst, smics_temp, SMICS); + while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE) + ; +} + +static struct scatterlist *smi_scatterlist_from_buffer( + struct bcm2835_smi_instance *inst, + dma_addr_t buf, + size_t len, + struct scatterlist *sg) +{ + sg_init_table(sg, 1); + sg_dma_address(sg) = buf; + sg_dma_len(sg) = len; + return sg; +} + +static void smi_dma_callback_user_copy(void *param) +{ + /* Notify the bottom half that a chunk is ready for user copy */ + struct bcm2835_smi_instance *inst = + (struct bcm2835_smi_instance *)param; + + up(&inst->bounce.callback_sem); +} + +/* Creates a descriptor, assigns the given callback, and submits the + descriptor to dmaengine. Does not block - can queue up multiple + descriptors and then wait for them all to complete. + sg_len is the number of control blocks, NOT the number of bytes. + dir can be DMA_MEM_TO_DEV or DMA_DEV_TO_MEM. + callback can be NULL - in this case it is not called. */ +static inline struct dma_async_tx_descriptor *smi_dma_submit_sgl( + struct bcm2835_smi_instance *inst, + struct scatterlist *sgl, + size_t sg_len, + enum dma_transfer_direction dir, + dma_async_tx_callback callback) +{ + struct dma_async_tx_descriptor *desc; + + desc = dmaengine_prep_slave_sg(inst->dma_chan, + sgl, + sg_len, + dir, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK | + DMA_PREP_FENCE); + if (!desc) { + dev_err(inst->dev, "read_sgl: dma slave preparation failed!"); + write_smi_reg(inst, read_smi_reg(inst, SMICS) & ~SMICS_ACTIVE, + SMICS); + while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE) + cpu_relax(); + write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ACTIVE, + SMICS); + return NULL; + } + desc->callback = callback; + desc->callback_param = inst; + if (dmaengine_submit(desc) < 0) + return NULL; + return desc; +} + +/* NB this function blocks until the transfer is complete */ +static void +smi_dma_read_sgl(struct bcm2835_smi_instance *inst, + struct scatterlist *sgl, size_t sg_len, size_t n_bytes) +{ + struct dma_async_tx_descriptor *desc; + + /* Disable SMI and set to read before dispatching DMA - if SMI is in + * write mode and TX fifo is empty, it will generate a DREQ which may + * cause the read DMA to complete before the SMI read command is even + * dispatched! We want to dispatch DMA before SMI read so that reading + * is gapless, for logic analyser. + */ + + smi_disable(inst, DMA_DEV_TO_MEM); + + desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_DEV_TO_MEM, NULL); + dma_async_issue_pending(inst->dma_chan); + + if (inst->settings.data_width == SMI_WIDTH_8BIT) + smi_init_programmed_read(inst, n_bytes); + else + smi_init_programmed_read(inst, n_bytes / 2); + + if (dma_wait_for_async_tx(desc) == DMA_ERROR) + smi_dump_context_labelled(inst, "DMA timeout!"); +} + +static void +smi_dma_write_sgl(struct bcm2835_smi_instance *inst, + struct scatterlist *sgl, size_t sg_len, size_t n_bytes) +{ + struct dma_async_tx_descriptor *desc; + + if (inst->settings.data_width == SMI_WIDTH_8BIT) + smi_init_programmed_write(inst, n_bytes); + else + smi_init_programmed_write(inst, n_bytes / 2); + + desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_MEM_TO_DEV, NULL); + dma_async_issue_pending(inst->dma_chan); + + if (dma_wait_for_async_tx(desc) == DMA_ERROR) + smi_dump_context_labelled(inst, "DMA timeout!"); + else + /* Wait for SMI to finish our writes */ + while (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) + cpu_relax(); +} + +ssize_t bcm2835_smi_user_dma( + struct bcm2835_smi_instance *inst, + enum dma_transfer_direction dma_dir, + char __user *user_ptr, size_t count, + struct bcm2835_smi_bounce_info **bounce) +{ + int chunk_no = 0, chunk_size, count_left = count; + struct scatterlist *sgl; + void (*init_trans_func)(struct bcm2835_smi_instance *, int); + + spin_lock(&inst->transaction_lock); + + if (dma_dir == DMA_DEV_TO_MEM) + init_trans_func = smi_init_programmed_read; + else + init_trans_func = smi_init_programmed_write; + + smi_disable(inst, dma_dir); + + sema_init(&inst->bounce.callback_sem, 0); + if (bounce) + *bounce = &inst->bounce; + while (count_left) { + chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ? + DMA_BOUNCE_BUFFER_SIZE : count_left; + if (chunk_size == DMA_BOUNCE_BUFFER_SIZE) { + sgl = + &inst->bounce.sgl[chunk_no % DMA_BOUNCE_BUFFER_COUNT]; + } else { + sgl = smi_scatterlist_from_buffer( + inst, + inst->bounce.phys[ + chunk_no % DMA_BOUNCE_BUFFER_COUNT], + chunk_size, + &inst->buffer_sgl); + } + + if (!smi_dma_submit_sgl(inst, sgl, 1, dma_dir, + smi_dma_callback_user_copy + )) { + dev_err(inst->dev, "sgl submit failed"); + count = 0; + goto out; + } + count_left -= chunk_size; + chunk_no++; + } + dma_async_issue_pending(inst->dma_chan); + + if (inst->settings.data_width == SMI_WIDTH_8BIT) + init_trans_func(inst, count); + else if (inst->settings.data_width == SMI_WIDTH_16BIT) + init_trans_func(inst, count / 2); +out: + spin_unlock(&inst->transaction_lock); + return count; +} +EXPORT_SYMBOL(bcm2835_smi_user_dma); + + +/**************************************************************************** +* +* High level buffer transfer functions - for use by other drivers +* +***************************************************************************/ + +/* Buffer must be physically contiguous - i.e. kmalloc, not vmalloc! */ +void bcm2835_smi_write_buf( + struct bcm2835_smi_instance *inst, + const void *buf, size_t n_bytes) +{ + int odd_bytes = n_bytes & 0x3; + + n_bytes -= odd_bytes; + + spin_lock(&inst->transaction_lock); + + if (n_bytes > DMA_THRESHOLD_BYTES) { + dma_addr_t phy_addr = dma_map_single( + inst->dev, + (void *)buf, + n_bytes, + DMA_TO_DEVICE); + struct scatterlist *sgl = + smi_scatterlist_from_buffer(inst, phy_addr, n_bytes, + &inst->buffer_sgl); + + if (!sgl) { + smi_dump_context_labelled(inst, + "Error: could not create scatterlist for write!"); + goto out; + } + smi_dma_write_sgl(inst, sgl, 1, n_bytes); + + dma_unmap_single + (inst->dev, phy_addr, n_bytes, DMA_TO_DEVICE); + } else if (n_bytes) { + smi_write_fifo(inst, (uint32_t *) buf, n_bytes); + } + buf += n_bytes; + + if (inst->settings.data_width == SMI_WIDTH_8BIT) { + while (odd_bytes--) + smi_write_single_word(inst, *(uint8_t *) (buf++)); + } else { + while (odd_bytes >= 2) { + smi_write_single_word(inst, *(uint16_t *)buf); + buf += 2; + odd_bytes -= 2; + } + if (odd_bytes) { + /* Reading an odd number of bytes on a 16 bit bus is + a user bug. It's kinder to fail early and tell them + than to e.g. transparently give them the bottom byte + of a 16 bit transfer. */ + dev_err(inst->dev, + "WARNING: odd number of bytes specified for wide transfer."); + dev_err(inst->dev, + "At least one byte dropped as a result."); + dump_stack(); + } + } +out: + spin_unlock(&inst->transaction_lock); +} +EXPORT_SYMBOL(bcm2835_smi_write_buf); + +void bcm2835_smi_read_buf(struct bcm2835_smi_instance *inst, + void *buf, size_t n_bytes) +{ + + /* SMI is inherently 32-bit, which causes surprising amounts of mess + for bytes % 4 != 0. Easiest to avoid this mess altogether + by handling remainder separately. */ + int odd_bytes = n_bytes & 0x3; + + spin_lock(&inst->transaction_lock); + n_bytes -= odd_bytes; + if (n_bytes > DMA_THRESHOLD_BYTES) { + dma_addr_t phy_addr = dma_map_single(inst->dev, + buf, n_bytes, + DMA_FROM_DEVICE); + struct scatterlist *sgl = smi_scatterlist_from_buffer( + inst, phy_addr, n_bytes, + &inst->buffer_sgl); + if (!sgl) { + smi_dump_context_labelled(inst, + "Error: could not create scatterlist for read!"); + goto out; + } + smi_dma_read_sgl(inst, sgl, 1, n_bytes); + dma_unmap_single(inst->dev, phy_addr, n_bytes, DMA_FROM_DEVICE); + } else if (n_bytes) { + smi_read_fifo(inst, (uint32_t *)buf, n_bytes); + } + buf += n_bytes; + + if (inst->settings.data_width == SMI_WIDTH_8BIT) { + while (odd_bytes--) + *((uint8_t *) (buf++)) = smi_read_single_word(inst); + } else { + while (odd_bytes >= 2) { + *(uint16_t *) buf = smi_read_single_word(inst); + buf += 2; + odd_bytes -= 2; + } + if (odd_bytes) { + dev_err(inst->dev, + "WARNING: odd number of bytes specified for wide transfer."); + dev_err(inst->dev, + "At least one byte dropped as a result."); + dump_stack(); + } + } +out: + spin_unlock(&inst->transaction_lock); +} +EXPORT_SYMBOL(bcm2835_smi_read_buf); + +void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst, + unsigned int address) +{ + spin_lock(&inst->transaction_lock); + smi_set_address(inst, address); + spin_unlock(&inst->transaction_lock); +} +EXPORT_SYMBOL(bcm2835_smi_set_address); + +struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node) +{ + struct platform_device *pdev; + + if (!node) + return NULL; + + pdev = of_find_device_by_node(node); + if (!pdev) + return NULL; + + return platform_get_drvdata(pdev); +} +EXPORT_SYMBOL(bcm2835_smi_get); + +/**************************************************************************** +* +* bcm2835_smi_probe - called when the driver is loaded. +* +***************************************************************************/ + +static int bcm2835_smi_dma_setup(struct bcm2835_smi_instance *inst) +{ + int i, rv = 0; + + inst->dma_chan = dma_request_slave_channel(inst->dev, "rx-tx"); + + inst->dma_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + inst->dma_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + inst->dma_config.src_addr = inst->smi_regs_busaddr + SMID; + inst->dma_config.dst_addr = inst->dma_config.src_addr; + /* Direction unimportant - always overridden by prep_slave_sg */ + inst->dma_config.direction = DMA_DEV_TO_MEM; + dmaengine_slave_config(inst->dma_chan, &inst->dma_config); + /* Alloc and map bounce buffers */ + for (i = 0; i < DMA_BOUNCE_BUFFER_COUNT; ++i) { + inst->bounce.buffer[i] = + dmam_alloc_coherent(inst->dev, DMA_BOUNCE_BUFFER_SIZE, + &inst->bounce.phys[i], + GFP_KERNEL); + if (!inst->bounce.buffer[i]) { + dev_err(inst->dev, "Could not allocate buffer!"); + rv = -ENOMEM; + break; + } + smi_scatterlist_from_buffer( + inst, + inst->bounce.phys[i], + DMA_BOUNCE_BUFFER_SIZE, + &inst->bounce.sgl[i] + ); + } + + return rv; +} + +static int bcm2835_smi_probe(struct platform_device *pdev) +{ + int err; + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct resource *ioresource; + struct bcm2835_smi_instance *inst; + + /* We require device tree support */ + if (!node) + return -EINVAL; + /* Allocate buffers and instance data */ + inst = devm_kzalloc(dev, sizeof(struct bcm2835_smi_instance), + GFP_KERNEL); + if (!inst) + return -ENOMEM; + + inst->dev = dev; + spin_lock_init(&inst->transaction_lock); + + inst->smi_regs_ptr = devm_platform_get_and_ioremap_resource(pdev, 0, + &ioresource); + if (IS_ERR(inst->smi_regs_ptr)) { + err = PTR_ERR(inst->smi_regs_ptr); + goto err; + } + inst->smi_regs_busaddr = ioresource->start; + + err = bcm2835_smi_dma_setup(inst); + if (err) + goto err; + + /* request clock */ + inst->clk = devm_clk_get(dev, NULL); + if (!inst->clk) + goto err; + clk_prepare_enable(inst->clk); + + /* Finally, do peripheral setup */ + smi_setup_regs(inst); + + platform_set_drvdata(pdev, inst); + + dev_info(inst->dev, "initialised"); + + return 0; +err: + kfree(inst); + return err; +} + +/**************************************************************************** +* +* bcm2835_smi_remove - called when the driver is unloaded. +* +***************************************************************************/ + +static void bcm2835_smi_remove(struct platform_device *pdev) +{ + struct bcm2835_smi_instance *inst = platform_get_drvdata(pdev); + struct device *dev = inst->dev; + + dmaengine_terminate_all(inst->dma_chan); + dma_release_channel(inst->dma_chan); + + clk_disable_unprepare(inst->clk); + + dev_info(dev, "SMI device removed - OK"); +} + +/**************************************************************************** +* +* Register the driver with device tree +* +***************************************************************************/ + +static const struct of_device_id bcm2835_smi_of_match[] = { + {.compatible = "brcm,bcm2835-smi",}, + { /* sentinel */ }, +}; + +MODULE_DEVICE_TABLE(of, bcm2835_smi_of_match); + +static struct platform_driver bcm2835_smi_driver = { + .probe = bcm2835_smi_probe, + .remove = bcm2835_smi_remove, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = bcm2835_smi_of_match, + }, +}; + +module_platform_driver(bcm2835_smi_driver); + +MODULE_ALIAS("platform:smi-bcm2835"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Device driver for BCM2835's secondary memory interface"); +MODULE_AUTHOR("Luke Wren <[email protected]>"); diff --git a/drivers/misc/rp1-fw-pio.h b/drivers/misc/rp1-fw-pio.h new file mode 100644 index 000000000000..ba28cba38f84 --- /dev/null +++ b/drivers/misc/rp1-fw-pio.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 2023-2024 Raspberry Pi Ltd. + */ + +#ifndef __SOC_RP1_FIRMWARE_OPS_H__ +#define __SOC_RP1_FIRMWARE_OPS_H__ + +#include <linux/rp1-firmware.h> + +#define FOURCC_PIO RP1_FOURCC("PIO ") + +enum rp1_pio_ops { + PIO_CAN_ADD_PROGRAM, // u16 num_instrs, u16 origin -> origin + PIO_ADD_PROGRAM, // u16 num_instrs, u16 origin, u16 prog[] -> rc + PIO_REMOVE_PROGRAM, // u16 num_instrs, u16 origin + PIO_CLEAR_INSTR_MEM, // - + + PIO_SM_CLAIM, // u16 mask -> sm + PIO_SM_UNCLAIM, // u16 mask + PIO_SM_IS_CLAIMED, // u16 mask -> claimed + + PIO_SM_INIT, // u16 sm, u16 initial_pc, u32 sm_config[4] + PIO_SM_SET_CONFIG, // u16 sm, u16 rsvd, u32 sm_config[4] + PIO_SM_EXEC, // u16 sm, u16 instr, u8 blocking, u8 rsvd + PIO_SM_CLEAR_FIFOS, // u16 sm + PIO_SM_SET_CLKDIV, // u16 sm, u16 div_int, u8 div_frac, u8 rsvd + PIO_SM_SET_PINS, // u16 sm, u16 rsvd, u32 values, u32 mask + PIO_SM_SET_PINDIRS, // u16 sm, u16 rsvd, u32 dirs, u32 mask + PIO_SM_SET_ENABLED, // u16 mask, u8 enable, u8 rsvd + PIO_SM_RESTART, // u16 mask + PIO_SM_CLKDIV_RESTART, // u16 mask + PIO_SM_ENABLE_SYNC, // u16 mask + PIO_SM_PUT, // u16 sm, u8 blocking, u8 rsvd, u32 data + PIO_SM_GET, // u16 sm, u8 blocking, u8 rsvd -> u32 data + PIO_SM_SET_DMACTRL, // u16 sm, u16 is_tx, u32 ctrl + + GPIO_INIT, // u16 gpio + GPIO_SET_FUNCTION, // u16 gpio, u16 fn + GPIO_SET_PULLS, // u16 gpio, u8 up, u8 down + GPIO_SET_OUTOVER, // u16 gpio, u16 value + GPIO_SET_INOVER, // u16 gpio, u16 value + GPIO_SET_OEOVER, // u16 gpio, u16 value + GPIO_SET_INPUT_ENABLED, // u16 gpio, u16 value + GPIO_SET_DRIVE_STRENGTH, // u16 gpio, u16 value + + READ_HW, // src address, len -> data bytes + WRITE_HW, // dst address, data + + PIO_SM_FIFO_STATE, // u16 sm, u8 tx -> u16 level, u8 empty, u8 full + PIO_SM_DRAIN_TX, // u16 sm + + PIO_COUNT +}; + +#endif diff --git a/drivers/misc/rp1-pio.c b/drivers/misc/rp1-pio.c new file mode 100644 index 000000000000..e1ee5016a354 --- /dev/null +++ b/drivers/misc/rp1-pio.c @@ -0,0 +1,1371 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PIO driver for RP1 + * + * Copyright (C) 2023-2024 Raspberry Pi Ltd. + * + * Parts of this driver are based on: + * - vcio.c, by Noralf Trønnes + * Copyright (C) 2010 Broadcom + * Copyright (C) 2015 Noralf Trønnes + * Copyright (C) 2021 Raspberry Pi (Trading) Ltd. + * - bcm2835_smi.c & bcm2835_smi_dev.c by Luke Wren + * Copyright (c) 2015 Raspberry Pi (Trading) Ltd. + */ + +#include <linux/cdev.h> +#include <linux/compat.h> +#include <linux/device.h> +#include <linux/dmaengine.h> +#include <linux/dma-mapping.h> +#include <linux/fs.h> +#include <linux/init.h> +#include <linux/ioctl.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/pio_rp1.h> +#include <linux/platform_device.h> +#include <linux/rp1-firmware.h> +#include <linux/semaphore.h> +#include <linux/slab.h> +#include <linux/spinlock.h> +#include <linux/uaccess.h> +#include <uapi/misc/rp1_pio_if.h> + +#include "rp1-fw-pio.h" + +#define DRIVER_NAME "rp1-pio" + +#define RP1_PIO_SMS_COUNT 4 +#define RP1_PIO_INSTR_COUNT 32 + +#define MAX_ARG_SIZE 256 + +#define RP1_PIO_FIFO_TX0 0x00 +#define RP1_PIO_FIFO_TX1 0x04 +#define RP1_PIO_FIFO_TX2 0x08 +#define RP1_PIO_FIFO_TX3 0x0c +#define RP1_PIO_FIFO_RX0 0x10 +#define RP1_PIO_FIFO_RX1 0x14 +#define RP1_PIO_FIFO_RX2 0x18 +#define RP1_PIO_FIFO_RX3 0x1c + +#define RP1_PIO_DMACTRL_DEFAULT 0x80000104 + +#define HANDLER(_n, _f) \ + [_IOC_NR(PIO_IOC_ ## _n)] = { #_n, rp1_pio_ ## _f, _IOC_SIZE(PIO_IOC_ ## _n) } + + +#define ROUND_UP(x, y) (((x) + (y) - 1) - (((x) + (y) - 1) % (y))) + +#define DMA_BOUNCE_BUFFER_SIZE 0x1000 +#define DMA_BOUNCE_BUFFER_COUNT 4 + +struct dma_xfer_state { + struct dma_info *dma; + void (*callback)(void *param); + void *callback_param; +}; + +struct dma_buf_info { + void *buf; + dma_addr_t dma_addr; + struct scatterlist sgl; +}; + +struct dma_info { + struct semaphore buf_sem; + struct dma_chan *chan; + size_t buf_size; + size_t buf_count; + unsigned int head_idx; + unsigned int tail_idx; + struct dma_buf_info bufs[DMA_BOUNCE_BUFFER_COUNT]; +}; + +struct rp1_pio_device { + struct platform_device *pdev; + struct rp1_firmware *fw; + uint16_t fw_pio_base; + uint16_t fw_pio_count; + dev_t dev_num; + struct class *dev_class; + struct cdev cdev; + phys_addr_t phys_addr; + uint32_t claimed_sms; + uint32_t claimed_dmas; + spinlock_t lock; + struct mutex instr_mutex; + struct dma_info dma_configs[RP1_PIO_SMS_COUNT][RP1_PIO_DIR_COUNT]; + uint32_t used_instrs; + uint8_t instr_refcounts[RP1_PIO_INSTR_COUNT]; + uint16_t instrs[RP1_PIO_INSTR_COUNT]; + uint client_count; +}; + +struct rp1_pio_client { + struct rp1_pio_device *pio; + uint32_t claimed_sms; + uint32_t claimed_instrs; + uint32_t claimed_dmas; + int error; +}; + +static struct rp1_pio_device *g_pio; + +static int rp1_pio_message(struct rp1_pio_device *pio, + uint16_t op, const void *data, unsigned int data_len) +{ + uint32_t rc; + int ret; + + if (op >= pio->fw_pio_count) + return -EOPNOTSUPP; + ret = rp1_firmware_message(pio->fw, pio->fw_pio_base + op, + data, data_len, + &rc, sizeof(rc)); + if (ret == 4) + ret = rc; + return ret; +} + +static int rp1_pio_message_resp(struct rp1_pio_device *pio, + uint16_t op, const void *data, unsigned int data_len, + void *resp, void __user *userbuf, unsigned int resp_len) +{ + uint32_t resp_buf[1 + 32]; + int ret; + + if (op >= pio->fw_pio_count) + return -EOPNOTSUPP; + if (resp_len + 4 >= sizeof(resp_buf)) + return -EINVAL; + if (!resp && !userbuf) + return -EINVAL; + ret = rp1_firmware_message(pio->fw, pio->fw_pio_base + op, + data, data_len, + resp_buf, resp_len + 4); + if (ret >= 4 && !resp_buf[0]) { + ret -= 4; + if (resp) + memcpy(resp, &resp_buf[1], ret); + else if (copy_to_user(userbuf, &resp_buf[1], ret)) + ret = -EFAULT; + } else if (ret >= 0) { + ret = -EIO; + } + return ret; +} + +static int rp1_pio_read_hw(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_device *pio = client->pio; + struct rp1_access_hw_args *args = param; + + return rp1_pio_message_resp(pio, READ_HW, + args, 8, NULL, args->data, args->len); +} + +static int rp1_pio_write_hw(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_device *pio = client->pio; + struct rp1_access_hw_args *args = param; + uint32_t write_buf[32 + 1]; + int len; + + len = min(args->len, sizeof(write_buf) - 4); + write_buf[0] = args->addr; + if (copy_from_user(&write_buf[1], args->data, len)) + return -EFAULT; + return rp1_firmware_message(pio->fw, pio->fw_pio_base + WRITE_HW, + write_buf, 4 + len, NULL, 0); +} + +static int rp1_pio_find_program(struct rp1_pio_device *pio, + struct rp1_pio_add_program_args *prog) +{ + uint start, end, prog_size; + uint32_t used_mask; + uint i; + + start = (prog->origin != RP1_PIO_ORIGIN_ANY) ? prog->origin : 0; + end = (prog->origin != RP1_PIO_ORIGIN_ANY) ? prog->origin : + (RP1_PIO_INSTRUCTION_COUNT - prog->num_instrs); + prog_size = sizeof(prog->instrs[0]) * prog->num_instrs; + used_mask = (uint32_t)(~0) >> (32 - prog->num_instrs); + + /* Find the best match */ + for (i = start; i <= end; i++) { + uint32_t mask = used_mask << i; + + if ((pio->used_instrs & mask) != mask) + continue; + if (!memcmp(pio->instrs + i, prog->instrs, prog_size)) + return i; + } + + return -1; +} + +int rp1_pio_can_add_program(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_add_program_args *args = param; + struct rp1_pio_device *pio = client->pio; + int offset; + + if (args->num_instrs > RP1_PIO_INSTR_COUNT || + ((args->origin != RP1_PIO_ORIGIN_ANY) && + (args->origin >= RP1_PIO_INSTR_COUNT || + ((args->origin + args->num_instrs) > RP1_PIO_INSTR_COUNT)))) + return -EINVAL; + + mutex_lock(&pio->instr_mutex); + offset = rp1_pio_find_program(pio, args); + mutex_unlock(&pio->instr_mutex); + if (offset >= 0) + return offset; + + /* Don't send the instructions, just the header */ + return rp1_pio_message(pio, PIO_CAN_ADD_PROGRAM, args, + offsetof(struct rp1_pio_add_program_args, instrs)); +} +EXPORT_SYMBOL_GPL(rp1_pio_can_add_program); + +int rp1_pio_add_program(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_add_program_args *args = param; + struct rp1_pio_device *pio = client->pio; + int offset; + uint i; + + if (args->num_instrs > RP1_PIO_INSTR_COUNT || + ((args->origin != RP1_PIO_ORIGIN_ANY) && + (args->origin >= RP1_PIO_INSTR_COUNT || + ((args->origin + args->num_instrs) > RP1_PIO_INSTR_COUNT)))) + return -EINVAL; + + mutex_lock(&pio->instr_mutex); + offset = rp1_pio_find_program(pio, args); + if (offset < 0) + offset = rp1_pio_message(client->pio, PIO_ADD_PROGRAM, args, sizeof(*args)); + + if (offset >= 0) { + uint32_t used_mask; + uint prog_size; + + used_mask = ((uint32_t)(~0) >> (-args->num_instrs & 0x1f)) << offset; + prog_size = sizeof(args->instrs[0]) * args->num_instrs; + + if ((pio->used_instrs & used_mask) != used_mask) { + pio->used_instrs |= used_mask; + memcpy(pio->instrs + offset, args->instrs, prog_size); + } + client->claimed_instrs |= used_mask; + for (i = 0; i < args->num_instrs; i++) + pio->instr_refcounts[offset + i]++; + } + mutex_unlock(&pio->instr_mutex); + return offset; +} +EXPORT_SYMBOL_GPL(rp1_pio_add_program); + +static void rp1_pio_remove_instrs(struct rp1_pio_device *pio, uint32_t mask) +{ + struct rp1_pio_remove_program_args args; + uint i; + + mutex_lock(&pio->instr_mutex); + args.num_instrs = 0; + for (i = 0; ; i++, mask >>= 1) { + if ((mask & 1) && pio->instr_refcounts[i] && !--pio->instr_refcounts[i]) { + pio->used_instrs &= ~(1 << i); + args.num_instrs++; + } else if (args.num_instrs) { + args.origin = i - args.num_instrs; + rp1_pio_message(pio, PIO_REMOVE_PROGRAM, &args, sizeof(args)); + args.num_instrs = 0; + } + if (!mask) + break; + } + mutex_unlock(&pio->instr_mutex); +} + +int rp1_pio_remove_program(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_remove_program_args *args = param; + uint32_t used_mask; + int ret = -ENOENT; + + if (args->num_instrs > RP1_PIO_INSTR_COUNT || + args->origin >= RP1_PIO_INSTR_COUNT || + (args->origin + args->num_instrs) > RP1_PIO_INSTR_COUNT) + return -EINVAL; + + used_mask = ((uint32_t)(~0) >> (32 - args->num_instrs)) << args->origin; + if ((client->claimed_instrs & used_mask) == used_mask) { + client->claimed_instrs &= ~used_mask; + rp1_pio_remove_instrs(client->pio, used_mask); + ret = 0; + } + return ret; +} +EXPORT_SYMBOL_GPL(rp1_pio_remove_program); + +int rp1_pio_clear_instr_mem(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_device *pio = client->pio; + + mutex_lock(&pio->instr_mutex); + (void)rp1_pio_message(client->pio, PIO_CLEAR_INSTR_MEM, NULL, 0); + memset(pio->instr_refcounts, 0, sizeof(pio->instr_refcounts)); + pio->used_instrs = 0; + client->claimed_instrs = 0; + mutex_unlock(&pio->instr_mutex); + return 0; +} +EXPORT_SYMBOL_GPL(rp1_pio_clear_instr_mem); + +int rp1_pio_sm_claim(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_claim_args *args = param; + struct rp1_pio_device *pio = client->pio; + int ret; + + mutex_lock(&pio->instr_mutex); + ret = rp1_pio_message(client->pio, PIO_SM_CLAIM, args, sizeof(*args)); + if (ret >= 0) { + if (args->mask) + client->claimed_sms |= args->mask; + else + client->claimed_sms |= (1 << ret); + pio->claimed_sms |= client->claimed_sms; + } + mutex_unlock(&pio->instr_mutex); + return ret; +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_claim); + +int rp1_pio_sm_unclaim(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_claim_args *args = param; + struct rp1_pio_device *pio = client->pio; + + mutex_lock(&pio->instr_mutex); + (void)rp1_pio_message(client->pio, PIO_SM_UNCLAIM, args, sizeof(*args)); + client->claimed_sms &= ~args->mask; + pio->claimed_sms &= ~args->mask; + mutex_unlock(&pio->instr_mutex); + return 0; +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_unclaim); + +int rp1_pio_sm_is_claimed(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_claim_args *args = param; + + return rp1_pio_message(client->pio, PIO_SM_IS_CLAIMED, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_is_claimed); + +int rp1_pio_sm_init(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_init_args *args = param; + + return rp1_pio_message(client->pio, PIO_SM_INIT, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_init); + +int rp1_pio_sm_set_config(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_set_config_args *args = param; + + return rp1_pio_message(client->pio, PIO_SM_SET_CONFIG, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_set_config); + +int rp1_pio_sm_exec(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_exec_args *args = param; + + return rp1_pio_message(client->pio, PIO_SM_EXEC, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_exec); + +int rp1_pio_sm_clear_fifos(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_clear_fifos_args *args = param; + + return rp1_pio_message(client->pio, PIO_SM_CLEAR_FIFOS, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_clear_fifos); + +int rp1_pio_sm_set_clkdiv(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_set_clkdiv_args *args = param; + + return rp1_pio_message(client->pio, PIO_SM_SET_CLKDIV, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_set_clkdiv); + +int rp1_pio_sm_set_pins(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_set_pins_args *args = param; + + return rp1_pio_message(client->pio, PIO_SM_SET_PINS, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_set_pins); + +int rp1_pio_sm_set_pindirs(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_set_pindirs_args *args = param; + + return rp1_pio_message(client->pio, PIO_SM_SET_PINDIRS, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_set_pindirs); + +int rp1_pio_sm_set_enabled(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_set_enabled_args *args = param; + + return rp1_pio_message(client->pio, PIO_SM_SET_ENABLED, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_set_enabled); + +int rp1_pio_sm_restart(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_restart_args *args = param; + + return rp1_pio_message(client->pio, PIO_SM_RESTART, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_restart); + +int rp1_pio_sm_clkdiv_restart(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_restart_args *args = param; + + return rp1_pio_message(client->pio, PIO_SM_CLKDIV_RESTART, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_clkdiv_restart); + +int rp1_pio_sm_enable_sync(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_enable_sync_args *args = param; + + return rp1_pio_message(client->pio, PIO_SM_ENABLE_SYNC, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_enable_sync); + +int rp1_pio_sm_put(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_put_args *args = param; + + return rp1_pio_message(client->pio, PIO_SM_PUT, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_put); + +int rp1_pio_sm_get(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_get_args *args = param; + int ret; + + ret = rp1_pio_message_resp(client->pio, PIO_SM_GET, args, sizeof(*args), + &args->data, NULL, sizeof(args->data)); + if (ret >= 0) + return offsetof(struct rp1_pio_sm_get_args, data) + ret; + return ret; +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_get); + +int rp1_pio_sm_set_dmactrl(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_set_dmactrl_args *args = param; + + return rp1_pio_message(client->pio, PIO_SM_SET_DMACTRL, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_set_dmactrl); + +int rp1_pio_sm_fifo_state(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_fifo_state_args *args = param; + const int level_offset = offsetof(struct rp1_pio_sm_fifo_state_args, level); + int ret; + + ret = rp1_pio_message_resp(client->pio, PIO_SM_FIFO_STATE, args, sizeof(*args), + &args->level, NULL, sizeof(*args) - level_offset); + if (ret >= 0) + return level_offset + ret; + return ret; +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_fifo_state); + +int rp1_pio_sm_drain_tx(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_clear_fifos_args *args = param; + + return rp1_pio_message(client->pio, PIO_SM_DRAIN_TX, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_drain_tx); + +int rp1_pio_gpio_init(struct rp1_pio_client *client, void *param) +{ + struct rp1_gpio_init_args *args = param; + + return rp1_pio_message(client->pio, GPIO_INIT, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_gpio_init); + +int rp1_pio_gpio_set_function(struct rp1_pio_client *client, void *param) +{ + struct rp1_gpio_set_function_args *args = param; + + return rp1_pio_message(client->pio, GPIO_SET_FUNCTION, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_gpio_set_function); + +int rp1_pio_gpio_set_pulls(struct rp1_pio_client *client, void *param) +{ + struct rp1_gpio_set_pulls_args *args = param; + + return rp1_pio_message(client->pio, GPIO_SET_PULLS, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_gpio_set_pulls); + +int rp1_pio_gpio_set_outover(struct rp1_pio_client *client, void *param) +{ + struct rp1_gpio_set_args *args = param; + + return rp1_pio_message(client->pio, GPIO_SET_OUTOVER, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_gpio_set_outover); + +int rp1_pio_gpio_set_inover(struct rp1_pio_client *client, void *param) +{ + struct rp1_gpio_set_args *args = param; + + return rp1_pio_message(client->pio, GPIO_SET_INOVER, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_gpio_set_inover); + +int rp1_pio_gpio_set_oeover(struct rp1_pio_client *client, void *param) +{ + struct rp1_gpio_set_args *args = param; + + return rp1_pio_message(client->pio, GPIO_SET_OEOVER, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_gpio_set_oeover); + +int rp1_pio_gpio_set_input_enabled(struct rp1_pio_client *client, void *param) +{ + struct rp1_gpio_set_args *args = param; + + return rp1_pio_message(client->pio, GPIO_SET_INPUT_ENABLED, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_gpio_set_input_enabled); + +int rp1_pio_gpio_set_drive_strength(struct rp1_pio_client *client, void *param) +{ + struct rp1_gpio_set_args *args = param; + + return rp1_pio_message(client->pio, GPIO_SET_DRIVE_STRENGTH, args, sizeof(*args)); +} +EXPORT_SYMBOL_GPL(rp1_pio_gpio_set_drive_strength); + +static void rp1_pio_sm_dma_callback(void *param) +{ + struct dma_info *dma = param; + + up(&dma->buf_sem); +} + +static void rp1_pio_sm_kernel_dma_callback(void *param) +{ + struct dma_xfer_state *dxs = param; + + dxs->dma->tail_idx++; + up(&dxs->dma->buf_sem); + + dxs->callback(dxs->callback_param); + + kfree(dxs); +} + +static void rp1_pio_sm_dma_free(struct device *dev, struct dma_info *dma) +{ + dmaengine_terminate_all(dma->chan); + while (dma->buf_count > 0) { + dma->buf_count--; + dma_free_coherent(dev, ROUND_UP(dma->buf_size, PAGE_SIZE), + dma->bufs[dma->buf_count].buf, + dma->bufs[dma->buf_count].dma_addr); + } + + dma_release_channel(dma->chan); +} + +static int rp1_pio_sm_config_xfer_internal(struct rp1_pio_client *client, uint sm, uint dir, + uint buf_size, uint buf_count) +{ + struct rp1_pio_sm_set_dmactrl_args set_dmactrl_args; + struct rp1_pio_device *pio = client->pio; + struct platform_device *pdev = pio->pdev; + struct device *dev = &pdev->dev; + struct dma_slave_config config = {}; + phys_addr_t fifo_addr; + struct dma_info *dma; + uint32_t dma_mask; + char chan_name[4]; + int ret = 0; + + if (sm >= RP1_PIO_SMS_COUNT || dir >= RP1_PIO_DIR_COUNT) + return -EINVAL; + if ((buf_count || buf_size) && + (!buf_size || (buf_size & 3) || + !buf_count || buf_count > DMA_BOUNCE_BUFFER_COUNT)) + return -EINVAL; + + dma_mask = 1 << (sm * 2 + dir); + + dma = &pio->dma_configs[sm][dir]; + + spin_lock(&pio->lock); + if (pio->claimed_dmas & dma_mask) + rp1_pio_sm_dma_free(dev, dma); + pio->claimed_dmas |= dma_mask; + client->claimed_dmas |= dma_mask; + spin_unlock(&pio->lock); + + dma->buf_size = buf_size; + /* Round up the allocations */ + buf_size = ROUND_UP(buf_size, PAGE_SIZE); + sema_init(&dma->buf_sem, 0); + + /* Allocate and configure a DMA channel */ + /* Careful - each SM FIFO has its own DREQ value */ + chan_name[0] = (dir == RP1_PIO_DIR_TO_SM) ? 't' : 'r'; + chan_name[1] = 'x'; + chan_name[2] = '0' + sm; + chan_name[3] = '\0'; + + dma->chan = dma_request_chan(dev, chan_name); + if (IS_ERR(dma->chan)) + return PTR_ERR(dma->chan); + + /* Alloc and map bounce buffers */ + for (dma->buf_count = 0; dma->buf_count < buf_count; dma->buf_count++) { + struct dma_buf_info *dbi = &dma->bufs[dma->buf_count]; + + dbi->buf = dma_alloc_coherent(dma->chan->device->dev, buf_size, + &dbi->dma_addr, GFP_KERNEL); + if (!dbi->buf) { + ret = -ENOMEM; + goto err_dma_free; + } + sg_init_table(&dbi->sgl, 1); + sg_dma_address(&dbi->sgl) = dbi->dma_addr; + } + + fifo_addr = pio->phys_addr; + fifo_addr += sm * (RP1_PIO_FIFO_TX1 - RP1_PIO_FIFO_TX0); + fifo_addr += (dir == RP1_PIO_DIR_TO_SM) ? RP1_PIO_FIFO_TX0 : RP1_PIO_FIFO_RX0; + + config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + config.src_addr = fifo_addr; + config.dst_addr = fifo_addr; + config.direction = (dir == RP1_PIO_DIR_TO_SM) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; + + ret = dmaengine_slave_config(dma->chan, &config); + if (ret) + goto err_dma_free; + + set_dmactrl_args.sm = sm; + set_dmactrl_args.is_tx = (dir == RP1_PIO_DIR_TO_SM); + set_dmactrl_args.ctrl = RP1_PIO_DMACTRL_DEFAULT; + if (dir == RP1_PIO_DIR_FROM_SM) + set_dmactrl_args.ctrl = (RP1_PIO_DMACTRL_DEFAULT & ~0x1f) | 1; + + ret = rp1_pio_sm_set_dmactrl(client, &set_dmactrl_args); + if (ret) + goto err_dma_free; + + return 0; + +err_dma_free: + rp1_pio_sm_dma_free(dev, dma); + + spin_lock(&pio->lock); + client->claimed_dmas &= ~dma_mask; + pio->claimed_dmas &= ~dma_mask; + spin_unlock(&pio->lock); + + return ret; +} + +static int rp1_pio_sm_config_xfer_user(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_config_xfer_args *args = param; + + return rp1_pio_sm_config_xfer_internal(client, args->sm, args->dir, + args->buf_size, args->buf_count); +} + +static int rp1_pio_sm_tx_user(struct rp1_pio_device *pio, struct dma_info *dma, + const void __user *userbuf, size_t bytes) +{ + struct platform_device *pdev = pio->pdev; + struct dma_async_tx_descriptor *desc; + struct device *dev = &pdev->dev; + int ret = 0; + + /* Clean the slate - we're running synchronously */ + dma->head_idx = 0; + dma->tail_idx = 0; + + while (bytes > 0) { + size_t copy_bytes = min(bytes, dma->buf_size); + struct dma_buf_info *dbi; + + /* grab the next free buffer, waiting if they're all full */ + if (dma->head_idx - dma->tail_idx == dma->buf_count) { + if (down_timeout(&dma->buf_sem, + msecs_to_jiffies(1000))) { + dev_err(dev, "DMA bounce timed out\n"); + break; + } + dma->tail_idx++; + } + + dbi = &dma->bufs[dma->head_idx % dma->buf_count]; + + sg_dma_len(&dbi->sgl) = copy_bytes; + + ret = copy_from_user(dbi->buf, userbuf, copy_bytes); + if (ret < 0) + break; + + userbuf += copy_bytes; + + desc = dmaengine_prep_slave_sg(dma->chan, &dbi->sgl, 1, + DMA_MEM_TO_DEV, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK | + DMA_PREP_FENCE); + if (!desc) { + dev_err(dev, "DMA preparation failed\n"); + ret = -EIO; + break; + } + + desc->callback = rp1_pio_sm_dma_callback; + desc->callback_param = dma; + + /* Submit the buffer - the callback will kick the semaphore */ + ret = dmaengine_submit(desc); + if (ret < 0) + break; + ret = 0; + + dma_async_issue_pending(dma->chan); + + dma->head_idx++; + bytes -= copy_bytes; + } + + /* Block for completion */ + while (dma->tail_idx != dma->head_idx) { + if (down_timeout(&dma->buf_sem, msecs_to_jiffies(1000))) { + dev_err(dev, "DMA wait timed out\n"); + ret = -ETIMEDOUT; + break; + } + dma->tail_idx++; + } + + return ret; +} + +static int rp1_pio_sm_rx_user(struct rp1_pio_device *pio, struct dma_info *dma, + void __user *userbuf, size_t bytes) +{ + struct platform_device *pdev = pio->pdev; + struct dma_async_tx_descriptor *desc; + struct device *dev = &pdev->dev; + int ret = 0; + + /* Clean the slate - we're running synchronously */ + dma->head_idx = 0; + dma->tail_idx = 0; + + while (bytes || dma->tail_idx != dma->head_idx) { + size_t copy_bytes = min(bytes, dma->buf_size); + struct dma_buf_info *dbi; + + /* + * wait for the next RX to complete if all the buffers are + * outstanding or we're finishing up. + */ + if (!bytes || dma->head_idx - dma->tail_idx == dma->buf_count) { + if (down_timeout(&dma->buf_sem, + msecs_to_jiffies(1000))) { + dev_err(dev, "DMA wait timed out\n"); + ret = -ETIMEDOUT; + break; + } + + dbi = &dma->bufs[dma->tail_idx++ % dma->buf_count]; + ret = copy_to_user(userbuf, dbi->buf, sg_dma_len(&dbi->sgl)); + if (ret < 0) + break; + userbuf += sg_dma_len(&dbi->sgl); + + if (!bytes) + continue; + } + + dbi = &dma->bufs[dma->head_idx % dma->buf_count]; + sg_dma_len(&dbi->sgl) = copy_bytes; + desc = dmaengine_prep_slave_sg(dma->chan, &dbi->sgl, 1, + DMA_DEV_TO_MEM, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK | + DMA_PREP_FENCE); + if (!desc) { + dev_err(dev, "DMA preparation failed\n"); + ret = -EIO; + break; + } + + desc->callback = rp1_pio_sm_dma_callback; + desc->callback_param = dma; + + /* Submit the buffer - the callback will kick the semaphore */ + ret = dmaengine_submit(desc); + if (ret < 0) + break; + + dma_async_issue_pending(dma->chan); + + dma->head_idx++; + bytes -= copy_bytes; + } + + return ret; +} + +static int rp1_pio_sm_xfer_data32_user(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_xfer_data32_args *args = param; + struct rp1_pio_device *pio = client->pio; + struct dma_info *dma; + + if (args->sm >= RP1_PIO_SMS_COUNT || args->dir >= RP1_PIO_DIR_COUNT || + !args->data_bytes || !args->data) + return -EINVAL; + + dma = &pio->dma_configs[args->sm][args->dir]; + + if (args->dir == RP1_PIO_DIR_TO_SM) + return rp1_pio_sm_tx_user(pio, dma, args->data, args->data_bytes); + else + return rp1_pio_sm_rx_user(pio, dma, args->data, args->data_bytes); +} + +static int rp1_pio_sm_xfer_data_user(struct rp1_pio_client *client, void *param) +{ + struct rp1_pio_sm_xfer_data_args *args = param; + struct rp1_pio_sm_xfer_data32_args args32; + + args32.sm = args->sm; + args32.dir = args->dir; + args32.data_bytes = args->data_bytes; + args32.data = args->data; + + return rp1_pio_sm_xfer_data32_user(client, &args32); +} + +int rp1_pio_sm_config_xfer(struct rp1_pio_client *client, uint sm, uint dir, + uint buf_size, uint buf_count) +{ + return rp1_pio_sm_config_xfer_internal(client, sm, dir, buf_size, buf_count); +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_config_xfer); + +int rp1_pio_sm_xfer_data(struct rp1_pio_client *client, uint sm, uint dir, + uint data_bytes, void *data, dma_addr_t dma_addr, + void (*callback)(void *param), void *param) +{ + struct rp1_pio_device *pio = client->pio; + struct platform_device *pdev = pio->pdev; + struct dma_async_tx_descriptor *desc; + struct dma_xfer_state *dxs = NULL; + struct device *dev = &pdev->dev; + struct dma_buf_info *dbi = NULL; + struct scatterlist sg; + struct dma_info *dma; + int ret = 0; + + if (sm >= RP1_PIO_SMS_COUNT || dir >= RP1_PIO_DIR_COUNT) + return -EINVAL; + + dma = &pio->dma_configs[sm][dir]; + + if (!dma_addr) { + dxs = kmalloc(sizeof(*dxs), GFP_KERNEL); + dxs->dma = dma; + dxs->callback = callback; + dxs->callback_param = param; + callback = rp1_pio_sm_kernel_dma_callback; + param = dxs; + + if (!dma->buf_count || data_bytes > dma->buf_size) + return -EINVAL; + + /* Grab a dma buffer */ + if (dma->head_idx - dma->tail_idx == dma->buf_count) { + if (down_timeout(&dma->buf_sem, msecs_to_jiffies(1000))) { + dev_err(dev, "DMA wait timed out\n"); + return -ETIMEDOUT; + } + } + + dbi = &dma->bufs[dma->head_idx % dma->buf_count]; + dma_addr = dbi->dma_addr; + + if (dir == PIO_DIR_TO_SM) + memcpy(dbi->buf, data, data_bytes); + } + + sg_init_table(&sg, 1); + sg_dma_address(&sg) = dma_addr; + sg_dma_len(&sg) = data_bytes; + + desc = dmaengine_prep_slave_sg(dma->chan, &sg, 1, + (dir == PIO_DIR_TO_SM) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK | + DMA_PREP_FENCE); + if (!desc) { + dev_err(dev, "DMA preparation failed\n"); + return -EIO; + } + + desc->callback = callback; + desc->callback_param = param; + + ret = dmaengine_submit(desc); + if (ret < 0) { + dev_err(dev, "dmaengine_submit failed (%d)\n", ret); + return ret; + } + + dma_async_issue_pending(dma->chan); + + return 0; +} +EXPORT_SYMBOL_GPL(rp1_pio_sm_xfer_data); + +struct handler_info { + const char *name; + int (*func)(struct rp1_pio_client *client, void *param); + int argsize; +} ioctl_handlers[] = { + HANDLER(SM_CONFIG_XFER, sm_config_xfer_user), + HANDLER(SM_XFER_DATA, sm_xfer_data_user), + HANDLER(SM_XFER_DATA32, sm_xfer_data32_user), + + HANDLER(CAN_ADD_PROGRAM, can_add_program), + HANDLER(ADD_PROGRAM, add_program), + HANDLER(REMOVE_PROGRAM, remove_program), + HANDLER(CLEAR_INSTR_MEM, clear_instr_mem), + + HANDLER(SM_CLAIM, sm_claim), + HANDLER(SM_UNCLAIM, sm_unclaim), + HANDLER(SM_IS_CLAIMED, sm_is_claimed), + + HANDLER(SM_INIT, sm_init), + HANDLER(SM_SET_CONFIG, sm_set_config), + HANDLER(SM_EXEC, sm_exec), + HANDLER(SM_CLEAR_FIFOS, sm_clear_fifos), + HANDLER(SM_SET_CLKDIV, sm_set_clkdiv), + HANDLER(SM_SET_PINS, sm_set_pins), + HANDLER(SM_SET_PINDIRS, sm_set_pindirs), + HANDLER(SM_SET_ENABLED, sm_set_enabled), + HANDLER(SM_RESTART, sm_restart), + HANDLER(SM_CLKDIV_RESTART, sm_clkdiv_restart), + HANDLER(SM_ENABLE_SYNC, sm_enable_sync), + HANDLER(SM_PUT, sm_put), + HANDLER(SM_GET, sm_get), + HANDLER(SM_SET_DMACTRL, sm_set_dmactrl), + HANDLER(SM_FIFO_STATE, sm_fifo_state), + HANDLER(SM_DRAIN_TX, sm_drain_tx), + + HANDLER(GPIO_INIT, gpio_init), + HANDLER(GPIO_SET_FUNCTION, gpio_set_function), + HANDLER(GPIO_SET_PULLS, gpio_set_pulls), + HANDLER(GPIO_SET_OUTOVER, gpio_set_outover), + HANDLER(GPIO_SET_INOVER, gpio_set_inover), + HANDLER(GPIO_SET_OEOVER, gpio_set_oeover), + HANDLER(GPIO_SET_INPUT_ENABLED, gpio_set_input_enabled), + HANDLER(GPIO_SET_DRIVE_STRENGTH, gpio_set_drive_strength), + + HANDLER(READ_HW, read_hw), + HANDLER(WRITE_HW, write_hw), +}; + +struct rp1_pio_client *rp1_pio_open(void) +{ + struct rp1_pio_client *client; + + if (!g_pio) + return ERR_PTR(-ENOENT); + + client = kzalloc(sizeof(*client), GFP_KERNEL); + if (!client) + return ERR_PTR(-ENOMEM); + + client->pio = g_pio; + + return client; +} +EXPORT_SYMBOL_GPL(rp1_pio_open); + +void rp1_pio_close(struct rp1_pio_client *client) +{ + struct rp1_pio_device *pio = client->pio; + uint claimed_dmas = client->claimed_dmas; + int i; + + /* Free any allocated resources */ + + for (i = 0; claimed_dmas; i++) { + uint mask = (1 << i); + + if (claimed_dmas & mask) { + struct dma_info *dma = &pio->dma_configs[i >> 1][i & 1]; + + claimed_dmas &= ~mask; + rp1_pio_sm_dma_free(&pio->pdev->dev, dma); + } + } + + spin_lock(&pio->lock); + pio->claimed_dmas &= ~client->claimed_dmas; + spin_unlock(&pio->lock); + + if (client->claimed_sms) { + struct rp1_pio_sm_set_enabled_args se_args = { + .mask = client->claimed_sms, .enable = 0 + }; + struct rp1_pio_sm_claim_args uc_args = { + .mask = client->claimed_sms + }; + + rp1_pio_sm_set_enabled(client, &se_args); + rp1_pio_sm_unclaim(client, &uc_args); + } + + if (client->claimed_instrs) + rp1_pio_remove_instrs(pio, client->claimed_instrs); + + /* Reinitialise the SM? */ + + kfree(client); +} +EXPORT_SYMBOL_GPL(rp1_pio_close); + +void rp1_pio_set_error(struct rp1_pio_client *client, int err) +{ + client->error = err; +} +EXPORT_SYMBOL_GPL(rp1_pio_set_error); + +int rp1_pio_get_error(const struct rp1_pio_client *client) +{ + return client->error; +} +EXPORT_SYMBOL_GPL(rp1_pio_get_error); + +void rp1_pio_clear_error(struct rp1_pio_client *client) +{ + client->error = 0; +} +EXPORT_SYMBOL_GPL(rp1_pio_clear_error); + +static int rp1_pio_file_open(struct inode *inode, struct file *filp) +{ + struct rp1_pio_client *client; + + client = rp1_pio_open(); + if (IS_ERR(client)) + return PTR_ERR(client); + + filp->private_data = client; + + return 0; +} + +static int rp1_pio_file_release(struct inode *inode, struct file *filp) +{ + struct rp1_pio_client *client = filp->private_data; + + rp1_pio_close(client); + + return 0; +} + +static long rp1_pio_ioctl(struct file *filp, unsigned int ioctl_num, + unsigned long ioctl_param) +{ + struct rp1_pio_client *client = filp->private_data; + struct device *dev = &client->pio->pdev->dev; + void __user *argp = (void __user *)ioctl_param; + int nr = _IOC_NR(ioctl_num); + int sz = _IOC_SIZE(ioctl_num); + struct handler_info *hdlr = &ioctl_handlers[nr]; + uint32_t argbuf[MAX_ARG_SIZE/sizeof(uint32_t)]; + int ret; + + if (nr >= ARRAY_SIZE(ioctl_handlers) || !hdlr->func) { + dev_err(dev, "unknown ioctl: %x\n", ioctl_num); + return -EOPNOTSUPP; + } + + if (sz != hdlr->argsize) { + dev_err(dev, "wrong %s argsize (expected %d, got %d)\n", + hdlr->name, hdlr->argsize, sz); + return -EINVAL; + } + + if (copy_from_user(argbuf, argp, sz)) + return -EFAULT; + + ret = (hdlr->func)(client, argbuf); + dev_dbg(dev, "%s: %s -> %d\n", __func__, hdlr->name, ret); + if (ret > 0) { + if (copy_to_user(argp, argbuf, ret)) + ret = -EFAULT; + } + + return ret; +} + +#ifdef CONFIG_COMPAT + +struct rp1_pio_sm_xfer_data_args_compat { + uint16_t sm; + uint16_t dir; + uint16_t data_bytes; + compat_uptr_t data; +}; + +struct rp1_pio_sm_xfer_data32_args_compat { + uint16_t sm; + uint16_t dir; + uint32_t data_bytes; + compat_uptr_t data; +}; + +struct rp1_access_hw_args_compat { + uint32_t addr; + uint32_t len; + compat_uptr_t data; +}; + +#define PIO_IOC_SM_XFER_DATA_COMPAT \ + _IOW(PIO_IOC_MAGIC, 1, struct rp1_pio_sm_xfer_data_args_compat) +#define PIO_IOC_SM_XFER_DATA32_COMPAT \ + _IOW(PIO_IOC_MAGIC, 2, struct rp1_pio_sm_xfer_data32_args_compat) +#define PIO_IOC_READ_HW_COMPAT _IOW(PIO_IOC_MAGIC, 8, struct rp1_access_hw_args_compat) +#define PIO_IOC_WRITE_HW_COMPAT _IOW(PIO_IOC_MAGIC, 9, struct rp1_access_hw_args_compat) + +static long rp1_pio_compat_ioctl(struct file *filp, unsigned int ioctl_num, + unsigned long ioctl_param) +{ + struct rp1_pio_client *client = filp->private_data; + + switch (ioctl_num) { + case PIO_IOC_SM_XFER_DATA_COMPAT: + { + struct rp1_pio_sm_xfer_data_args_compat compat_param; + struct rp1_pio_sm_xfer_data_args param; + + if (copy_from_user(&compat_param, compat_ptr(ioctl_param), sizeof(compat_param))) + return -EFAULT; + param.sm = compat_param.sm; + param.dir = compat_param.dir; + param.data_bytes = compat_param.data_bytes; + param.data = compat_ptr(compat_param.data); + return rp1_pio_sm_xfer_data_user(client, ¶m); + } + case PIO_IOC_SM_XFER_DATA32_COMPAT: + { + struct rp1_pio_sm_xfer_data32_args_compat compat_param; + struct rp1_pio_sm_xfer_data32_args param; + + if (copy_from_user(&compat_param, compat_ptr(ioctl_param), sizeof(compat_param))) + return -EFAULT; + param.sm = compat_param.sm; + param.dir = compat_param.dir; + param.data_bytes = compat_param.data_bytes; + param.data = compat_ptr(compat_param.data); + return rp1_pio_sm_xfer_data32_user(client, ¶m); + } + + case PIO_IOC_READ_HW_COMPAT: + case PIO_IOC_WRITE_HW_COMPAT: + { + struct rp1_access_hw_args_compat compat_param; + struct rp1_access_hw_args param; + + if (copy_from_user(&compat_param, compat_ptr(ioctl_param), sizeof(compat_param))) + return -EFAULT; + param.addr = compat_param.addr; + param.len = compat_param.len; + param.data = compat_ptr(compat_param.data); + if (ioctl_num == PIO_IOC_READ_HW_COMPAT) + return rp1_pio_read_hw(client, ¶m); + else + return rp1_pio_write_hw(client, ¶m); + } + default: + return rp1_pio_ioctl(filp, ioctl_num, ioctl_param); + } +} +#else +#define rp1_pio_compat_ioctl NULL +#endif + +const struct file_operations rp1_pio_fops = { + .owner = THIS_MODULE, + .open = rp1_pio_file_open, + .release = rp1_pio_file_release, + .unlocked_ioctl = rp1_pio_ioctl, + .compat_ioctl = rp1_pio_compat_ioctl, +}; + +static int rp1_pio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *ioresource; + struct rp1_pio_device *pio; + struct rp1_firmware *fw; + uint32_t op_count = 0; + uint32_t op_base = 0; + struct device *cdev; + char dev_name[16]; + void *p; + int ret; + int i; + + /* Run-time check for a build-time misconfiguration */ + for (i = 0; i < ARRAY_SIZE(ioctl_handlers); i++) { + struct handler_info *hdlr = &ioctl_handlers[i]; + + if (WARN_ON(hdlr->argsize > MAX_ARG_SIZE)) + return -EINVAL; + } + + pdev->id = of_alias_get_id(pdev->dev.of_node, "pio"); + if (pdev->id < 0) + return dev_err_probe(dev, pdev->id, "alias is missing\n"); + + fw = devm_rp1_firmware_get(dev, dev->of_node); + if (IS_ERR_OR_NULL(fw)) + return dev_err_probe(dev, -ENOENT, "failed to contact RP1 firmware\n"); + ret = rp1_firmware_get_feature(fw, FOURCC_PIO, &op_base, &op_count); + if (ret < 0) + return ret; + + pio = devm_kzalloc(&pdev->dev, sizeof(*pio), GFP_KERNEL); + if (!pio) + return -ENOMEM; + + platform_set_drvdata(pdev, pio); + pio->fw_pio_base = op_base; + pio->fw_pio_count = op_count; + pio->pdev = pdev; + pio->fw = fw; + spin_lock_init(&pio->lock); + mutex_init(&pio->instr_mutex); + + p = devm_platform_get_and_ioremap_resource(pdev, 0, &ioresource); + if (IS_ERR(p)) + return PTR_ERR(p); + + pio->phys_addr = ioresource->start; + + ret = alloc_chrdev_region(&pio->dev_num, 0, 1, DRIVER_NAME); + if (ret < 0) { + dev_err(dev, "alloc_chrdev_region failed (rc=%d)\n", ret); + goto out_err; + } + + pio->dev_class = class_create(DRIVER_NAME); + if (IS_ERR(pio->dev_class)) { + ret = PTR_ERR(pio->dev_class); + dev_err(dev, "class_create failed (err %d)\n", ret); + goto out_unregister; + } + + cdev_init(&pio->cdev, &rp1_pio_fops); + ret = cdev_add(&pio->cdev, pio->dev_num, 1); + if (ret) { + dev_err(dev, "cdev_add failed (err %d)\n", ret); + goto out_class_destroy; + } + + sprintf(dev_name, "pio%d", pdev->id); + cdev = device_create(pio->dev_class, NULL, pio->dev_num, NULL, dev_name); + if (IS_ERR(cdev)) { + ret = PTR_ERR(cdev); + dev_err(dev, "%s: device_create failed (err %d)\n", __func__, ret); + goto out_cdev_del; + } + + g_pio = pio; + + dev_info(dev, "Created instance as %s\n", dev_name); + return 0; + +out_cdev_del: + cdev_del(&pio->cdev); + +out_class_destroy: + class_destroy(pio->dev_class); + +out_unregister: + unregister_chrdev_region(pio->dev_num, 1); + +out_err: + return ret; +} + +static void rp1_pio_remove(struct platform_device *pdev) +{ + struct rp1_pio_device *pio = platform_get_drvdata(pdev); + + /* There should be no clients */ + + if (g_pio == pio) + g_pio = NULL; +} + +static const struct of_device_id rp1_pio_ids[] = { + { .compatible = "raspberrypi,rp1-pio" }, + { } +}; +MODULE_DEVICE_TABLE(of, rp1_pio_ids); + +static struct platform_driver rp1_pio_driver = { + .driver = { + .name = "rp1-pio", + .of_match_table = of_match_ptr(rp1_pio_ids), + }, + .probe = rp1_pio_probe, + .remove = rp1_pio_remove, + .shutdown = rp1_pio_remove, +}; + +module_platform_driver(rp1_pio_driver); + +MODULE_DESCRIPTION("PIO controller driver for Raspberry Pi RP1"); +MODULE_AUTHOR("Phil Elwell"); +MODULE_LICENSE("GPL"); diff --git a/drivers/misc/ws2812-pio-rp1.c b/drivers/misc/ws2812-pio-rp1.c new file mode 100644 index 000000000000..23b7028868aa --- /dev/null +++ b/drivers/misc/ws2812-pio-rp1.c @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Raspberry Pi PIO-based WS2812 driver + * + * Copyright (C) 2014-2024 Raspberry Pi Ltd. + * + * Author: Phil Elwell ([email protected]) + * + * Based on the ws2812 driver by Gordon Hollingworth <[email protected]> + */ + +#include <linux/cdev.h> +#include <linux/delay.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/fcntl.h> +#include <linux/file.h> +#include <linux/fs.h> +#include <linux/pio_rp1.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/gpio/consumer.h> + +#define DRIVER_NAME "ws2812-pio-rp1" +#define MAX_INSTANCES 4 + +#define RESET_US 50 +#define PIXEL_BYTES 4 + +struct ws2812_pio_rp1_state { + struct device *dev; + struct gpio_desc *gpiod; + struct gpio_desc *power_gpiod; + uint gpio; + PIO pio; + uint sm; + uint offset; + + u8 *buffer; + u8 *pixbuf; + u32 pixbuf_size; + u32 write_end; + + u8 brightness; + u32 invert; + u32 num_leds; + u32 xfer_end_us; + bool is_rgbw; + struct delayed_work deferred_work; + + struct completion dma_completion; + struct cdev cdev; + dev_t dev_num; + const char *dev_name; +}; + +static DEFINE_MUTEX(ws2812_pio_mutex); +static DEFINE_IDA(ws2812_pio_ida); +static long ws2812_pio_ref_count; +static struct class *ws2812_pio_class; +static dev_t ws2812_pio_dev_num; +/* + * WS2812B gamma correction + * GammaE=255*(res/255).^(1/.45) + * From: http://rgb-123.com/ws2812-color-output/ + */ + +static const u8 ws2812_gamma[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, + 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, + 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, + 11, 12, 12, 13, 13, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, + 19, 19, 20, 21, 21, 22, 22, 23, 23, 24, 25, 25, 26, 27, 27, 28, + 29, 29, 30, 31, 31, 32, 33, 34, 34, 35, 36, 37, 37, 38, 39, 40, + 40, 41, 42, 43, 44, 45, 46, 46, 47, 48, 49, 50, 51, 52, 53, 54, + 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, + 71, 72, 73, 74, 76, 77, 78, 79, 80, 81, 83, 84, 85, 86, 88, 89, + 90, 91, 93, 94, 95, 96, 98, 99, 100, 102, 103, 104, 106, 107, 109, 110, + 111, 113, 114, 116, 117, 119, 120, 121, 123, 124, 126, 128, 129, 131, 132, 134, + 135, 137, 138, 140, 142, 143, 145, 146, 148, 150, 151, 153, 155, 157, 158, 160, + 162, 163, 165, 167, 169, 170, 172, 174, 176, 178, 179, 181, 183, 185, 187, 189, + 191, 193, 194, 196, 198, 200, 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, + 222, 224, 227, 229, 231, 233, 235, 237, 239, 241, 244, 246, 248, 250, 252, 255 +}; + +// ------ // +// ws2812 // +// ------ // + +#define ws2812_wrap_target 0 +#define ws2812_wrap 3 + +#define ws2812_T1 3 +#define ws2812_T2 4 +#define ws2812_T3 3 + +static const uint16_t ws2812_program_instructions[] = { + // .wrap_target + 0x6221, // 0: out x, 1 side 0 [2] + 0x1223, // 1: jmp !x, 3 side 1 [2] + 0x1300, // 2: jmp 0 side 1 [3] + 0xa342, // 3: nop side 0 [3] + // .wrap +}; + +static const struct pio_program ws2812_program = { + .instructions = ws2812_program_instructions, + .length = 4, + .origin = -1, +}; + +static inline pio_sm_config ws2812_program_get_default_config(uint offset) +{ + pio_sm_config c = pio_get_default_sm_config(); + + sm_config_set_wrap(&c, offset + ws2812_wrap_target, offset + ws2812_wrap); + sm_config_set_sideset(&c, 1, false, false); + return c; +} + +static inline void ws2812_program_init(PIO pio, uint sm, uint offset, uint pin, uint freq, + bool rgbw) +{ + int cycles_per_bit = ws2812_T1 + ws2812_T2 + ws2812_T3; + struct fp24_8 div; + pio_sm_config c; + + pio_gpio_init(pio, pin); + pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true); + c = ws2812_program_get_default_config(offset); + sm_config_set_sideset_pins(&c, pin); + sm_config_set_out_shift(&c, false, true, rgbw ? 32 : 24); + sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX); + div = make_fp24_8(clock_get_hz(clk_sys), freq * cycles_per_bit); + sm_config_set_clkdiv(&c, div); + pio_sm_init(pio, sm, offset, &c); + pio_sm_set_enabled(pio, sm, true); +} + +static uint8_t ws2812_apply_gamma(uint8_t brightness, uint8_t val) +{ + int bright; + + if (!val) + return 0; + bright = (val * brightness) / 255; + return ws2812_gamma[bright]; +} + +static inline uint8_t *rgbw_u32(const struct ws2812_pio_rp1_state *state, + uint8_t r, uint8_t g, uint8_t b, uint8_t w, uint8_t *p) +{ + p[0] = ws2812_apply_gamma(state->brightness, w); + p[1] = ws2812_apply_gamma(state->brightness, b); + p[2] = ws2812_apply_gamma(state->brightness, r); + p[3] = ws2812_apply_gamma(state->brightness, g); + return p + 4; +} + +static void ws2812_dma_complete(void *param) +{ + struct ws2812_pio_rp1_state *state = param; + + complete(&state->dma_completion); +} + +static void ws2812_update_leds(struct ws2812_pio_rp1_state *state, uint length) +{ + init_completion(&state->dma_completion); + if (!pio_sm_xfer_data(state->pio, state->sm, PIO_DIR_TO_SM, length, state->buffer, 0, + (void (*)(void *))ws2812_dma_complete, state)) { + wait_for_completion(&state->dma_completion); + usleep_range(RESET_US, RESET_US + 100); + } +} + +static void ws2812_clear_leds(struct ws2812_pio_rp1_state *state) +{ + uint8_t *p_buffer; + uint length; + int i; + + p_buffer = state->buffer; + for (i = 0; i < state->num_leds; i++) + p_buffer = rgbw_u32(state, 0, 0, 0, 0, p_buffer); + + length = (void *)p_buffer - (void *)state->buffer; + + ws2812_update_leds(state, length); +} + +/* + * Function to write the RGB buffer to the WS2812 leds, the input buffer + * contains a sequence of up to num_leds RGB32 integers, these are then + * gamma-corrected before being sent to the PIO state machine. + */ + +static ssize_t ws2812_pio_rp1_write(struct file *filp, const char __user *buf, size_t count, + loff_t *ppos) +{ + struct ws2812_pio_rp1_state *state; + uint32_t pixbuf_size; + unsigned long delay; + loff_t pos = *ppos; + int err = 0; + + state = (struct ws2812_pio_rp1_state *)filp->private_data; + pixbuf_size = state->pixbuf_size; + + if (pos > pixbuf_size) + return -EFBIG; + + if (count > pixbuf_size) { + err = -EFBIG; + count = pixbuf_size; + } + + if (pos + count > pixbuf_size) { + if (!err) + err = -ENOSPC; + + count = pixbuf_size - pos; + } + + if (!pos && count == 1) { + if (copy_from_user(&state->brightness, buf, 1)) + return -EFAULT; + } else { + if (copy_from_user(state->pixbuf + pos, buf, count)) + return -EFAULT; + pos += count; + state->write_end = (u32)pos; + } + + *ppos = pos; + + delay = (state->write_end == pixbuf_size) ? 0 : HZ / 20; + schedule_delayed_work(&state->deferred_work, delay); + + return err ? err : count; +} + +static void ws2812_pio_rp1_deferred_work(struct work_struct *work) +{ + struct ws2812_pio_rp1_state *state = + container_of(work, struct ws2812_pio_rp1_state, deferred_work.work); + uint8_t *p_buffer; + uint32_t *p_rgb; + int blank_bytes; + uint length; + int i; + + blank_bytes = state->pixbuf_size - state->write_end; + if (blank_bytes > 0) + memset(state->pixbuf + state->write_end, 0, blank_bytes); + + p_rgb = (uint32_t *)state->pixbuf; + p_buffer = state->buffer; + + for (i = 0; i < state->num_leds; i++) { + uint32_t rgbw_pix = *(p_rgb++); + + p_buffer = rgbw_u32(state, + (uint8_t)(rgbw_pix >> 0), + (uint8_t)(rgbw_pix >> 8), + (uint8_t)(rgbw_pix >> 16), + (uint8_t)(rgbw_pix >> 24), + p_buffer); + } + + length = (void *)p_buffer - (void *)state->buffer; + + ws2812_update_leds(state, length); +} + +static int ws2812_pio_rp1_open(struct inode *inode, struct file *file) +{ + struct ws2812_pio_rp1_state *state; + + state = container_of(inode->i_cdev, struct ws2812_pio_rp1_state, cdev); + file->private_data = state; + + return 0; +} + +const struct file_operations ws2812_pio_rp1_fops = { + .owner = THIS_MODULE, + .write = ws2812_pio_rp1_write, + .open = ws2812_pio_rp1_open, +}; + +/* + * Probe function + */ +static int ws2812_pio_rp1_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct of_phandle_args of_args = { 0 }; + struct ws2812_pio_rp1_state *state; + struct device *dev = &pdev->dev; + struct device *char_dev; + const char *dev_name; + uint32_t brightness; + bool is_rp1; + int minor; + int ret; + + state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); + if (IS_ERR(state)) + return PTR_ERR(state); + + state->dev = dev; + + platform_set_drvdata(pdev, state); + + ret = of_property_read_u32(np, "rpi,num-leds", &state->num_leds); + if (ret) + return dev_err_probe(dev, ret, "Could not get num-leds\n"); + + brightness = 255; + of_property_read_u32(np, "rpi,brightness", &brightness); + state->brightness = min(brightness, 255); + + state->pixbuf_size = state->num_leds * PIXEL_BYTES; + + state->is_rgbw = of_property_read_bool(np, "rpi,rgbw"); + state->gpiod = devm_gpiod_get(dev, "leds", GPIOD_ASIS); + if (IS_ERR(state->gpiod)) + return dev_err_probe(dev, PTR_ERR(state->gpiod), + "Could not get a gpio\n"); + + /* This must be an RP1 GPIO in the first bank, and retrieve the offset. */ + /* Unfortunately I think this has to be done by parsing the gpios property */ + + /* This really shouldn't fail, given that we have a gpiod */ + if (of_parse_phandle_with_args(np, "leds-gpios", "#gpio-cells", 0, &of_args)) + return dev_err_probe(dev, -EINVAL, + "Can't find gpio declaration\n"); + + is_rp1 = of_device_is_compatible(of_args.np, "raspberrypi,rp1-gpio"); + of_node_put(of_args.np); + if (!is_rp1 || of_args.args_count != 2) + return dev_err_probe(dev, -EINVAL, + "Not an RP1 gpio\n"); + + state->gpio = of_args.args[0]; + + state->pixbuf = devm_kmalloc(dev, state->pixbuf_size, GFP_KERNEL); + if (state->pixbuf == NULL) + return -ENOMEM; + + state->buffer = devm_kmalloc(dev, state->num_leds * PIXEL_BYTES, GFP_KERNEL); + if (state->buffer == NULL) + return -ENOMEM; + + ret = of_property_read_string(np, "dev-name", &dev_name); + if (ret) { + pr_err("Failed to read 'dev-name' property\n"); + return ret; + } + + state->pio = pio_open(); + if (IS_ERR(state->pio)) + return dev_err_probe(dev, PTR_ERR(state->pio), + "Could not open PIO\n"); + + state->sm = pio_claim_unused_sm(state->pio, false); + if ((int)state->sm < 0) { + dev_err(dev, "No free PIO SM\n"); + ret = -EBUSY; + goto fail_pio; + } + + state->offset = pio_add_program(state->pio, &ws2812_program); + if (state->offset == PIO_ORIGIN_ANY) { + dev_err(dev, "Not enough PIO program space\n"); + ret = -EBUSY; + goto fail_pio; + } + + pio_sm_config_xfer(state->pio, state->sm, PIO_DIR_TO_SM, state->num_leds * sizeof(int), 1); + + pio_sm_clear_fifos(state->pio, state->sm); + pio_sm_set_clkdiv(state->pio, state->sm, make_fp24_8(1, 1)); + ws2812_program_init(state->pio, state->sm, state->offset, state->gpio, 800000, + state->is_rgbw); + + mutex_lock(&ws2812_pio_mutex); + + if (!ws2812_pio_ref_count) { + ret = alloc_chrdev_region(&ws2812_pio_dev_num, 0, MAX_INSTANCES, DRIVER_NAME); + if (ret < 0) { + dev_err(dev, "alloc_chrdev_region failed (rc=%d)\n", ret); + goto fail_mutex; + } + + ws2812_pio_class = class_create(DRIVER_NAME); + if (IS_ERR(ws2812_pio_class)) { + pr_err("Unable to create class " DRIVER_NAME "\n"); + ret = PTR_ERR(ws2812_pio_class); + goto fail_chrdev; + } + } + + ws2812_pio_ref_count++; + + minor = ida_alloc_range(&ws2812_pio_ida, 0, MAX_INSTANCES - 1, GFP_KERNEL); + if (minor < 0) { + pr_err("No free instances\n"); + ret = minor; + goto fail_class; + + } + + mutex_unlock(&ws2812_pio_mutex); + + state->dev_num = MKDEV(MAJOR(ws2812_pio_dev_num), minor); + state->dev_name = devm_kasprintf(dev, GFP_KERNEL, dev_name, minor); + + char_dev = device_create(ws2812_pio_class, NULL, state->dev_num, NULL, state->dev_name); + + if (IS_ERR(char_dev)) { + pr_err("Unable to create device %s\n", state->dev_name); + ret = PTR_ERR(char_dev); + goto fail_ida; + } + + state->cdev.owner = THIS_MODULE; + cdev_init(&state->cdev, &ws2812_pio_rp1_fops); + + ret = cdev_add(&state->cdev, state->dev_num, 1); + if (ret) { + pr_err("cdev_add failed\n"); + goto fail_device; + } + + INIT_DELAYED_WORK(&state->deferred_work, ws2812_pio_rp1_deferred_work); + + ws2812_clear_leds(state); + + dev_info(&pdev->dev, "Instantiated %d LEDs on GPIO %d as /dev/%s\n", + state->num_leds, state->gpio, state->dev_name); + + return 0; + +fail_device: + device_destroy(ws2812_pio_class, state->dev_num); +fail_ida: + mutex_lock(&ws2812_pio_mutex); + ida_free(&ws2812_pio_ida, minor); +fail_class: + ws2812_pio_ref_count--; + if (ws2812_pio_ref_count) + goto fail_mutex; + class_destroy(ws2812_pio_class); +fail_chrdev: + unregister_chrdev_region(ws2812_pio_dev_num, MAX_INSTANCES); +fail_mutex: + mutex_unlock(&ws2812_pio_mutex); +fail_pio: + pio_close(state->pio); + + return ret; +} + +static void ws2812_pio_rp1_remove(struct platform_device *pdev) +{ + struct ws2812_pio_rp1_state *state = platform_get_drvdata(pdev); + + cancel_delayed_work(&state->deferred_work); + platform_set_drvdata(pdev, NULL); + + cdev_del(&state->cdev); + device_destroy(ws2812_pio_class, state->dev_num); + + mutex_lock(&ws2812_pio_mutex); + ida_free(&ws2812_pio_ida, MINOR(state->dev_num)); + ws2812_pio_ref_count--; + if (!ws2812_pio_ref_count) { + class_destroy(ws2812_pio_class); + unregister_chrdev_region(ws2812_pio_dev_num, MAX_INSTANCES); + } + mutex_unlock(&ws2812_pio_mutex); + + pio_close(state->pio); +} + +static const struct of_device_id ws2812_pio_rp1_match[] = { + { .compatible = "raspberrypi,ws2812-pio-rp1" }, + { } +}; +MODULE_DEVICE_TABLE(of, ws2812_pio_rp1_match); + +static struct platform_driver ws2812_pio_rp1_driver = { + .driver = { + .name = "ws2812-pio-rp1", + .of_match_table = ws2812_pio_rp1_match, + }, + .probe = ws2812_pio_rp1_probe, + .remove = ws2812_pio_rp1_remove, +}; +module_platform_driver(ws2812_pio_rp1_driver); + +MODULE_DESCRIPTION("WS2812 PIO RP1 driver"); +MODULE_AUTHOR("Phil Elwell"); +MODULE_LICENSE("GPL"); |