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path: root/drivers/gpu/drm/i915/display/intel_hdmi.c
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Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_hdmi.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_hdmi.c10
1 files changed, 0 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index a0133713725b..95584b61cf08 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1909,16 +1909,6 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800)
return MODE_CLOCK_RANGE;
- /*
- * SNPS PHYs' MPLLB table-based programming can only handle a fixed
- * set of link rates.
- *
- * FIXME: We will hopefully get an algorithmic way of programming
- * the MPLLB for HDMI in the future.
- */
- if (DISPLAY_VER(display) >= 14)
- return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock);
-
return MODE_OK;
}