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| author | Bhargava Chenna Marreddy <[email protected]> | 2024-10-08 07:41:41 +0000 |
|---|---|---|
| committer | Jason Gunthorpe <[email protected]> | 2024-10-11 23:49:02 +0000 |
| commit | 7988bdbbb85ac85a847baf09879edcd0f70521dc (patch) | |
| tree | 9abfbb7aa781cd9c978adad5b62e4e121b44c7fe /tools/testing/selftests/net/lib/py/nsim.py | |
| parent | RDMA/bnxt_re: Change the sequence of updating the CQ toggle value (diff) | |
| download | kernel-7988bdbbb85ac85a847baf09879edcd0f70521dc.tar.gz kernel-7988bdbbb85ac85a847baf09879edcd0f70521dc.zip | |
RDMA/bnxt_re: Fix a bug while setting up Level-2 PBL pages
Avoid memory corruption while setting up Level-2 PBL pages for the non MR
resources when num_pages > 256K.
There will be a single PDE page address (contiguous pages in the case of >
PAGE_SIZE), but, current logic assumes multiple pages, leading to invalid
memory access after 256K PBL entries in the PDE.
Fixes: 0c4dcd602817 ("RDMA/bnxt_re: Refactor hardware queue memory allocation")
Link: https://patch.msgid.link/r/[email protected]
Signed-off-by: Bhargava Chenna Marreddy <[email protected]>
Signed-off-by: Selvin Xavier <[email protected]>
Signed-off-by: Jason Gunthorpe <[email protected]>
Diffstat (limited to 'tools/testing/selftests/net/lib/py/nsim.py')
0 files changed, 0 insertions, 0 deletions