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| author | Jakub Kicinski <[email protected]> | 2025-07-10 02:08:56 +0000 |
|---|---|---|
| committer | Jakub Kicinski <[email protected]> | 2025-07-10 02:08:57 +0000 |
| commit | 11b5d56d37f2fe6b093f5b4599370f21a33b6409 (patch) | |
| tree | 5823a7fa0d2c9d5a4e7d7e84f594e8133d482edf /tools/testing/selftests/drivers/net/hw/rss_api.py | |
| parent | virtio-net: xsk: rx: move the xdp->data adjustment to buf_to_xdp() (diff) | |
| parent | dpll: zl3073x: Add support to get/set frequency on pins (diff) | |
| download | kernel-11b5d56d37f2fe6b093f5b4599370f21a33b6409.tar.gz kernel-11b5d56d37f2fe6b093f5b4599370f21a33b6409.zip | |
Merge branch 'add-microchip-zl3073x-support-part-1'
Ivan Vecera says:
====================
Add Microchip ZL3073x support (part 1)
Add support for Microchip Azurite DPLL/PTP/SyncE chip family that
provides DPLL and PTP functionality. This series bring first part
that adds the core functionality and basic DPLL support.
The next part of the series will bring additional DPLL functionality
like eSync support, phase offset and frequency offset reporting and
phase adjustments.
Testing was done by myself and by Prathosh Satish on Microchip EDS2
development board with ZL30732 DPLL chip connected over I2C bus.
====================
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Jakub Kicinski <[email protected]>
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