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| author | Andi Kleen <[email protected]> | 2011-03-03 02:34:48 +0000 |
|---|---|---|
| committer | Ingo Molnar <[email protected]> | 2011-03-04 10:32:53 +0000 |
| commit | e994d7d23a0bae34cd28834e85522ed4e782faf7 (patch) | |
| tree | f9b08a69bdccf047cba9449adee4dd86ed1e8892 /tools/perf/util/trace-event-scripting.c | |
| parent | perf: Add support for supplementary event registers (diff) | |
| download | kernel-e994d7d23a0bae34cd28834e85522ed4e782faf7.tar.gz kernel-e994d7d23a0bae34cd28834e85522ed4e782faf7.zip | |
perf: Fix LLC-* events on Intel Nehalem/Westmere
On Intel Nehalem and Westmere CPUs the generic perf LLC-* events count the
L2 caches, not the real L3 LLC - this was inconsistent with behavior on
other CPUs.
Fixing this requires the use of the special OFFCORE_RESPONSE
events which need a separate mask register.
This has been implemented by the previous patch, now use this infrastructure
to set correct events for the LLC-* on Nehalem and Westmere.
Signed-off-by: Andi Kleen <[email protected]>
Signed-off-by: Lin Ming <[email protected]>
Signed-off-by: Peter Zijlstra <[email protected]>
LKML-Reference: <[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>
Diffstat (limited to 'tools/perf/util/trace-event-scripting.c')
0 files changed, 0 insertions, 0 deletions