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| author | Kan Liang <[email protected]> | 2022-03-28 15:49:03 +0000 |
|---|---|---|
| committer | Peter Zijlstra <[email protected]> | 2022-04-05 07:59:44 +0000 |
| commit | e590928de7547454469693da9bc7ffd562e54b7e (patch) | |
| tree | 6ca3d5e4bb1f46152e815b09f3501b7a38a4c45f /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | perf/x86/intel: Don't extend the pseudo-encoding to GP counters (diff) | |
| download | kernel-e590928de7547454469693da9bc7ffd562e54b7e.tar.gz kernel-e590928de7547454469693da9bc7ffd562e54b7e.zip | |
perf/x86/intel: Update the FRONTEND MSR mask on Sapphire Rapids
On Sapphire Rapids, the FRONTEND_RETIRED.MS_FLOWS event requires the
FRONTEND MSR value 0x8. However, the current FRONTEND MSR mask doesn't
support it.
Update intel_spr_extra_regs[] to support it.
Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by: Kan Liang <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Cc: [email protected]
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions