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authorMauro Lima <[email protected]>2022-10-12 15:21:35 +0000
committerMark Brown <[email protected]>2022-10-13 12:01:37 +0000
commit6a43cd02ddbc597dc9a1f82c1e433f871a2f6f06 (patch)
treeaefb6073741de020f21d9d039982cc7442659276 /tools/perf/util/scripting-engines/trace-event-perl.c
parentspi: aspeed: Fix typo in mode_bits field for AST2600 platform (diff)
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spi: intel: Fix the offset to get the 64K erase opcode
According to documentation, the 64K erase opcode is located in VSCC range [16:23] instead of [8:15]. Use the proper value to shift the mask over the correct range. Signed-off-by: Mauro Lima <[email protected]> Reviewed-by: Mika Westerberg <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
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