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| author | Reinette Chatre <[email protected]> | 2018-06-22 22:42:29 +0000 |
|---|---|---|
| committer | Thomas Gleixner <[email protected]> | 2018-06-24 13:35:48 +0000 |
| commit | f3be1e7b2cf8bc096386a3588fc640b0db6b28d7 (patch) | |
| tree | 28024ec800ab578d0c5419706f805723d2ca3fc3 /tools/perf/scripts/python | |
| parent | x86/intel_rdt: More precise L2 hit/miss measurements (diff) | |
| download | kernel-f3be1e7b2cf8bc096386a3588fc640b0db6b28d7.tar.gz kernel-f3be1e7b2cf8bc096386a3588fc640b0db6b28d7.zip | |
x86/intel_rdt: Support L3 cache performance event of Broadwell
Broadwell microarchitecture supports pseudo-locking. Add support for
the L3 cache related performance events of these systems so that
the success of pseudo-locking can be measured more accurately on these
platforms.
Signed-off-by: Reinette Chatre <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Link: https://lkml.kernel.org/r/36c1414e9bd17c3faf440f32b644b9c879bcbae2.1529706536.git.reinette.chatre@intel.com
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