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authorAlexandre Ghiti <[email protected]>2023-07-25 13:22:46 +0000
committerPalmer Dabbelt <[email protected]>2023-08-10 15:54:29 +0000
commit7e3811521dc3934e2ecae8458676fc4a1f62bf9f (patch)
treea804c8230adc9cd8b1dbad23a1973b1db7ee4467 /tools/perf/scripts/python/task-analyzer.py
parentriscv: Do not allow vmap pud mappings for 3-level page table (diff)
downloadkernel-7e3811521dc3934e2ecae8458676fc4a1f62bf9f.tar.gz
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riscv: Implement flush_cache_vmap()
The RISC-V kernel needs a sfence.vma after a page table modification: we used to rely on the vmalloc fault handling to emit an sfence.vma, but commit 7d3332be011e ("riscv: mm: Pre-allocate PGD entries for vmalloc/modules area") got rid of this path for 64-bit kernels, so now we need to explicitly emit a sfence.vma in flush_cache_vmap(). Note that we don't need to implement flush_cache_vunmap() as the generic code should emit a flush tlb after unmapping a vmalloc region. Fixes: 7d3332be011e ("riscv: mm: Pre-allocate PGD entries for vmalloc/modules area") Signed-off-by: Alexandre Ghiti <[email protected]> Link: https://lore.kernel.org/r/[email protected] Cc: [email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
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